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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-05 11:14:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:48 -0400
commita09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch)
tree69689f467179891b498bd7423fcf61925173db31 /include/asm-arm/arch-orion5x
parenta1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff)
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-orion5x')
-rw-r--r--include/asm-arm/arch-orion5x/debug-macro.S22
-rw-r--r--include/asm-arm/arch-orion5x/dma.h1
-rw-r--r--include/asm-arm/arch-orion5x/entry-macro.S31
-rw-r--r--include/asm-arm/arch-orion5x/gpio.h28
-rw-r--r--include/asm-arm/arch-orion5x/hardware.h21
-rw-r--r--include/asm-arm/arch-orion5x/io.h63
-rw-r--r--include/asm-arm/arch-orion5x/irqs.h62
-rw-r--r--include/asm-arm/arch-orion5x/memory.h16
-rw-r--r--include/asm-arm/arch-orion5x/orion5x.h162
-rw-r--r--include/asm-arm/arch-orion5x/system.h32
-rw-r--r--include/asm-arm/arch-orion5x/timex.h13
-rw-r--r--include/asm-arm/arch-orion5x/uncompress.h49
-rw-r--r--include/asm-arm/arch-orion5x/vmalloc.h5
13 files changed, 0 insertions, 505 deletions
diff --git a/include/asm-arm/arch-orion5x/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
deleted file mode 100644
index 4f98f3ba2929..000000000000
--- a/include/asm-arm/arch-orion5x/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <asm/arch/orion5x.h>
12
13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =ORION5X_REGS_PHYS_BASE
17 ldrne \rx, =ORION5X_REGS_VIRT_BASE
18 orr \rx, \rx, #0x00012000
19 .endm
20
21#define UART_SHIFT 2
22#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion5x/dma.h b/include/asm-arm/arch-orion5x/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/include/asm-arm/arch-orion5x/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/include/asm-arm/arch-orion5x/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
deleted file mode 100644
index d8ef54c0ee9a..000000000000
--- a/include/asm-arm/arch-orion5x/entry-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Orion platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/orion5x.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =MAIN_IRQ_CAUSE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #0] @ main cause
25 ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
26 mov \irqnr, #0 @ default irqnr
27 @ find cause bits that are unmasked
28 ands \irqstat, \irqstat, \tmp @ clear Z flag if any
29 clzne \irqnr, \irqstat @ calc irqnr
30 rsbne \irqnr, \irqnr, #31
31 .endm
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
deleted file mode 100644
index c85e498388b6..000000000000
--- a/include/asm-arm/arch-orion5x/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/gpio.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9extern int gpio_request(unsigned pin, const char *label);
10extern void gpio_free(unsigned pin);
11extern int gpio_direction_input(unsigned pin);
12extern int gpio_direction_output(unsigned pin, int value);
13extern int gpio_get_value(unsigned pin);
14extern void gpio_set_value(unsigned pin, int value);
15extern void orion5x_gpio_set_blink(unsigned pin, int blink);
16extern void gpio_display(void); /* debug */
17
18static inline int gpio_to_irq(int pin)
19{
20 return pin + IRQ_ORION5X_GPIO_START;
21}
22
23static inline int irq_to_gpio(int irq)
24{
25 return irq - IRQ_ORION5X_GPIO_START;
26}
27
28#include <asm-generic/gpio.h> /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion5x/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
deleted file mode 100644
index 5d2d8e0b5630..000000000000
--- a/include/asm-arm/arch-orion5x/hardware.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "orion5x.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE
19
20
21#endif
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
deleted file mode 100644
index 59f1bc96a23b..000000000000
--- a/include/asm-arm/arch-orion5x/io.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/io.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H
13
14#include "orion5x.h"
15
16#define IO_SPACE_LIMIT 0xffffffff
17
18static inline void __iomem *
19__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
20{
21 void __iomem *retval;
22 unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
23 if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
24 size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
25 retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
26 } else {
27 retval = __arm_ioremap(paddr, size, mtype);
28 }
29
30 return retval;
31}
32
33static inline void
34__arch_iounmap(void __iomem *addr)
35{
36 if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
37 addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
38 __iounmap(addr);
39}
40
41static inline void __iomem *__io(unsigned long addr)
42{
43 return (void __iomem *)addr;
44}
45
46#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
47#define __arch_iounmap(a) __arch_iounmap(a)
48#define __io(a) __io(a)
49#define __mem_pci(a) (a)
50
51
52/*****************************************************************************
53 * Helpers to access Orion registers
54 ****************************************************************************/
55/*
56 * These are not preempt-safe. Locks, if needed, must be taken
57 * care of by the caller.
58 */
59#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
60#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
61
62
63#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
deleted file mode 100644
index abdd61a4833a..000000000000
--- a/include/asm-arm/arch-orion5x/irqs.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/irqs.h
3 *
4 * IRQ definitions for Orion SoC
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H
15
16#include "orion5x.h" /* need GPIO_MAX */
17
18/*
19 * Orion Main Interrupt Controller
20 */
21#define IRQ_ORION5X_BRIDGE 0
22#define IRQ_ORION5X_DOORBELL_H2C 1
23#define IRQ_ORION5X_DOORBELL_C2H 2
24#define IRQ_ORION5X_UART0 3
25#define IRQ_ORION5X_UART1 4
26#define IRQ_ORION5X_I2C 5
27#define IRQ_ORION5X_GPIO_0_7 6
28#define IRQ_ORION5X_GPIO_8_15 7
29#define IRQ_ORION5X_GPIO_16_23 8
30#define IRQ_ORION5X_GPIO_24_31 9
31#define IRQ_ORION5X_PCIE0_ERR 10
32#define IRQ_ORION5X_PCIE0_INT 11
33#define IRQ_ORION5X_USB1_CTRL 12
34#define IRQ_ORION5X_DEV_BUS_ERR 14
35#define IRQ_ORION5X_PCI_ERR 15
36#define IRQ_ORION5X_USB_BR_ERR 16
37#define IRQ_ORION5X_USB0_CTRL 17
38#define IRQ_ORION5X_ETH_RX 18
39#define IRQ_ORION5X_ETH_TX 19
40#define IRQ_ORION5X_ETH_MISC 20
41#define IRQ_ORION5X_ETH_SUM 21
42#define IRQ_ORION5X_ETH_ERR 22
43#define IRQ_ORION5X_IDMA_ERR 23
44#define IRQ_ORION5X_IDMA_0 24
45#define IRQ_ORION5X_IDMA_1 25
46#define IRQ_ORION5X_IDMA_2 26
47#define IRQ_ORION5X_IDMA_3 27
48#define IRQ_ORION5X_CESA 28
49#define IRQ_ORION5X_SATA 29
50#define IRQ_ORION5X_XOR0 30
51#define IRQ_ORION5X_XOR1 31
52
53/*
54 * Orion General Purpose Pins
55 */
56#define IRQ_ORION5X_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX
58
59#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
60
61
62#endif
diff --git a/include/asm-arm/arch-orion5x/memory.h b/include/asm-arm/arch-orion5x/memory.h
deleted file mode 100644
index 80053a7afc7a..000000000000
--- a/include/asm-arm/arch-orion5x/memory.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/memory.h
3 *
4 * Marvell Orion memory definitions
5 */
6
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#define PHYS_OFFSET UL(0x00000000)
11
12#define __virt_to_bus(x) __virt_to_phys(x)
13#define __bus_to_virt(x) __phys_to_virt(x)
14
15
16#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
deleted file mode 100644
index 10257f5c5e9e..000000000000
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/orion5x.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION5X_H
15#define __ASM_ARCH_ORION5X_H
16
17/*****************************************************************************
18 * Orion Address Maps
19 *
20 * phys
21 * e0000000 PCIe MEM space
22 * e8000000 PCI MEM space
23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only)
24 * f1000000 on-chip peripheral registers
25 * f2000000 PCIe I/O space
26 * f2100000 PCI I/O space
27 * f4000000 device bus mappings (boot)
28 * fa000000 device bus mappings (cs0)
29 * fa800000 device bus mappings (cs2)
30 * fc000000 device bus mappings (cs0/cs1)
31 *
32 * virt phys size
33 * fdd00000 f1000000 1M on-chip peripheral registers
34 * fde00000 f2000000 1M PCIe I/O space
35 * fdf00000 f2100000 1M PCI I/O space
36 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
37 ****************************************************************************/
38#define ORION5X_REGS_PHYS_BASE 0xf1000000
39#define ORION5X_REGS_VIRT_BASE 0xfdd00000
40#define ORION5X_REGS_SIZE SZ_1M
41
42#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
43#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
44#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
45#define ORION5X_PCIE_IO_SIZE SZ_1M
46
47#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
48#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
49#define ORION5X_PCI_IO_BUS_BASE 0x00100000
50#define ORION5X_PCI_IO_SIZE SZ_1M
51
52/* Relevant only for Orion-1/Orion-NAS */
53#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
54#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
55#define ORION5X_PCIE_WA_SIZE SZ_16M
56
57#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
58#define ORION5X_PCIE_MEM_SIZE SZ_128M
59
60#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
61#define ORION5X_PCI_MEM_SIZE SZ_128M
62
63/*******************************************************************************
64 * Supported Devices & Revisions
65 ******************************************************************************/
66/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
67#define MV88F5181_DEV_ID 0x5181
68#define MV88F5181_REV_B1 3
69#define MV88F5181L_REV_A0 8
70#define MV88F5181L_REV_A1 9
71/* Orion-NAS (88F5182) */
72#define MV88F5182_DEV_ID 0x5182
73#define MV88F5182_REV_A2 2
74/* Orion-2 (88F5281) */
75#define MV88F5281_DEV_ID 0x5281
76#define MV88F5281_REV_D1 5
77#define MV88F5281_REV_D2 6
78
79/*******************************************************************************
80 * Orion Registers Map
81 ******************************************************************************/
82#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
83#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
84
85#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
86#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
87#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
88#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
89#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
90#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
91#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
92#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
93
94#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
95#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
96#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
97
98#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
99#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
100
101#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
102#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
103
104#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
105#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
106#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
107
108#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
109#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
110#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
111
112#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
113#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
114#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
115
116#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
117#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
118#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
119
120/*******************************************************************************
121 * Device Bus Registers
122 ******************************************************************************/
123#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
124#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
125#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
126#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
127#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
128#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100)
129#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104)
130#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108)
131#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c)
132#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110)
133#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
134#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
135#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
136#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
137#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
138#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
139#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
140#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
141#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
142#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
143#define GPIO_MAX 32
144
145/***************************************************************************
146 * Orion CPU Bridge Registers
147 **************************************************************************/
148#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
149#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
150#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
151#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
152#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
153#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
154#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
155#define BRIDGE_INT_TIMER0 0x0002
156#define BRIDGE_INT_TIMER1 0x0004
157#define BRIDGE_INT_TIMER1_CLR (~0x0004)
158#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
159#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
160
161
162#endif
diff --git a/include/asm-arm/arch-orion5x/system.h b/include/asm-arm/arch-orion5x/system.h
deleted file mode 100644
index 3f1d1e2d38f8..000000000000
--- a/include/asm-arm/arch-orion5x/system.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/system.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14#include <asm/arch/hardware.h>
15#include <asm/arch/orion5x.h>
16
17static inline void arch_idle(void)
18{
19 cpu_do_idle();
20}
21
22static inline void arch_reset(char mode)
23{
24 /*
25 * Enable and issue soft reset
26 */
27 orion5x_setbits(CPU_RESET_MASK, (1 << 2));
28 orion5x_setbits(CPU_SOFT_RESET, 1);
29}
30
31
32#endif
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h
deleted file mode 100644
index 31c568e28cc3..000000000000
--- a/include/asm-arm/arch-orion5x/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/timex.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#define CLOCK_TICK_RATE (100 * HZ)
12
13#define ORION5X_TCLK 166666667
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
deleted file mode 100644
index 7548cedf2d76..000000000000
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/uncompress.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/serial_reg.h>
12#include <asm/arch/orion5x.h>
13
14#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
15
16static void putc(const char c)
17{
18 unsigned char *base = SERIAL_BASE;
19 int i;
20
21 for (i = 0; i < 0x1000; i++) {
22 if (base[UART_LSR << 2] & UART_LSR_THRE)
23 break;
24 barrier();
25 }
26
27 base[UART_TX << 2] = c;
28}
29
30static void flush(void)
31{
32 unsigned char *base = SERIAL_BASE;
33 unsigned char mask;
34 int i;
35
36 mask = UART_LSR_TEMT | UART_LSR_THRE;
37
38 for (i = 0; i < 0x1000; i++) {
39 if ((base[UART_LSR << 2] & mask) == mask)
40 break;
41 barrier();
42 }
43}
44
45/*
46 * nothing to do
47 */
48#define arch_decomp_setup()
49#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion5x/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
deleted file mode 100644
index 2b3061e90dc1..000000000000
--- a/include/asm-arm/arch-orion5x/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * include/asm-arm/arch-orion5x/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfd800000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 18:07:37 -0500