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authorIngo Molnar <mingo@elte.hu>2008-07-15 18:29:07 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-15 18:29:07 -0400
commit82638844d9a8581bbf33201cc209a14876eca167 (patch)
tree961d7f9360194421a71aa644a9d0c176a960ce49 /include/asm-arm/arch-omap
parent9982fbface82893e77d211fbabfbd229da6bdde6 (diff)
parent63cf13b77ab785e87c867defa8545e6d4a989774 (diff)
Merge branch 'linus' into cpus4096
Conflicts: arch/x86/xen/smp.c kernel/sched_rt.c net/iucv/iucv.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/arch-omap')
-rw-r--r--include/asm-arm/arch-omap/board-2430sdp.h5
-rw-r--r--include/asm-arm/arch-omap/board-h3.h6
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h3
-rw-r--r--include/asm-arm/arch-omap/board-perseus2.h6
-rw-r--r--include/asm-arm/arch-omap/clock.h17
-rw-r--r--include/asm-arm/arch-omap/common.h15
-rw-r--r--include/asm-arm/arch-omap/control.h4
-rw-r--r--include/asm-arm/arch-omap/cpu.h39
-rw-r--r--include/asm-arm/arch-omap/dma.h378
-rw-r--r--include/asm-arm/arch-omap/dmtimer.h1
-rw-r--r--include/asm-arm/arch-omap/fpga.h49
-rw-r--r--include/asm-arm/arch-omap/hardware.h1
-rw-r--r--include/asm-arm/arch-omap/io.h26
-rw-r--r--include/asm-arm/arch-omap/irqs.h44
-rw-r--r--include/asm-arm/arch-omap/mcbsp.h62
-rw-r--r--include/asm-arm/arch-omap/omap34xx.h72
-rw-r--r--include/asm-arm/arch-omap/sram.h37
-rw-r--r--include/asm-arm/arch-omap/tc.h10
-rw-r--r--include/asm-arm/arch-omap/usb.h23
19 files changed, 533 insertions, 265 deletions
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
38 38
39/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
40#define IH_TWL4030_BASE IH_BOARD_BASE
41#define IH_TWL4030_END (IH_TWL4030_BASE+8)
42#define NR_IRQS (IH_TWL4030_END)
43
44#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 39#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ 30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300 31#define OMAP1710_ETHR_START 0x04000300
32 32
33#define MAXIRQNUM (IH_BOARD_BASE)
34#define MAXFIQNUM MAXIRQNUM
35#define MAXSWINUM MAXIRQNUM
36
37#define NR_IRQS (MAXIRQNUM + 1)
38
39extern void h3_mmc_init(void); 33extern void h3_mmc_init(void);
40extern void h3_mmc_slot_cover_handler(void *arg, int state); 34extern void h3_mmc_slot_cover_handler(void *arg, int state);
41 35
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
38 38
39#define NR_FPGA_IRQS 24
40#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS)
41
42#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
43void fpga_write(unsigned char val, int reg); 40void fpga_write(unsigned char val, int reg);
44unsigned char fpga_read(int reg); 41unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
36#define OMAP_SDRAM_DEVICE D256M_1X16_4B 36#define OMAP_SDRAM_DEVICE D256M_1X16_4B
37#endif 37#endif
38 38
39#define MAXIRQNUM IH_BOARD_BASE
40#define MAXFIQNUM MAXIRQNUM
41#define MAXSWINUM MAXIRQNUM
42
43#define NR_IRQS (MAXIRQNUM + 1)
44
45#endif 39#endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
33 void __iomem *mult_div1_reg; 33 void __iomem *mult_div1_reg;
34 u32 mult_mask; 34 u32 mult_mask;
35 u32 div1_mask; 35 u32 div1_mask;
36 u16 last_rounded_m;
37 u8 last_rounded_n;
38 unsigned long last_rounded_rate;
39 unsigned int rate_tolerance;
40 u16 max_multiplier;
41 u8 max_divider;
42 u32 max_tolerance;
36# if defined(CONFIG_ARCH_OMAP3) 43# if defined(CONFIG_ARCH_OMAP3)
44 u8 modes;
37 void __iomem *control_reg; 45 void __iomem *control_reg;
38 u32 enable_mask; 46 u32 enable_mask;
39 u8 auto_recal_bit; 47 u8 auto_recal_bit;
40 u8 recal_en_bit; 48 u8 recal_en_bit;
41 u8 recal_st_bit; 49 u8 recal_st_bit;
50 void __iomem *autoidle_reg;
51 u32 autoidle_mask;
52 void __iomem *idlest_reg;
53 u8 idlest_bit;
42# endif 54# endif
43}; 55};
44 56
@@ -66,11 +78,14 @@ struct clk {
66 void __iomem *clksel_reg; 78 void __iomem *clksel_reg;
67 u32 clksel_mask; 79 u32 clksel_mask;
68 const struct clksel *clksel; 80 const struct clksel *clksel;
69 const struct dpll_data *dpll_data; 81 struct dpll_data *dpll_data;
70#else 82#else
71 __u8 rate_offset; 83 __u8 rate_offset;
72 __u8 src_offset; 84 __u8 src_offset;
73#endif 85#endif
86#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
87 struct dentry *dent; /* For visible tree hierarchy */
88#endif
74}; 89};
75 90
76struct cpufreq_frequency_table; 91struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
47} 47}
48#endif 48#endif
49 49
50/* IO bases for various OMAP processors */
51struct omap_globals {
52 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */
55 void __iomem *ctrl; /* System Control Module */
56 void __iomem *prm; /* Power and Reset Management */
57 void __iomem *cm; /* Clock Management */
58};
59
50void omap2_set_globals_242x(void); 60void omap2_set_globals_242x(void);
51void omap2_set_globals_243x(void); 61void omap2_set_globals_243x(void);
52void omap2_set_globals_343x(void); 62void omap2_set_globals_343x(void);
53 63
64/* These get called from omap2_set_globals_xxxx(), do not call these */
65void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *);
68
54#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 69#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
167 167
168#ifndef __ASSEMBLY__ 168#ifndef __ASSEMBLY__
169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
170extern void omap_ctrl_base_set(u32 base); 170extern void __iomem *omap_ctrl_base_get(void);
171extern u32 omap_ctrl_base_get(void);
172extern u8 omap_ctrl_readb(u16 offset); 171extern u8 omap_ctrl_readb(u16 offset);
173extern u16 omap_ctrl_readw(u16 offset); 172extern u16 omap_ctrl_readw(u16 offset);
174extern u32 omap_ctrl_readl(u16 offset); 173extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
176extern void omap_ctrl_writew(u16 val, u16 offset); 175extern void omap_ctrl_writew(u16 val, u16 offset);
177extern void omap_ctrl_writel(u32 val, u16 offset); 176extern void omap_ctrl_writel(u32 val, u16 offset);
178#else 177#else
179#define omap_ctrl_base_set(x) WARN_ON(1)
180#define omap_ctrl_base_get() 0 178#define omap_ctrl_base_get() 0
181#define omap_ctrl_readb(x) 0 179#define omap_ctrl_readb(x) 0
182#define omap_ctrl_readw(x) 0 180#define omap_ctrl_readw(x) 0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP cpu type detection 4 * OMAP cpu type detection
5 * 5 *
6 * Copyright (C) 2004 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
@@ -26,6 +26,12 @@
26#ifndef __ASM_ARCH_OMAP_CPU_H 26#ifndef __ASM_ARCH_OMAP_CPU_H
27#define __ASM_ARCH_OMAP_CPU_H 27#define __ASM_ARCH_OMAP_CPU_H
28 28
29struct omap_chip_id {
30 u8 oc;
31};
32
33#define OMAP_CHIP_INIT(x) { .oc = x }
34
29extern unsigned int system_rev; 35extern unsigned int system_rev;
30 36
31#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) 37#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
345#define OMAP2430_REV_ES1_0 0x24300000 351#define OMAP2430_REV_ES1_0 0x24300000
346#define OMAP3430_REV_ES1_0 0x34300000 352#define OMAP3430_REV_ES1_0 0x34300000
347#define OMAP3430_REV_ES2_0 0x34301000 353#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000
355#define OMAP3430_REV_ES2_2 0x34303000
356
357/*
358 * omap_chip bits
359 *
360 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
361 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
362 * something that is only valid on that particular ES revision.
363 *
364 * These bits may be ORed together to indicate structures that are
365 * available on multiple chip types.
366 *
367 * To test whether a particular structure matches the current OMAP chip type,
368 * use omap_chip_is().
369 *
370 */
371#define CHIP_IS_OMAP2420 (1 << 0)
372#define CHIP_IS_OMAP2430 (1 << 1)
373#define CHIP_IS_OMAP3430 (1 << 2)
374#define CHIP_IS_OMAP3430ES1 (1 << 3)
375#define CHIP_IS_OMAP3430ES2 (1 << 4)
376
377#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
378
379int omap_chip_is(struct omap_chip_id oci);
380
348 381
349/* 382/*
350 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD 383 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
362#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) 395#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
363#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) 396#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
364 397
365#endif 398void omap2_check_revision(void);
399
400#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
366 401
367#endif 402#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
22#define __ASM_ARCH_DMA_H 22#define __ASM_ARCH_DMA_H
23 23
24/* Hardware registers for omap1 */ 24/* Hardware registers for omap1 */
25#define OMAP_DMA_BASE (0xfffed800) 25#define OMAP1_DMA_BASE (0xfffed800)
26#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) 26
27#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) 27#define OMAP1_DMA_GCR 0x400
28#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) 28#define OMAP1_DMA_GSCR 0x404
29#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) 29#define OMAP1_DMA_GRST 0x408
30#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) 30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) 31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) 32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) 33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) 34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) 35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) 36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) 37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) 38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) 39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) 40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) 41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) 42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) 43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) 44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP1_DMA_PCH1_SR 0x482
46 46#define OMAP1_DMA_PCHD_SR 0x4c0
47/* Hardware registers for omap2 */ 47
48#if defined(CONFIG_ARCH_OMAP3) 48/* Hardware registers for omap2 and omap3 */
49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) 49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#else /* CONFIG_ARCH_OMAP2 */ 50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) 51
52#endif 52#define OMAP_DMA4_REVISION 0x00
53 53#define OMAP_DMA4_GCR 0x78
54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) 54#define OMAP_DMA4_IRQSTATUS_L0 0x08
55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) 55#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) 56#define OMAP_DMA4_IRQSTATUS_L2 0x10
57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) 57#define OMAP_DMA4_IRQSTATUS_L3 0x14
58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) 58#define OMAP_DMA4_IRQENABLE_L0 0x18
59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) 59#define OMAP_DMA4_IRQENABLE_L1 0x1c
60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) 60#define OMAP_DMA4_IRQENABLE_L2 0x20
61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) 61#define OMAP_DMA4_IRQENABLE_L3 0x24
62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) 62#define OMAP_DMA4_SYSSTATUS 0x28
63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) 63#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) 64#define OMAP_DMA4_CAPS_0 0x64
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) 65#define OMAP_DMA4_CAPS_2 0x6c
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) 66#define OMAP_DMA4_CAPS_3 0x70
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) 67#define OMAP_DMA4_CAPS_4 0x74
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) 68
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) 69#define OMAP1_LOGICAL_DMA_CH_COUNT 17
70 70#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
71#ifdef CONFIG_ARCH_OMAP1
72
73#define OMAP_LOGICAL_DMA_CH_COUNT 17
74 71
75/* Common channel specific registers for omap1 */ 72/* Common channel specific registers for omap1 */
76#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) 73#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
77#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) 74#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
78#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) 75#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
79#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) 76#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
80#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) 77#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
81#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) 78#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
82#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) 79#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
83#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) 80#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
84#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) 81#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
85#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) 82#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
86#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) 83#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
87#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) 84#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
88#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) 85#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
89 86#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
90#else 87#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
91
92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
93 88
94/* Common channel specific registers for omap2 */ 89/* Common channel specific registers for omap2 */
95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) 90#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) 91#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) 92#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) 93#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) 94#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) 95#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) 96#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) 97#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) 98#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) 99#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) 100#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) 101#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) 102#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
108 103#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
109#endif
110 104
111/* Channel specific registers only on omap1 */ 105/* Channel specific registers only on omap1 */
112#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) 106#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
113#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) 107#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
114#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) 108#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
115#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) 109#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
116#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) 110#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
117#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) 111#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
118#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) 112#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 113#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
114#define OMAP1_DMA_CCEN(n) 0
115#define OMAP1_DMA_CCFN(n) 0
120 116
121/* Channel specific registers only on omap2 */ 117/* Channel specific registers only on omap2 */
122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) 118#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) 119#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) 120#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) 121#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) 122#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
123
124/* Dummy defines to keep multi-omap compiles happy */
125#define OMAP1_DMA_REVISION 0
126#define OMAP1_DMA_IRQSTATUS_L0 0
127#define OMAP1_DMA_IRQENABLE_L0 0
128#define OMAP1_DMA_OCP_SYSCONFIG 0
129#define OMAP_DMA4_HW_ID 0
130#define OMAP_DMA4_CAPS_0_L 0
131#define OMAP_DMA4_CAPS_0_U 0
132#define OMAP_DMA4_CAPS_1_L 0
133#define OMAP_DMA4_CAPS_1_U 0
134#define OMAP_DMA4_GSCR 0
135#define OMAP_DMA4_CPC(n) 0
136
137#define OMAP_DMA4_LCH_CTRL(n) 0
138#define OMAP_DMA4_COLOR_L(n) 0
139#define OMAP_DMA4_COLOR_U(n) 0
140#define OMAP_DMA4_CCR2(n) 0
141#define OMAP1_DMA_CSSA(n) 0
142#define OMAP1_DMA_CDSA(n) 0
143#define OMAP_DMA4_CSSA_L(n) 0
144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0
127 147
128/*----------------------------------------------------------------------------*/ 148/*----------------------------------------------------------------------------*/
129 149
@@ -196,63 +216,98 @@
196#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 216#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
197#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ 217#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
198#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ 218#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
199#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ 219#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
220#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
200#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ 221#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
201#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ 222#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
202#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ 223#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
203#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ 224#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
204#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ 225#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
205#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ 226#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
206#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ 227#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
207#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ 228#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
208#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ 229#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
209#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ 230#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
210#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ 231#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
211#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ 232#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
212#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ 233#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
213#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ 234#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
214#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ 235#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
215#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ 236#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
216#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ 237#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
217#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ 238#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
218#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ 239#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
240#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
241#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
242#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
243#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
244#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
245#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
246#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
247#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
248#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
249#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
250#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
251#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
252#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
253#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
254#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
255#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
219#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ 256#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
220#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ 257#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
221#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ 258#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
222#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ 259#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
223#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ 260#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
224#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ 261#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
225#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ 262#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
226#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ 263#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
227#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ 264#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
228#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ 265#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
229#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ 266#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
230#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ 267#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
231#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ 268#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
232#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ 269#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
233#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ 270#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
234#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ 271#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
235#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ 272#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
236#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ 273#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
237#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ 274#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
238#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ 275#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
239 276#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
240#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ 277#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
241#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ 278#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
242#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ 279#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
243#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ 280#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
244#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ 281#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
245#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ 282#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
246#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ 283#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
247#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ 284#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
248#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ 285#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
249#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ 286#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
250#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ 287#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
251#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ 288#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
252#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ 289#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
253#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ 290#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
254#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ 291#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
255#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ 292#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
293#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
294#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
295#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
296#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
297#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
298#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
299#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
300#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
301#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
302#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
303#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
304#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
305#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
306#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
307#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
308#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
309#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
310#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
256 311
257/*----------------------------------------------------------------------------*/ 312/*----------------------------------------------------------------------------*/
258 313
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
358 OMAP_DMA_DATA_BURST_16, 413 OMAP_DMA_DATA_BURST_16,
359}; 414};
360 415
416enum end_type {
417 OMAP_DMA_LITTLE_ENDIAN = 0,
418 OMAP_DMA_BIG_ENDIAN
419};
420
361enum omap_dma_color_mode { 421enum omap_dma_color_mode {
362 OMAP_DMA_COLOR_DIS = 0, 422 OMAP_DMA_COLOR_DIS = 0,
363 OMAP_DMA_CONSTANT_FILL, 423 OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
370 OMAP_DMA_WRITE_LAST_NON_POSTED 430 OMAP_DMA_WRITE_LAST_NON_POSTED
371}; 431};
372 432
433enum omap_dma_channel_mode {
434 OMAP_DMA_LCH_2D = 0,
435 OMAP_DMA_LCH_G,
436 OMAP_DMA_LCH_P,
437 OMAP_DMA_LCH_PD
438};
439
373struct omap_dma_channel_params { 440struct omap_dma_channel_params {
374 int data_type; /* data type 8,16,32 */ 441 int data_type; /* data type 8,16,32 */
375 int elem_count; /* number of elements in a frame */ 442 int elem_count; /* number of elements in a frame */
376 int frame_count; /* number of frames in a element */ 443 int frame_count; /* number of frames in a element */
377 444
378 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ 445 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
379 int src_amode; /* constant , post increment, indexed , double indexed */ 446 int src_amode; /* constant, post increment, indexed,
447 double indexed */
380 unsigned long src_start; /* source address : physical */ 448 unsigned long src_start; /* source address : physical */
381 int src_ei; /* source element index */ 449 int src_ei; /* source element index */
382 int src_fi; /* source frame index */ 450 int src_fi; /* source frame index */
383 451
384 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ 452 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
385 int dst_amode; /* constant , post increment, indexed , double indexed */ 453 int dst_amode; /* constant, post increment, indexed,
454 double indexed */
386 unsigned long dst_start; /* source address : physical */ 455 unsigned long dst_start; /* source address : physical */
387 int dst_ei; /* source element index */ 456 int dst_ei; /* source element index */
388 int dst_fi; /* source frame index */ 457 int dst_fi; /* source frame index */
389 458
390 int trigger; /* trigger attached if the channel is synchronized */ 459 int trigger; /* trigger attached if the channel is
460 synchronized */
391 int sync_mode; /* sycn on element, frame , block or packet */ 461 int sync_mode; /* sycn on element, frame , block or packet */
392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 462 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
393 463
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
404 474
405extern void omap_set_dma_priority(int lch, int dst_port, int priority); 475extern void omap_set_dma_priority(int lch, int dst_port, int priority);
406extern int omap_request_dma(int dev_id, const char *dev_name, 476extern int omap_request_dma(int dev_id, const char *dev_name,
407 void (* callback)(int lch, u16 ch_status, void *data), 477 void (*callback)(int lch, u16 ch_status, void *data),
408 void *data, int *dma_ch); 478 void *data, int *dma_ch);
409extern void omap_enable_dma_irq(int ch, u16 irq_bits); 479extern void omap_enable_dma_irq(int ch, u16 irq_bits);
410extern void omap_disable_dma_irq(int ch, u16 irq_bits); 480extern void omap_disable_dma_irq(int ch, u16 irq_bits);
411extern void omap_free_dma(int ch); 481extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
418extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, 488extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
419 u32 color); 489 u32 color);
420extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 490extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
491extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
421 492
422extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 493extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
423 unsigned long src_start, 494 unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
436 enum omap_dma_burst_mode burst_mode); 507 enum omap_dma_burst_mode burst_mode);
437 508
438extern void omap_set_dma_params(int lch, 509extern void omap_set_dma_params(int lch,
439 struct omap_dma_channel_params * params); 510 struct omap_dma_channel_params *params);
440 511
441extern void omap_dma_link_lch (int lch_head, int lch_queue); 512extern void omap_dma_link_lch(int lch_head, int lch_queue);
442extern void omap_dma_unlink_lch (int lch_head, int lch_queue); 513extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
443 514
444extern int omap_set_dma_callback(int lch, 515extern int omap_set_dma_callback(int lch,
445 void (* callback)(int lch, u16 ch_status, void *data), 516 void (*callback)(int lch, u16 ch_status, void *data),
446 void *data); 517 void *data);
447extern dma_addr_t omap_get_dma_src_pos(int lch); 518extern dma_addr_t omap_get_dma_src_pos(int lch);
448extern dma_addr_t omap_get_dma_dst_pos(int lch); 519extern dma_addr_t omap_get_dma_dst_pos(int lch);
449extern int omap_get_dma_src_addr_counter(int lch);
450extern void omap_clear_dma(int lch); 520extern void omap_clear_dma(int lch);
521extern int omap_get_dma_active_status(int lch);
451extern int omap_dma_running(void); 522extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 523extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams); 524 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, 525extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio); 526 unsigned char write_prio);
527extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
528extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
529extern int omap_get_dma_index(int lch, int *ei, int *fi);
456 530
457/* Chaining APIs */ 531/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1 532#ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
478#endif 552#endif
479 553
480/* LCD DMA functions */ 554/* LCD DMA functions */
481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 555extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
482 void *data); 556 void *data);
483extern void omap_free_lcd_dma(void); 557extern void omap_free_lcd_dma(void);
484extern void omap_setup_lcd_dma(void); 558extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
66 66
67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
70void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); 71void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
71void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 72void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
170 170
171/* IRQ Numbers for interrupts muxed through the FPGA */ 171/* IRQ Numbers for interrupts muxed through the FPGA */
172#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE 172#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
173#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) 173#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
174#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) 174#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
175#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) 175#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
176#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) 176#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
177#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) 177#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
178#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) 178#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
179#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) 179#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
180#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) 180#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
181#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) 181#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
182#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) 182#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
183#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) 183#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
184#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) 184#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
185#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) 185#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
186#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) 186#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
187#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) 187#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
188#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) 188#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
189#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) 189#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
190#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) 190#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
191#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) 191#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
192#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) 192#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
193#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) 193#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
194#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) 194#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
195#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) 195#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
196#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
197 196
198#endif 197#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h" 285#include "omap24xx.h"
286#include "omap16xx.h" 286#include "omap16xx.h"
287#include "omap34xx.h"
287 288
288#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
289 290
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_p2v(pa) ((pa) - IO_OFFSET)
64#define io_v2p(va) ((va) + IO_OFFSET) 65#define io_v2p(va) ((va) + IO_OFFSET)
65 66
@@ -91,6 +92,7 @@
91 92
92#define IO_OFFSET 0x90000000 93#define IO_OFFSET 0x90000000
93#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
96 98
@@ -148,6 +150,7 @@
148 150
149#define IO_OFFSET 0x90000000 151#define IO_OFFSET 0x90000000
150#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
151#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
153 156
@@ -183,35 +186,12 @@
183#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
184#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
185 188
186/* 16 bit uses LDRH/STRH, base +/- offset_8 */
187typedef struct { volatile u16 offset[256]; } __regbase16;
188#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
189 ->offset[((vaddr)&0xff)>>1]
190#define __REG16(paddr) __REGV16(io_p2v(paddr))
191
192/* 8/32 bit uses LDR/STR, base +/- offset_12 */
193typedef struct { volatile u8 offset[4096]; } __regbase8;
194#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
195 ->offset[((vaddr)&4095)>>0]
196#define __REG8(paddr) __REGV8(io_p2v(paddr))
197
198typedef struct { volatile u32 offset[4096]; } __regbase32;
199#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
200 ->offset[((vaddr)&4095)>>2]
201#define __REG32(paddr) __REGV32(io_p2v(paddr))
202
203extern void omap1_map_common_io(void); 189extern void omap1_map_common_io(void);
204extern void omap1_init_common_hw(void); 190extern void omap1_init_common_hw(void);
205 191
206extern void omap2_map_common_io(void); 192extern void omap2_map_common_io(void);
207extern void omap2_init_common_hw(void); 193extern void omap2_init_common_hw(void);
208 194
209#else
210
211#define __REG8(paddr) io_p2v(paddr)
212#define __REG16(paddr) io_p2v(paddr)
213#define __REG32(paddr) io_p2v(paddr)
214
215#endif 195#endif
216 196
217#endif 197#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
285#define OMAP_MAX_GPIO_LINES 192 285#define OMAP_MAX_GPIO_LINES 192
286#define IH_GPIO_BASE (128 + IH2_BASE) 286#define IH_GPIO_BASE (128 + IH2_BASE)
287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
288#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) 288#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
289
290/* External FPGA handles interrupts on Innovator boards */
291#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
292#ifdef CONFIG_MACH_OMAP_INNOVATOR
293#define OMAP_FPGA_NR_IRQS 24
294#else
295#define OMAP_FPGA_NR_IRQS 0
296#endif
297#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
298
299/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
300#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
301#ifdef CONFIG_TWL4030_CORE
302#define TWL4030_BASE_NR_IRQS 8
303#define TWL4030_PWR_NR_IRQS 8
304#else
305#define TWL4030_BASE_NR_IRQS 0
306#define TWL4030_PWR_NR_IRQS 0
307#endif
308#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
309#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
310#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
311
312/* External TWL4030 gpio interrupts are optional */
313#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
314#ifdef CONFIG_TWL4030_GPIO
315#define TWL4030_GPIO_NR_IRQS 18
316#else
317#define TWL4030_GPIO_NR_IRQS 0
318#endif
319#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
320
321/* Total number of interrupts depends on the enabled blocks above */
322#define NR_IRQS TWL4030_GPIO_IRQ_END
289 323
290#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 324#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
291 325
@@ -293,14 +327,6 @@
293extern void omap_init_irq(void); 327extern void omap_init_irq(void);
294#endif 328#endif
295 329
296/*
297 * The definition of NR_IRQS is in board-specific header file, which is
298 * included via hardware.h
299 */
300#include <asm/hardware.h> 330#include <asm/hardware.h>
301 331
302#ifndef NR_IRQS
303#define NR_IRQS IH_BOARD_BASE
304#endif
305
306#endif 332#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
24#ifndef __ASM_ARCH_OMAP_MCBSP_H 24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
27#include <asm/hardware.h> 30#include <asm/hardware.h>
31#include <asm/arch/clock.h>
28 32
29#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP730_MCBSP1_BASE 0xfffb1000
30#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP730_MCBSP2_BASE 0xfffb1800
@@ -40,6 +44,9 @@
40#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
41#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
42 46
47#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000
49
43#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
44 51
45#define OMAP_MCBSP_REG_DRR2 0x00 52#define OMAP_MCBSP_REG_DRR2 0x00
@@ -74,7 +81,8 @@
74#define OMAP_MCBSP_REG_XCERG 0x3A 81#define OMAP_MCBSP_REG_XCERG 0x3A
75#define OMAP_MCBSP_REG_XCERH 0x3C 82#define OMAP_MCBSP_REG_XCERH 0x3C
76 83
77#define OMAP_MAX_MCBSP_COUNT 3 84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
78 86
79#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
80#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
117#define OMAP_MCBSP_REG_XCERG 0x74 125#define OMAP_MCBSP_REG_XCERG 0x74
118#define OMAP_MCBSP_REG_XCERH 0x78 126#define OMAP_MCBSP_REG_XCERH 0x78
119 127
120#define OMAP_MAX_MCBSP_COUNT 2 128#define OMAP_MAX_MCBSP_COUNT 2
129#define MAX_MCBSP_CLOCKS 2
121 130
122#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
123#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
298 omap_mcbsp_word_length word_length; 307 omap_mcbsp_word_length word_length;
299}; 308};
300 309
310/* Platform specific configuration */
311struct omap_mcbsp_ops {
312 void (*request)(unsigned int);
313 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315};
316
317struct omap_mcbsp_platform_data {
318 u32 virt_base;
319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops;
322 char const *clk_name;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 u32 io_base;
328 u8 id;
329 u8 free;
330 omap_mcbsp_word_length rx_word_length;
331 omap_mcbsp_word_length tx_word_length;
332
333 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
334 /* IRQ based TX/RX */
335 int rx_irq;
336 int tx_irq;
337
338 /* DMA stuff */
339 u8 dma_rx_sync;
340 short dma_rx_lch;
341 u8 dma_tx_sync;
342 short dma_tx_lch;
343
344 /* Completion queues */
345 struct completion tx_irq_completion;
346 struct completion rx_irq_completion;
347 struct completion tx_dma_completion;
348 struct completion rx_dma_completion;
349
350 /* Protect the field .free, while checking if the mcbsp is in use */
351 spinlock_t lock;
352 struct omap_mcbsp_platform_data *pdata;
353 struct clk *clk;
354};
355
356int omap_mcbsp_init(void);
357void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
358 int size);
301void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 359void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
302int omap_mcbsp_request(unsigned int id); 360int omap_mcbsp_request(unsigned int id);
303void omap_mcbsp_free(unsigned int id); 361void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
1/*
2 * include/asm-arm/arch-omap/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP34XX_H
25#define __ASM_ARCH_OMAP34XX_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_WK_OMAP_BASE L4_WK_34XX_BASE
35#define L4_PER_34XX_BASE 0x49000000
36#define L4_PER_OMAP_BASE L4_PER_34XX_BASE
37#define L4_EMU_34XX_BASE 0x54000000
38#define L4_EMU_BASE L4_EMU_34XX_BASE
39#define L3_34XX_BASE 0x68000000
40#define L3_OMAP_BASE L3_34XX_BASE
41
42#define OMAP3430_32KSYNCT_BASE 0x48320000
43#define OMAP3430_CM_BASE 0x48004800
44#define OMAP3430_PRM_BASE 0x48306800
45#define OMAP343X_SMS_BASE 0x6C000000
46#define OMAP343X_SDRC_BASE 0x6D000000
47#define OMAP34XX_GPMC_BASE 0x6E000000
48#define OMAP343X_SCM_BASE 0x48002000
49#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
50
51#define OMAP34XX_IC_BASE 0x48200000
52#define OMAP34XX_IVA_INTC_BASE 0x40000000
53#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
54#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
55#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
56
57
58#if defined(CONFIG_ARCH_OMAP3430)
59
60#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
61#define OMAP2_CM_BASE OMAP3430_CM_BASE
62#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
63#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
64
65#endif
66
67#define OMAP34XX_DSP_BASE 0x58000000
68#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
69#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
70#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
71#endif /* __ASM_ARCH_OMAP34XX_H */
72
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
22 23
23/* Do not use these */ 24/* Do not use these */
24extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); 25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
25extern unsigned long sram_reprogram_clock_sz; 26extern unsigned long omap1_sram_reprogram_clock_sz;
26 27
27extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 28extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
28 u32 base_cs, u32 force_unlock); 29extern unsigned long omap24xx_sram_reprogram_clock_sz;
29extern unsigned long sram_ddr_init_sz;
30 30
31extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 31extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
32extern unsigned long sram_set_prcm_sz; 32 u32 base_cs, u32 force_unlock);
33extern unsigned long omap242x_sram_ddr_init_sz;
33 34
34extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); 35extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
35extern unsigned long sram_reprogram_sdrc_sz; 36 int bypass);
37extern unsigned long omap242x_sram_set_prcm_sz;
38
39extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40 u32 mem_type);
41extern unsigned long omap242x_sram_reprogram_sdrc_sz;
42
43
44extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
45 u32 base_cs, u32 force_unlock);
46extern unsigned long omap243x_sram_ddr_init_sz;
47
48extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
49 int bypass);
50extern unsigned long omap243x_sram_set_prcm_sz;
51
52extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz;
36 55
37#endif 56#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
75#ifndef __ASSEMBLER__ 75#ifndef __ASSEMBLER__
76 76
77/* EMIF Slow Interface Configuration Register */ 77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG)
79
80#define OMAP_EMIFS_CONFIG_FR (1 << 4) 78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
81#define OMAP_EMIFS_CONFIG_PDE (1 << 3) 79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
82#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) 80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
83#define OMAP_EMIFS_CONFIG_BM (1 << 1) 81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
84#define OMAP_EMIFS_CONFIG_WP (1 << 0) 82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
85 83
86#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n))) 84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
87#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n))) 85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
88 86
89/* Almost all documentation for chip and board memory maps assumes 87/* Almost all documentation for chip and board memory maps assumes
90 * BM is clear. Most devel boards have a switch to control booting 88 * BM is clear. Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
93 */ 91 */
94static inline u32 omap_cs0_phys(void) 92static inline u32 omap_cs0_phys(void)
95{ 93{
96 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
97 ? OMAP_CS3_PHYS : 0; 95 ? OMAP_CS3_PHYS : 0;
98} 96}
99 97
100static inline u32 omap_cs3_phys(void) 98static inline u32 omap_cs3_phys(void)
101{ 99{
102 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
103 ? 0 : OMAP_CS3_PHYS; 101 ? 0 : OMAP_CS3_PHYS;
104} 102}
105 103
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
34/* 34/*
35 * OTG and transceiver registers, for OMAPs starting with ARM926 35 * OTG and transceiver registers, for OMAPs starting with ARM926
36 */ 36 */
37#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) 37#define OTG_REV (OTG_BASE + 0x00)
38#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) 38#define OTG_SYSCON_1 (OTG_BASE + 0x04)
39
40#define OTG_REV_REG OTG_REG32(0x00)
41#define OTG_SYSCON_1_REG OTG_REG32(0x04)
42# define USB2_TRX_MODE(w) (((w)>>24)&0x07) 39# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
43# define USB1_TRX_MODE(w) (((w)>>20)&0x07) 40# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
44# define USB0_TRX_MODE(w) (((w)>>16)&0x07) 41# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
47# define DEV_IDLE_EN (1 << 13) 44# define DEV_IDLE_EN (1 << 13)
48# define OTG_RESET_DONE (1 << 2) 45# define OTG_RESET_DONE (1 << 2)
49# define OTG_SOFT_RESET (1 << 1) 46# define OTG_SOFT_RESET (1 << 1)
50#define OTG_SYSCON_2_REG OTG_REG32(0x08) 47#define OTG_SYSCON_2 (OTG_BASE + 0x08)
51# define OTG_EN (1 << 31) 48# define OTG_EN (1 << 31)
52# define USBX_SYNCHRO (1 << 30) 49# define USBX_SYNCHRO (1 << 30)
53# define OTG_MST16 (1 << 29) 50# define OTG_MST16 (1 << 29)
@@ -65,7 +62,7 @@
65# define HMC_TLLSPEED (1 << 7) 62# define HMC_TLLSPEED (1 << 7)
66# define HMC_TLLATTACH (1 << 6) 63# define HMC_TLLATTACH (1 << 6)
67# define OTG_HMC(w) (((w)>>0)&0x3f) 64# define OTG_HMC(w) (((w)>>0)&0x3f)
68#define OTG_CTRL_REG OTG_REG32(0x0c) 65#define OTG_CTRL (OTG_BASE + 0x0c)
69# define OTG_USB2_EN (1 << 29) 66# define OTG_USB2_EN (1 << 29)
70# define OTG_USB2_DP (1 << 28) 67# define OTG_USB2_DP (1 << 28)
71# define OTG_USB2_DM (1 << 27) 68# define OTG_USB2_DM (1 << 27)
@@ -92,7 +89,7 @@
92# define OTG_PD_VBUS (1 << 2) 89# define OTG_PD_VBUS (1 << 2)
93# define OTG_PU_VBUS (1 << 1) 90# define OTG_PU_VBUS (1 << 1)
94# define OTG_PU_ID (1 << 0) 91# define OTG_PU_ID (1 << 0)
95#define OTG_IRQ_EN_REG OTG_REG16(0x10) 92#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
96# define DRIVER_SWITCH (1 << 15) 93# define DRIVER_SWITCH (1 << 15)
97# define A_VBUS_ERR (1 << 13) 94# define A_VBUS_ERR (1 << 13)
98# define A_REQ_TMROUT (1 << 12) 95# define A_REQ_TMROUT (1 << 12)
@@ -102,9 +99,9 @@
102# define B_SRP_DONE (1 << 8) 99# define B_SRP_DONE (1 << 8)
103# define B_SRP_STARTED (1 << 7) 100# define B_SRP_STARTED (1 << 7)
104# define OPRT_CHG (1 << 0) 101# define OPRT_CHG (1 << 0)
105#define OTG_IRQ_SRC_REG OTG_REG16(0x14) 102#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
106 // same bits as in IRQ_EN 103 // same bits as in IRQ_EN
107#define OTG_OUTCTRL_REG OTG_REG16(0x18) 104#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
108# define OTGVPD (1 << 14) 105# define OTGVPD (1 << 14)
109# define OTGVPU (1 << 13) 106# define OTGVPU (1 << 13)
110# define OTGPUID (1 << 12) 107# define OTGPUID (1 << 12)
@@ -117,13 +114,13 @@
117# define USB0VDR (1 << 2) 114# define USB0VDR (1 << 2)
118# define USB0PDEN (1 << 1) 115# define USB0PDEN (1 << 1)
119# define USB0PUEN (1 << 0) 116# define USB0PUEN (1 << 0)
120#define OTG_TEST_REG OTG_REG16(0x20) 117#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
121#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) 118#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
122 119
123/*-------------------------------------------------------------------------*/ 120/*-------------------------------------------------------------------------*/
124 121
125/* OMAP1 */ 122/* OMAP1 */
126#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) 123#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
127# define CONF_USB2_UNI_R (1 << 8) 124# define CONF_USB2_UNI_R (1 << 8)
128# define CONF_USB1_UNI_R (1 << 7) 125# define CONF_USB1_UNI_R (1 << 7)
129# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) 126# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 20:57:28 -0500