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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-omap
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-omap')
-rw-r--r--include/asm-arm/arch-omap/aic23.h112
-rw-r--r--include/asm-arm/arch-omap/board-h2.h47
-rw-r--r--include/asm-arm/arch-omap/board-h3.h49
-rw-r--r--include/asm-arm/arch-omap/board-h4.h35
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h80
-rw-r--r--include/asm-arm/arch-omap/board-netstar.h19
-rw-r--r--include/asm-arm/arch-omap/board-osk.h41
-rw-r--r--include/asm-arm/arch-omap/board-perseus2.h58
-rw-r--r--include/asm-arm/arch-omap/board-voiceblue.h25
-rw-r--r--include/asm-arm/arch-omap/board.h126
-rw-r--r--include/asm-arm/arch-omap/cpu.h183
-rw-r--r--include/asm-arm/arch-omap/debug-macro.S45
-rw-r--r--include/asm-arm/arch-omap/dma.h264
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S32
-rw-r--r--include/asm-arm/arch-omap/fpga.h196
-rw-r--r--include/asm-arm/arch-omap/gpio.h69
-rw-r--r--include/asm-arm/arch-omap/hardware.h324
-rw-r--r--include/asm-arm/arch-omap/io.h107
-rw-r--r--include/asm-arm/arch-omap/irqs.h255
-rw-r--r--include/asm-arm/arch-omap/mcbsp.h257
-rw-r--r--include/asm-arm/arch-omap/memory.h87
-rw-r--r--include/asm-arm/arch-omap/mux.h561
-rw-r--r--include/asm-arm/arch-omap/omap1510.h61
-rw-r--r--include/asm-arm/arch-omap/omap16xx.h187
-rw-r--r--include/asm-arm/arch-omap/omap730.h106
-rw-r--r--include/asm-arm/arch-omap/param.h8
-rw-r--r--include/asm-arm/arch-omap/pm.h229
-rw-r--r--include/asm-arm/arch-omap/system.h20
-rw-r--r--include/asm-arm/arch-omap/tc.h108
-rw-r--r--include/asm-arm/arch-omap/timex.h33
-rw-r--r--include/asm-arm/arch-omap/tps65010.h80
-rw-r--r--include/asm-arm/arch-omap/uncompress.h82
-rw-r--r--include/asm-arm/arch-omap/usb.h108
-rw-r--r--include/asm-arm/arch-omap/vmalloc.h33
34 files changed, 4027 insertions, 0 deletions
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
new file mode 100644
index 000000000000..590bac25b7c4
--- /dev/null
+++ b/include/asm-arm/arch-omap/aic23.h
@@ -0,0 +1,112 @@
1/*
2 * linux/include/asm-arm/arch-omap/aic23.h
3 *
4 * Hardware definitions for TI TLV320AIC23 audio codec
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_AIC23_H
31#define __ASM_ARCH_AIC23_H
32
33// Codec TLV320AIC23
34#define LEFT_LINE_VOLUME_ADDR 0x00
35#define RIGHT_LINE_VOLUME_ADDR 0x01
36#define LEFT_CHANNEL_VOLUME_ADDR 0x02
37#define RIGHT_CHANNEL_VOLUME_ADDR 0x03
38#define ANALOG_AUDIO_CONTROL_ADDR 0x04
39#define DIGITAL_AUDIO_CONTROL_ADDR 0x05
40#define POWER_DOWN_CONTROL_ADDR 0x06
41#define DIGITAL_AUDIO_FORMAT_ADDR 0x07
42#define SAMPLE_RATE_CONTROL_ADDR 0x08
43#define DIGITAL_INTERFACE_ACT_ADDR 0x09
44#define RESET_CONTROL_ADDR 0x0F
45
46// Left (right) line input volume control register
47#define LRS_ENABLED 0x0100
48#define LIM_MUTED 0x0080
49#define LIV_DEFAULT 0x0017
50#define LIV_MAX 0x001f
51#define LIV_MIN 0x0000
52
53// Left (right) channel headphone volume control register
54#define LZC_ON 0x0080
55#define LHV_DEFAULT 0x0079
56#define LHV_MAX 0x007f
57#define LHV_MIN 0x0000
58
59// Analog audio path control register
60#define STE_ENABLED 0x0020
61#define DAC_SELECTED 0x0010
62#define BYPASS_ON 0x0008
63#define INSEL_MIC 0x0004
64#define MICM_MUTED 0x0002
65#define MICB_20DB 0x0001
66
67// Digital audio path control register
68#define DACM_MUTE 0x0008
69#define DEEMP_32K 0x0002
70#define DEEMP_44K 0x0004
71#define DEEMP_48K 0x0006
72#define ADCHP_ON 0x0001
73
74// Power control down register
75#define DEVICE_POWER_OFF 0x0080
76#define CLK_OFF 0x0040
77#define OSC_OFF 0x0020
78#define OUT_OFF 0x0010
79#define DAC_OFF 0x0008
80#define ADC_OFF 0x0004
81#define MIC_OFF 0x0002
82#define LINE_OFF 0x0001
83
84// Digital audio interface register
85#define MS_MASTER 0x0040
86#define LRSWAP_ON 0x0020
87#define LRP_ON 0x0010
88#define IWL_16 0x0000
89#define IWL_20 0x0004
90#define IWL_24 0x0008
91#define IWL_32 0x000C
92#define FOR_I2S 0x0002
93#define FOR_DSP 0x0003
94
95// Sample rate control register
96#define CLKOUT_HALF 0x0080
97#define CLKIN_HALF 0x0040
98#define BOSR_384fs 0x0002 // BOSR_272fs when in USB mode
99#define USB_CLK_ON 0x0001
100#define SR_MASK 0xf
101#define CLKOUT_SHIFT 7
102#define CLKIN_SHIFT 6
103#define SR_SHIFT 2
104#define BOSR_SHIFT 1
105
106// Digital interface register
107#define ACT_ON 0x0001
108
109#define TLV320AIC23ID1 (0x1a) // cs low
110#define TLV320AIC23ID2 (0x1b) // cs high
111
112#endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
new file mode 100644
index 000000000000..60f002b72983
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -0,0 +1,47 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h2.h
3 *
4 * Hardware definitions for TI OMAP1610 H2 board.
5 *
6 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_H2_H
30#define __ASM_ARCH_OMAP_H2_H
31
32/* Placeholder for H2 specific defines */
33
34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
35#define OMAP1610_ETHR_START 0x04000300
36
37/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
38#define OMAP_NOR_FLASH_SIZE SZ_32M
39#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
40#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
41
42/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
43#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
44#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
45
46#endif /* __ASM_ARCH_OMAP_H2_H */
47
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
new file mode 100644
index 000000000000..e4d1cd231731
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -0,0 +1,49 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h3.h
3 *
4 * Copyright (C) 2001 RidgeRun, Inc.
5 * Copyright (C) 2004 Texas Instruments, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_ARCH_OMAP_H3_H
28#define __ASM_ARCH_OMAP_H3_H
29
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300
32
33/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
34#define OMAP_NOR_FLASH_SIZE SZ_32M
35#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
36#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
37
38/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
39#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
40#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
41
42#define MAXIRQNUM (IH_BOARD_BASE)
43#define MAXFIQNUM MAXIRQNUM
44#define MAXSWINUM MAXIRQNUM
45
46#define NR_IRQS (MAXIRQNUM + 1)
47
48
49#endif /* __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
new file mode 100644
index 000000000000..79138dcfb4ac
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -0,0 +1,35 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-h4.h
3 *
4 * Hardware definitions for TI OMAP1610 H4 board.
5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H
31
32/* Placeholder for H4 specific defines */
33
34#endif /* __ASM_ARCH_OMAP_H4_H */
35
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
new file mode 100644
index 000000000000..0f1abaefe4de
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -0,0 +1,80 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-innovator.h
3 *
4 * Copyright (C) 2001 RidgeRun, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
27#define __ASM_ARCH_OMAP_INNOVATOR_H
28
29#if defined (CONFIG_ARCH_OMAP1510)
30
31#ifndef OMAP_SDRAM_DEVICE
32#define OMAP_SDRAM_DEVICE D256M_1X16_4B
33#endif
34
35#define OMAP1510P1_IMIF_PRI_VALUE 0x00
36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
38
39/*
40 * These definitions define an area of FLASH set aside
41 * for the use of MTD/JFFS2. This is the area of flash
42 * that a JFFS2 filesystem will reside which is mounted
43 * at boot with the "root=/dev/mtdblock/0 rw"
44 * command line option. The flash address used here must
45 * fall within the legal range defined by rrload for storing
46 * the filesystem component. This address will be sufficiently
47 * deep into the overall flash range to avoid the other
48 * components also stored in flash such as the bootloader,
49 * the bootloader params, and the kernel.
50 * The SW2 settings for the map below are:
51 * 1 off, 2 off, 3 on, 4 off.
52 */
53
54/* Intel flash_0, partitioned as expected by rrload */
55#define OMAP_FLASH_0_BASE 0xD8000000
56#define OMAP_FLASH_0_START 0x00000000
57#define OMAP_FLASH_0_SIZE SZ_16M
58
59/* Intel flash_1, used for cramfs or other flash file systems */
60#define OMAP_FLASH_1_BASE 0xD9000000
61#define OMAP_FLASH_1_START 0x01000000
62#define OMAP_FLASH_1_SIZE SZ_16M
63
64#define NR_FPGA_IRQS 24
65#define NR_IRQS IH_BOARD_BASE + NR_FPGA_IRQS
66
67#ifndef __ASSEMBLY__
68void fpga_write(unsigned char val, int reg);
69unsigned char fpga_read(int reg);
70#endif
71
72#endif /* CONFIG_ARCH_OMAP1510 */
73
74#if defined (CONFIG_ARCH_OMAP16XX)
75
76/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
77#define INNOVATOR1610_ETHR_START 0x04000300
78
79#endif /* CONFIG_ARCH_OMAP1610 */
80#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/include/asm-arm/arch-omap/board-netstar.h b/include/asm-arm/arch-omap/board-netstar.h
new file mode 100644
index 000000000000..77cc0fb54d54
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-netstar.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
3 *
4 * Hardware definitions for OMAP5910 based NetStar board.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_NETSTAR_H
12#define __ASM_ARCH_NETSTAR_H
13
14#include <asm/arch/tc.h>
15
16#define OMAP_NAND_FLASH_START1 OMAP_CS1_PHYS + (1 << 23)
17#define OMAP_NAND_FLASH_START2 OMAP_CS1_PHYS + (2 << 23)
18
19#endif /* __ASM_ARCH_NETSTAR_H */
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
new file mode 100644
index 000000000000..aaa49a0fbd21
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -0,0 +1,41 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-osk.h
3 *
4 * Hardware definitions for TI OMAP5912 OSK board.
5 *
6 * Written by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_OSK_H
30#define __ASM_ARCH_OMAP_OSK_H
31
32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
33#define OMAP_OSK_ETHR_START 0x04800300
34
35/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
36#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000
37#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M
38#define OMAP_OSK_NOR_FLASH_START 0x00000000
39
40#endif /* __ASM_ARCH_OMAP_OSK_H */
41
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
new file mode 100644
index 000000000000..0c224cc74fe4
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -0,0 +1,58 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-perseus2.h
3 *
4 * Copyright 2003 by Texas Instruments Incorporated
5 * OMAP730 / Perseus2 support by Jean Pihet
6 *
7 * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
8 * Author: RidgeRun, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
31#define __ASM_ARCH_OMAP_PERSEUS2_H
32
33#include <asm/arch/fpga.h>
34
35#ifndef OMAP_SDRAM_DEVICE
36#define OMAP_SDRAM_DEVICE D256M_1X16_4B
37#endif
38
39/*
40 * These definitions define an area of FLASH set aside
41 * for the use of MTD/JFFS2. This is the area of flash
42 * that a JFFS2 filesystem will reside which is mounted
43 * at boot with the "root=/dev/mtdblock/0 rw"
44 * command line option.
45 */
46
47/* Intel flash_0, partitioned as expected by rrload */
48#define OMAP_FLASH_0_BASE 0xD8000000 /* VA */
49#define OMAP_FLASH_0_START 0x00000000 /* PA */
50#define OMAP_FLASH_0_SIZE SZ_32M
51
52#define MAXIRQNUM IH_BOARD_BASE
53#define MAXFIQNUM MAXIRQNUM
54#define MAXSWINUM MAXIRQNUM
55
56#define NR_IRQS (MAXIRQNUM + 1)
57
58#endif
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h
new file mode 100644
index 000000000000..33977b8956fb
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-voiceblue.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
3 *
4 * Hardware definitions for OMAP5910 based VoiceBlue board.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_VOICEBLUE_H
12#define __ASM_ARCH_VOICEBLUE_H
13
14#if (EXTERNAL_MAX_NR_PORTS < 4)
15#undef EXTERNAL_MAX_NR_PORTS
16#define EXTERNAL_MAX_NR_PORTS 4
17#endif
18
19extern void voiceblue_wdt_enable(void);
20extern void voiceblue_wdt_disable(void);
21extern void voiceblue_wdt_ping(void);
22extern void voiceblue_reset(void);
23
24#endif /* __ASM_ARCH_VOICEBLUE_H */
25
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
new file mode 100644
index 000000000000..1cefd60b6f2a
--- /dev/null
+++ b/include/asm-arm/arch-omap/board.h
@@ -0,0 +1,126 @@
1/*
2 * linux/include/asm-arm/arch-omap/board.h
3 *
4 * Information structures for board-specific data
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 */
9
10#ifndef _OMAP_BOARD_H
11#define _OMAP_BOARD_H
12
13#include <linux/config.h>
14#include <linux/types.h>
15
16/* Different peripheral ids */
17#define OMAP_TAG_CLOCK 0x4f01
18#define OMAP_TAG_MMC 0x4f02
19#define OMAP_TAG_UART 0x4f03
20#define OMAP_TAG_USB 0x4f04
21#define OMAP_TAG_LCD 0x4f05
22#define OMAP_TAG_GPIO_SWITCH 0x4f06
23
24#define OMAP_TAG_BOOT_REASON 0x4f80
25#define OMAP_TAG_FLASH_PART 0x4f81
26
27struct omap_clock_config {
28 /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
29 u8 system_clock_type;
30};
31
32struct omap_mmc_config {
33 u8 mmc_blocks;
34 s16 mmc1_power_pin, mmc2_power_pin;
35 s16 mmc1_switch_pin, mmc2_switch_pin;
36};
37
38struct omap_uart_config {
39 u8 console_uart;
40 u32 console_speed;
41};
42
43struct omap_usb_config {
44 /* Configure drivers according to the connectors on your board:
45 * - "A" connector (rectagular)
46 * ... for host/OHCI use, set "register_host".
47 * - "B" connector (squarish) or "Mini-B"
48 * ... for device/gadget use, set "register_dev".
49 * - "Mini-AB" connector (very similar to Mini-B)
50 * ... for OTG use as device OR host, initialize "otg"
51 */
52 unsigned register_host:1;
53 unsigned register_dev:1;
54 u8 otg; /* port number, 1-based: usb1 == 2 */
55
56 u8 hmc_mode;
57
58 /* implicitly true if otg: host supports remote wakeup? */
59 u8 rwc;
60
61 /* signaling pins used to talk to transceiver on usbN:
62 * 0 == usbN unused
63 * 2 == usb0-only, using internal transceiver
64 * 3 == 3 wire bidirectional
65 * 4 == 4 wire bidirectional
66 * 6 == 6 wire unidirectional (or TLL)
67 */
68 u8 pins[3];
69};
70
71struct omap_lcd_config {
72 char panel_name[16];
73 char ctrl_name[16];
74};
75
76/* Cover:
77 * high -> closed
78 * low -> open
79 * Connection:
80 * high -> connected
81 * low -> disconnected
82 */
83#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
84#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
85#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
86struct omap_gpio_switch_config {
87 char name[12];
88 u16 gpio;
89 int flags:4;
90 int type:4;
91 int key_code:24; /* Linux key code */
92};
93
94struct omap_flash_part_config {
95 char part_table[0];
96};
97
98struct omap_boot_reason_config {
99 char reason_str[12];
100};
101
102
103struct omap_board_config_entry {
104 u16 tag;
105 u16 len;
106 u8 data[0];
107};
108
109struct omap_board_config_kernel {
110 u16 tag;
111 const void *data;
112};
113
114extern const void *__omap_get_config(u16 tag, size_t len, int nr);
115
116#define omap_get_config(tag, type) \
117 ((const type *) __omap_get_config((tag), sizeof(type), 0))
118#define omap_get_nr_config(tag, type, nr) \
119 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
120
121extern const void *omap_get_var_config(u16 tag, size_t *len);
122
123extern struct omap_board_config_kernel *omap_board_config;
124extern int omap_board_config_size;
125
126#endif
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
new file mode 100644
index 000000000000..e8786713ee5c
--- /dev/null
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -0,0 +1,183 @@
1/*
2 * linux/include/asm-arm/arch-omap/cpu.h
3 *
4 * OMAP cpu type detection
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_CPU_H
27#define __ASM_ARCH_OMAP_CPU_H
28
29extern unsigned int system_rev;
30
31#define OMAP_DIE_ID_0 0xfffe1800
32#define OMAP_DIE_ID_1 0xfffe1804
33#define OMAP_PRODUCTION_ID_0 0xfffe2000
34#define OMAP_PRODUCTION_ID_1 0xfffe2004
35#define OMAP32_ID_0 0xfffed400
36#define OMAP32_ID_1 0xfffed404
37
38/*
39 * Test if multicore OMAP support is needed
40 */
41#undef MULTI_OMAP
42#undef OMAP_NAME
43
44#ifdef CONFIG_ARCH_OMAP730
45# ifdef OMAP_NAME
46# undef MULTI_OMAP
47# define MULTI_OMAP
48# else
49# define OMAP_NAME omap730
50# endif
51#endif
52#ifdef CONFIG_ARCH_OMAP1510
53# ifdef OMAP_NAME
54# undef MULTI_OMAP
55# define MULTI_OMAP
56# else
57# define OMAP_NAME omap1510
58# endif
59#endif
60#ifdef CONFIG_ARCH_OMAP16XX
61# ifdef OMAP_NAME
62# undef MULTI_OMAP
63# define MULTI_OMAP
64# else
65# define OMAP_NAME omap1610
66# endif
67#endif
68#ifdef CONFIG_ARCH_OMAP16XX
69# ifdef OMAP_NAME
70# undef MULTI_OMAP
71# define MULTI_OMAP
72# else
73# define OMAP_NAME omap1710
74# endif
75#endif
76
77/*
78 * Generate various OMAP cpu specific macros, and cpu class
79 * specific macros
80 */
81#define GET_OMAP_TYPE ((system_rev >> 24) & 0xff)
82#define GET_OMAP_CLASS (system_rev & 0xff)
83
84#define IS_OMAP_TYPE(type, id) \
85static inline int is_omap ##type (void) \
86{ \
87 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
88}
89
90#define IS_OMAP_CLASS(class, id) \
91static inline int is_omap ##class (void) \
92{ \
93 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
94}
95
96IS_OMAP_TYPE(730, 0x07)
97IS_OMAP_TYPE(1510, 0x15)
98IS_OMAP_TYPE(1610, 0x16)
99IS_OMAP_TYPE(5912, 0x16)
100IS_OMAP_TYPE(1710, 0x17)
101IS_OMAP_TYPE(2420, 0x24)
102
103IS_OMAP_CLASS(7xx, 0x07)
104IS_OMAP_CLASS(15xx, 0x15)
105IS_OMAP_CLASS(16xx, 0x16)
106IS_OMAP_CLASS(24xx, 0x24)
107
108/*
109 * Macros to group OMAP types into cpu classes.
110 * These can be used in most places.
111 * cpu_is_omap15xx(): True for 1510 and 5910
112 * cpu_is_omap16xx(): True for 1610, 5912 and 1710
113 */
114#if defined(MULTI_OMAP)
115# define cpu_is_omap7xx() is_omap7xx()
116# define cpu_is_omap15xx() is_omap15xx()
117# if !(defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP730))
118# define cpu_is_omap16xx() 1
119# else
120# define cpu_is_omap16xx() is_omap16xx()
121# endif
122#else
123# if defined(CONFIG_ARCH_OMAP730)
124# define cpu_is_omap7xx() 1
125# else
126# define cpu_is_omap7xx() 0
127# endif
128# if defined(CONFIG_ARCH_OMAP1510)
129# define cpu_is_omap15xx() 1
130# else
131# define cpu_is_omap15xx() 0
132# endif
133# if defined(CONFIG_ARCH_OMAP16XX)
134# define cpu_is_omap16xx() 1
135# else
136# define cpu_is_omap16xx() 0
137# endif
138#endif
139
140#if defined(MULTI_OMAP)
141# define cpu_is_omap730() is_omap730()
142# define cpu_is_omap1510() is_omap1510()
143# define cpu_is_omap1610() is_omap1610()
144# define cpu_is_omap5912() is_omap5912()
145# define cpu_is_omap1710() is_omap1710()
146#else
147# if defined(CONFIG_ARCH_OMAP730)
148# define cpu_is_omap730() 1
149# else
150# define cpu_is_omap730() 0
151# endif
152# if defined(CONFIG_ARCH_OMAP1510)
153# define cpu_is_omap1510() 1
154# else
155# define cpu_is_omap1510() 0
156# endif
157# if defined(CONFIG_ARCH_OMAP16XX)
158# define cpu_is_omap1610() 1
159# else
160# define cpu_is_omap1610() 0
161# endif
162# if defined(CONFIG_ARCH_OMAP16XX)
163# define cpu_is_omap5912() 1
164# else
165# define cpu_is_omap5912() 0
166# endif
167# if defined(CONFIG_ARCH_OMAP16XX)
168# define cpu_is_omap1610() is_omap1610()
169# define cpu_is_omap5912() is_omap5912()
170# define cpu_is_omap1710() is_omap1710()
171# else
172# define cpu_is_omap1610() 0
173# define cpu_is_omap5912() 0
174# define cpu_is_omap1710() 0
175# endif
176# if defined(CONFIG_ARCH_OMAP2420)
177# define cpu_is_omap2420() 1
178# else
179# define cpu_is_omap2420() 0
180# endif
181#endif
182
183#endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
new file mode 100644
index 000000000000..83bb458afd0b
--- /dev/null
+++ b/include/asm-arm/arch-omap/debug-macro.S
@@ -0,0 +1,45 @@
1/* linux/include/asm-arm/arch-omap/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0xff000000 @ physical base address
18 movne \rx, #0xfe000000 @ virtual base
19 orr \rx, \rx, #0x00fb0000
20#ifdef CONFIG_OMAP_LL_DEBUG_UART3
21 orr \rx, \rx, #0x00009000 @ UART 3
22#endif
23#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
24 orr \rx, \rx, #0x00000800 @ UART 2 & 3
25#endif
26 .endm
27
28 .macro senduart,rd,rx
29 strb \rd, [\rx]
30 .endm
31
32 .macro busyuart,rd,rx
331001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
34 and \rd, \rd, #0x60
35 teq \rd, #0x60
36 beq 1002f
37 ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
38 and \rd, \rd, #0x60
39 teq \rd, #0x60
40 bne 1001b
411002:
42 .endm
43
44 .macro waituart,rd,rx
45 .endm
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
new file mode 100644
index 000000000000..d785248377db
--- /dev/null
+++ b/include/asm-arm/arch-omap/dma.h
@@ -0,0 +1,264 @@
1/*
2 * linux/include/asm-arm/arch-omap/dma.h
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24#define MAX_DMA_ADDRESS 0xffffffff
25
26#define OMAP_LOGICAL_DMA_CH_COUNT 17
27
28#define OMAP_DMA_NO_DEVICE 0
29#define OMAP_DMA_MCSI1_TX 1
30#define OMAP_DMA_MCSI1_RX 2
31#define OMAP_DMA_I2C_RX 3
32#define OMAP_DMA_I2C_TX 4
33#define OMAP_DMA_EXT_NDMA_REQ 5
34#define OMAP_DMA_EXT_NDMA_REQ2 6
35#define OMAP_DMA_UWIRE_TX 7
36#define OMAP_DMA_MCBSP1_TX 8
37#define OMAP_DMA_MCBSP1_RX 9
38#define OMAP_DMA_MCBSP3_TX 10
39#define OMAP_DMA_MCBSP3_RX 11
40#define OMAP_DMA_UART1_TX 12
41#define OMAP_DMA_UART1_RX 13
42#define OMAP_DMA_UART2_TX 14
43#define OMAP_DMA_UART2_RX 15
44#define OMAP_DMA_MCBSP2_TX 16
45#define OMAP_DMA_MCBSP2_RX 17
46#define OMAP_DMA_UART3_TX 18
47#define OMAP_DMA_UART3_RX 19
48#define OMAP_DMA_CAMERA_IF_RX 20
49#define OMAP_DMA_MMC_TX 21
50#define OMAP_DMA_MMC_RX 22
51#define OMAP_DMA_NAND 23
52#define OMAP_DMA_IRQ_LCD_LINE 24
53#define OMAP_DMA_MEMORY_STICK 25
54#define OMAP_DMA_USB_W2FC_RX0 26
55#define OMAP_DMA_USB_W2FC_RX1 27
56#define OMAP_DMA_USB_W2FC_RX2 28
57#define OMAP_DMA_USB_W2FC_TX0 29
58#define OMAP_DMA_USB_W2FC_TX1 30
59#define OMAP_DMA_USB_W2FC_TX2 31
60
61/* These are only for 1610 */
62#define OMAP_DMA_CRYPTO_DES_IN 32
63#define OMAP_DMA_SPI_TX 33
64#define OMAP_DMA_SPI_RX 34
65#define OMAP_DMA_CRYPTO_HASH 35
66#define OMAP_DMA_CCP_ATTN 36
67#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
68#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
69#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
70#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
71#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
72#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
73#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
74#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
75#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
76#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
77#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
78#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
79#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
80#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
81#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
82#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
83#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
84#define OMAP_DMA_MMC2_TX 54
85#define OMAP_DMA_MMC2_RX 55
86#define OMAP_DMA_CRYPTO_DES_OUT 56
87
88
89#define OMAP_DMA_BASE (0xfffed800)
90#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
91#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
92#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
93#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
94#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
95#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
96#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
97#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
98#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
99#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
100#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
101#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
102#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
103#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
104#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
105#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
106#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
107#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
108#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
109#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
110
111#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
112#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
113#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
114#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
115#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
116#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
117
118#define OMAP1610_DMA_LCD_BASE (0xfffee300)
119#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
120#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
121#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
122#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
123#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
124#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
125#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
126#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
127#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
128#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
129#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
130#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
131#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
132#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
133#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
134#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
135#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
136
137
138/* Every LCh has its own set of the registers below */
139#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
140#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
141#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
142#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
143#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
144#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
145#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
146#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
147#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
148#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
149#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
150#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
151#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
152#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
153#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
154#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
155#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
156#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
157#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
158#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
159#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
160
161#define OMAP_DMA_TOUT_IRQ (1 << 0)
162#define OMAP_DMA_DROP_IRQ (1 << 1)
163#define OMAP_DMA_HALF_IRQ (1 << 2)
164#define OMAP_DMA_FRAME_IRQ (1 << 3)
165#define OMAP_DMA_LAST_IRQ (1 << 4)
166#define OMAP_DMA_BLOCK_IRQ (1 << 5)
167#define OMAP_DMA_SYNC_IRQ (1 << 6)
168
169#define OMAP_DMA_DATA_TYPE_S8 0x00
170#define OMAP_DMA_DATA_TYPE_S16 0x01
171#define OMAP_DMA_DATA_TYPE_S32 0x02
172
173#define OMAP_DMA_SYNC_ELEMENT 0x00
174#define OMAP_DMA_SYNC_FRAME 0x01
175#define OMAP_DMA_SYNC_BLOCK 0x02
176
177#define OMAP_DMA_PORT_EMIFF 0x00
178#define OMAP_DMA_PORT_EMIFS 0x01
179#define OMAP_DMA_PORT_OCP_T1 0x02
180#define OMAP_DMA_PORT_TIPB 0x03
181#define OMAP_DMA_PORT_OCP_T2 0x04
182#define OMAP_DMA_PORT_MPUI 0x05
183
184#define OMAP_DMA_AMODE_CONSTANT 0x00
185#define OMAP_DMA_AMODE_POST_INC 0x01
186#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
187#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
188
189/* LCD DMA block numbers */
190enum {
191 OMAP_LCD_DMA_B1_TOP,
192 OMAP_LCD_DMA_B1_BOTTOM,
193 OMAP_LCD_DMA_B2_TOP,
194 OMAP_LCD_DMA_B2_BOTTOM
195};
196
197enum omap_dma_burst_mode {
198 OMAP_DMA_DATA_BURST_DIS = 0,
199 OMAP_DMA_DATA_BURST_4,
200 OMAP_DMA_DATA_BURST_8
201};
202
203enum omap_dma_color_mode {
204 OMAP_DMA_COLOR_DIS = 0,
205 OMAP_DMA_CONSTANT_FILL,
206 OMAP_DMA_TRANSPARENT_COPY
207};
208
209extern void omap_set_dma_priority(int dst_port, int priority);
210extern int omap_request_dma(int dev_id, const char *dev_name,
211 void (* callback)(int lch, u16 ch_status, void *data),
212 void *data, int *dma_ch);
213extern void omap_enable_dma_irq(int ch, u16 irq_bits);
214extern void omap_disable_dma_irq(int ch, u16 irq_bits);
215extern void omap_free_dma(int ch);
216extern void omap_start_dma(int lch);
217extern void omap_stop_dma(int lch);
218extern void omap_set_dma_transfer_params(int lch, int data_type,
219 int elem_count, int frame_count,
220 int sync_mode);
221extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
222 u32 color);
223
224extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
225 unsigned long src_start);
226extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
227extern void omap_set_dma_src_data_pack(int lch, int enable);
228extern void omap_set_dma_src_burst_mode(int lch,
229 enum omap_dma_burst_mode burst_mode);
230
231extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
232 unsigned long dest_start);
233extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
234extern void omap_set_dma_dest_data_pack(int lch, int enable);
235extern void omap_set_dma_dest_burst_mode(int lch,
236 enum omap_dma_burst_mode burst_mode);
237
238extern void omap_dma_link_lch (int lch_head, int lch_queue);
239extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
240
241extern dma_addr_t omap_get_dma_src_pos(int lch);
242extern dma_addr_t omap_get_dma_dst_pos(int lch);
243extern void omap_clear_dma(int lch);
244
245/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
246extern int omap_dma_in_1510_mode(void);
247
248/* LCD DMA functions */
249extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
250 void *data);
251extern void omap_free_lcd_dma(void);
252extern void omap_setup_lcd_dma(void);
253extern void omap_enable_lcd_dma(void);
254extern void omap_stop_lcd_dma(void);
255extern void omap_set_lcd_dma_ext_controller(int external);
256extern void omap_set_lcd_dma_single_transfer(int single);
257extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
258 int data_type);
259extern void omap_set_lcd_dma_b1_rotation(int rotate);
260extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
261extern void omap_set_lcd_dma_b1_mirror(int mirror);
262extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
263
264#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
new file mode 100644
index 000000000000..57b126889b98
--- /dev/null
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -0,0 +1,32 @@
1/*
2 * include/asm-arm/arch-omap/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 .macro disable_fiq
12 .endm
13
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
16 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
17 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
18 mov \irqstat, #0xffffffff
19 bic \tmp, \irqstat, \tmp
20 tst \irqnr, \tmp
21 beq 1510f
22
23 ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
24 cmp \irqnr, #0
25 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
26 cmpeq \irqnr, #INT_IH2_IRQ
27 ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
28 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
29 addeqs \irqnr, \irqnr, #32
301510:
31 .endm
32
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
new file mode 100644
index 000000000000..676807dc50e1
--- /dev/null
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -0,0 +1,196 @@
1/*
2 * linux/include/asm-arm/arch-omap/fpga.h
3 *
4 * Interrupt handler for OMAP-1510 FPGA
5 *
6 * Copyright (C) 2001 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * Copyright (C) 2002 MontaVista Software, Inc.
10 *
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ASM_ARCH_OMAP_FPGA_H
20#define __ASM_ARCH_OMAP_FPGA_H
21
22#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510)
23extern void omap1510_fpga_init_irq(void);
24#else
25#define omap1510_fpga_init_irq() (0)
26#endif
27
28#define fpga_read(reg) __raw_readb(reg)
29#define fpga_write(val, reg) __raw_writeb(val, reg)
30
31/*
32 * ---------------------------------------------------------------------------
33 * H2/P2 Debug board FPGA
34 * ---------------------------------------------------------------------------
35 */
36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
43#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
44#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
45#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
46#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
47#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
48#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
49
50/* NOTE: most boards don't have a static mapping for the FPGA ... */
51struct h2p2_dbg_fpga {
52 /* offset 0x00 */
53 u16 smc91x[8];
54 /* offset 0x10 */
55 u16 fpga_rev;
56 u16 board_rev;
57 u16 gpio_outputs;
58 u16 leds;
59 /* offset 0x18 */
60 u16 misc_inputs;
61 u16 lan_status;
62 u16 lan_reset;
63 u16 reserved0;
64 /* offset 0x20 */
65 u16 ps2_data;
66 u16 ps2_ctrl;
67 /* plus also 4 rs232 ports ... */
68};
69
70/* LEDs definition on debug board (16 LEDs, all physically green) */
71#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
72#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
73#define H2P2_DBG_FPGA_LED_RED (1 << 13)
74#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
75/* cpu0 load-meter LEDs */
76#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
77#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
78#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
79
80
81/*
82 * ---------------------------------------------------------------------------
83 * OMAP-1510 FPGA
84 * ---------------------------------------------------------------------------
85 */
86#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */
87#define OMAP1510_FPGA_SIZE SZ_4K
88#define OMAP1510_FPGA_START 0x08000000 /* Physical */
89
90/* Revision */
91#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
92#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
93
94#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
95#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
96#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
97#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
98
99/* Interrupt status */
100#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
101#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
102
103/* Interrupt mask */
104#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
105#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
106
107/* Reset registers */
108#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
109#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
110
111#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
112#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
113#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
114#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
115#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
116#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
117#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
118#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
119#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
120#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
121
122#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
123
124#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
125#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
126#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
127#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
128#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
129#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
130#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
131#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
132#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
133#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
134#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
135
136#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
137
138/*
139 * Power up Giga UART driver, turn on HID clock.
140 * Turn off BT power, since we're not using it and it
141 * draws power.
142 */
143#define OMAP1510_FPGA_RESET_VALUE 0x42
144
145#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
146#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
147#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
148#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
149#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
150#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
151#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
152#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
153
154/*
155 * Innovator/OMAP1510 FPGA HID register bit definitions
156 */
157#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
158#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
159#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
160#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
161#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
162#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
163#define OMAP1510_FPGA_HID_rsrvd (1<<6)
164#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
165
166/* The FPGA IRQ is cascaded through GPIO_13 */
167#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
168
169/* IRQ Numbers for interrupts muxed through the FPGA */
170#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
171#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
172#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1)
173#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2)
174#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3)
175#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4)
176#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5)
177#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6)
178#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7)
179#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8)
180#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9)
181#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10)
182#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11)
183#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12)
184#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13)
185#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14)
186#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15)
187#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16)
188#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17)
189#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18)
190#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19)
191#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20)
192#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21)
193#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22)
194#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
195
196#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
new file mode 100644
index 000000000000..fad2fc93ee70
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -0,0 +1,69 @@
1/*
2 * linux/include/asm-arm/arch-omap/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <asm/arch/hardware.h>
30#include <asm/arch/irqs.h>
31#include <asm/io.h>
32
33#define OMAP_MPUIO_BASE 0xfffb5000
34#define OMAP_MPUIO_INPUT_LATCH 0x00
35#define OMAP_MPUIO_OUTPUT 0x04
36#define OMAP_MPUIO_IO_CNTL 0x08
37#define OMAP_MPUIO_KBR_LATCH 0x10
38#define OMAP_MPUIO_KBC 0x14
39#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
40#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
41#define OMAP_MPUIO_KBD_INT 0x20
42#define OMAP_MPUIO_GPIO_INT 0x24
43#define OMAP_MPUIO_KBD_MASKIT 0x28
44#define OMAP_MPUIO_GPIO_MASKIT 0x2c
45#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
46#define OMAP_MPUIO_LATCH 0x34
47
48#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
49#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
50
51#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
52 IH_MPUIO_BASE + ((nr) & 0x0f) : \
53 IH_GPIO_BASE + ((nr) & 0x3f))
54
55/* For EDGECTRL */
56#define OMAP_GPIO_NO_EDGE 0x00
57#define OMAP_GPIO_FALLING_EDGE 0x01
58#define OMAP_GPIO_RISING_EDGE 0x02
59#define OMAP_GPIO_BOTH_EDGES 0x03
60
61extern int omap_gpio_init(void); /* Call from board init only */
62extern int omap_request_gpio(int gpio);
63extern void omap_free_gpio(int gpio);
64extern void omap_set_gpio_direction(int gpio, int is_input);
65extern void omap_set_gpio_dataout(int gpio, int enable);
66extern int omap_get_gpio_datain(int gpio);
67extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
68
69#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
new file mode 100644
index 000000000000..37e06c782bdf
--- /dev/null
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -0,0 +1,324 @@
1/*
2 * linux/include/asm-arm/arch-omap/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#include <linux/config.h>
41#ifndef __ASSEMBLER__
42#include <asm/types.h>
43#include <asm/arch/cpu.h>
44#endif
45#include <asm/arch/io.h>
46
47/*
48 * ---------------------------------------------------------------------------
49 * Common definitions for all OMAP processors
50 * NOTE: Put all processor or board specific parts to the special header
51 * files.
52 * ---------------------------------------------------------------------------
53 */
54
55/*
56 * ----------------------------------------------------------------------------
57 * Clocks
58 * ----------------------------------------------------------------------------
59 */
60#define CLKGEN_REG_BASE (0xfffece00)
61#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
62#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
63#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
64#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
65#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
66#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
67#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
68#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
69
70#define CK_RATEF 1
71#define CK_IDLEF 2
72#define CK_ENABLEF 4
73#define CK_SELECTF 8
74#define SETARM_IDLE_SHIFT
75
76/* DPLL control registers */
77#define DPLL_CTL (0xfffecf00)
78
79/* DSP clock control */
80#define DSP_CONFIG_REG_BASE (0xe1008000)
81#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
82#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
83
84/*
85 * ---------------------------------------------------------------------------
86 * UPLD
87 * ---------------------------------------------------------------------------
88 */
89#define ULPD_REG_BASE (0xfffe0800)
90#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
91#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
92# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
93# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
94#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
95# define SOFT_UDC_REQ (1 << 4)
96# define SOFT_USB_CLK_REQ (1 << 3)
97# define SOFT_DPLL_REQ (1 << 0)
98#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
99#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
100#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
101#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
102#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
103# define DIS_MMC2_DPLL_REQ (1 << 11)
104# define DIS_MMC1_DPLL_REQ (1 << 10)
105# define DIS_UART3_DPLL_REQ (1 << 9)
106# define DIS_UART2_DPLL_REQ (1 << 8)
107# define DIS_UART1_DPLL_REQ (1 << 7)
108# define DIS_USB_HOST_DPLL_REQ (1 << 6)
109#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
110#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
111
112/*
113 * ---------------------------------------------------------------------------
114 * Watchdog timer
115 * ---------------------------------------------------------------------------
116 */
117
118/* Watchdog timer within the OMAP3.2 gigacell */
119#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
120#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
121#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
122#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
123#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
124
125/*
126 * ---------------------------------------------------------------------------
127 * Interrupts
128 * ---------------------------------------------------------------------------
129 */
130#define OMAP_IH1_BASE 0xfffecb00
131#define OMAP_IH2_BASE 0xfffe0000
132
133#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
134#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
135#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
136#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
137#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
138#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
139#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
140
141#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
142#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
143#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
144#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
145#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
146#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
147#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
148
149#define IRQ_ITR_REG_OFFSET 0x00
150#define IRQ_MIR_REG_OFFSET 0x04
151#define IRQ_SIR_IRQ_REG_OFFSET 0x10
152#define IRQ_SIR_FIQ_REG_OFFSET 0x14
153#define IRQ_CONTROL_REG_OFFSET 0x18
154#define IRQ_ISR_REG_OFFSET 0x9c
155#define IRQ_ILR0_REG_OFFSET 0x1c
156#define IRQ_GMR_REG_OFFSET 0xa0
157
158/*
159 * ----------------------------------------------------------------------------
160 * System control registers
161 * ----------------------------------------------------------------------------
162 */
163#define MOD_CONF_CTRL_0 0xfffe1080
164#define MOD_CONF_CTRL_1 0xfffe1110
165
166/*
167 * ----------------------------------------------------------------------------
168 * Pin multiplexing registers
169 * ----------------------------------------------------------------------------
170 */
171#define FUNC_MUX_CTRL_0 0xfffe1000
172#define FUNC_MUX_CTRL_1 0xfffe1004
173#define FUNC_MUX_CTRL_2 0xfffe1008
174#define COMP_MODE_CTRL_0 0xfffe100c
175#define FUNC_MUX_CTRL_3 0xfffe1010
176#define FUNC_MUX_CTRL_4 0xfffe1014
177#define FUNC_MUX_CTRL_5 0xfffe1018
178#define FUNC_MUX_CTRL_6 0xfffe101C
179#define FUNC_MUX_CTRL_7 0xfffe1020
180#define FUNC_MUX_CTRL_8 0xfffe1024
181#define FUNC_MUX_CTRL_9 0xfffe1028
182#define FUNC_MUX_CTRL_A 0xfffe102C
183#define FUNC_MUX_CTRL_B 0xfffe1030
184#define FUNC_MUX_CTRL_C 0xfffe1034
185#define FUNC_MUX_CTRL_D 0xfffe1038
186#define PULL_DWN_CTRL_0 0xfffe1040
187#define PULL_DWN_CTRL_1 0xfffe1044
188#define PULL_DWN_CTRL_2 0xfffe1048
189#define PULL_DWN_CTRL_3 0xfffe104c
190#define PULL_DWN_CTRL_4 0xfffe10ac
191
192/* OMAP-1610 specific multiplexing registers */
193#define FUNC_MUX_CTRL_E 0xfffe1090
194#define FUNC_MUX_CTRL_F 0xfffe1094
195#define FUNC_MUX_CTRL_10 0xfffe1098
196#define FUNC_MUX_CTRL_11 0xfffe109c
197#define FUNC_MUX_CTRL_12 0xfffe10a0
198#define PU_PD_SEL_0 0xfffe10b4
199#define PU_PD_SEL_1 0xfffe10b8
200#define PU_PD_SEL_2 0xfffe10bc
201#define PU_PD_SEL_3 0xfffe10c0
202#define PU_PD_SEL_4 0xfffe10c4
203
204/* Timer32K for 1610 and 1710*/
205#define OMAP_TIMER32K_BASE 0xFFFBC400
206
207/*
208 * ---------------------------------------------------------------------------
209 * TIPB bus interface
210 * ---------------------------------------------------------------------------
211 */
212#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
213#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
214#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
215#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
216
217/*
218 * ----------------------------------------------------------------------------
219 * MPUI interface
220 * ----------------------------------------------------------------------------
221 */
222#define MPUI_BASE (0xfffec900)
223#define MPUI_CTRL (MPUI_BASE + 0x0)
224#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
225#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
226#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
227#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
228#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
229#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
230#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
231
232/*
233 * ----------------------------------------------------------------------------
234 * LED Pulse Generator
235 * ----------------------------------------------------------------------------
236 */
237#define OMAP_LPG1_BASE 0xfffbd000
238#define OMAP_LPG2_BASE 0xfffbd800
239#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
240#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
241#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
242#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
243
244#ifndef __ASSEMBLER__
245
246/*
247 * ---------------------------------------------------------------------------
248 * Serial ports
249 * ---------------------------------------------------------------------------
250 */
251#define OMAP_UART1_BASE (unsigned char *)0xfffb0000
252#define OMAP_UART2_BASE (unsigned char *)0xfffb0800
253#define OMAP_UART3_BASE (unsigned char *)0xfffb9800
254#define OMAP_MAX_NR_PORTS 3
255#define OMAP1510_BASE_BAUD (12000000/16)
256#define OMAP16XX_BASE_BAUD (48000000/16)
257
258#define is_omap_port(p) ({int __ret = 0; \
259 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
260 p == IO_ADDRESS(OMAP_UART2_BASE) || \
261 p == IO_ADDRESS(OMAP_UART3_BASE)) \
262 __ret = 1; \
263 __ret; \
264 })
265
266/*
267 * ---------------------------------------------------------------------------
268 * Processor specific defines
269 * ---------------------------------------------------------------------------
270 */
271#ifdef CONFIG_ARCH_OMAP730
272#include "omap730.h"
273#endif
274
275#ifdef CONFIG_ARCH_OMAP1510
276#include "omap1510.h"
277#endif
278
279#ifdef CONFIG_ARCH_OMAP16XX
280#include "omap16xx.h"
281#endif
282
283/*
284 * ---------------------------------------------------------------------------
285 * Board specific defines
286 * ---------------------------------------------------------------------------
287 */
288
289#ifdef CONFIG_MACH_OMAP_INNOVATOR
290#include "board-innovator.h"
291#endif
292
293#ifdef CONFIG_MACH_OMAP_H2
294#include "board-h2.h"
295#endif
296
297#ifdef CONFIG_MACH_OMAP_PERSEUS2
298#include "board-perseus2.h"
299#endif
300
301#ifdef CONFIG_MACH_OMAP_H3
302#include "board-h3.h"
303#endif
304
305#ifdef CONFIG_MACH_OMAP_H4
306#include "board-h4.h"
307#error "Support for H4 board not yet implemented."
308#endif
309
310#ifdef CONFIG_MACH_OMAP_OSK
311#include "board-osk.h"
312#endif
313
314#ifdef CONFIG_MACH_VOICEBLUE
315#include "board-voiceblue.h"
316#endif
317
318#ifdef CONFIG_MACH_NETSTAR
319#include "board-netstar.h"
320#endif
321
322#endif /* !__ASSEMBLER__ */
323
324#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
new file mode 100644
index 000000000000..1c8c9fcc766e
--- /dev/null
+++ b/include/asm-arm/arch-omap/io.h
@@ -0,0 +1,107 @@
1/*
2 * linux/include/asm-arm/arch-omap/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from linux/include/asm-arm/arch-sa1100/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Modifications:
30 * 06-12-1997 RMK Created.
31 * 07-04-1999 RMK Major cleanup
32 */
33
34#ifndef __ASM_ARM_ARCH_IO_H
35#define __ASM_ARM_ARCH_IO_H
36
37#define IO_SPACE_LIMIT 0xffffffff
38
39/*
40 * We don't actually have real ISA nor PCI buses, but there is so many
41 * drivers out there that might just work if we fake them...
42 */
43#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
44#define __mem_pci(a) (a)
45#define __mem_isa(a) (a)
46
47/*
48 * ----------------------------------------------------------------------------
49 * I/O mapping
50 * ----------------------------------------------------------------------------
51 */
52#define IO_PHYS 0xFFFB0000
53#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
54#define IO_VIRT (IO_PHYS - IO_OFFSET)
55#define IO_SIZE 0x40000
56#define IO_ADDRESS(x) ((x) - IO_OFFSET)
57
58#define PCIO_BASE 0
59
60#define io_p2v(x) ((x) - IO_OFFSET)
61#define io_v2p(x) ((x) + IO_OFFSET)
62
63#ifndef __ASSEMBLER__
64
65/*
66 * Functions to access the OMAP IO region
67 *
68 * NOTE: - Use omap_read/write[bwl] for physical register addresses
69 * - Use __raw_read/write[bwl]() for virtual register addresses
70 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
71 * - DO NOT use hardcoded virtual addresses to allow changing the
72 * IO address space again if needed
73 */
74#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
75#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
76#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
77
78#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
79#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
80#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
81
82/* 16 bit uses LDRH/STRH, base +/- offset_8 */
83typedef struct { volatile u16 offset[256]; } __regbase16;
84#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
85 ->offset[((vaddr)&0xff)>>1]
86#define __REG16(paddr) __REGV16(io_p2v(paddr))
87
88/* 8/32 bit uses LDR/STR, base +/- offset_12 */
89typedef struct { volatile u8 offset[4096]; } __regbase8;
90#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
91 ->offset[((vaddr)&4095)>>0]
92#define __REG8(paddr) __REGV8(io_p2v(paddr))
93
94typedef struct { volatile u32 offset[4096]; } __regbase32;
95#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
96 ->offset[((vaddr)&4095)>>2]
97#define __REG32(paddr) __REGV32(io_p2v(paddr))
98
99#else
100
101#define __REG8(paddr) io_p2v(paddr)
102#define __REG16(paddr) io_p2v(paddr)
103#define __REG32(paddr) io_p2v(paddr)
104
105#endif
106
107#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
new file mode 100644
index 000000000000..6701fd9e5f9b
--- /dev/null
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -0,0 +1,255 @@
1/*
2 * linux/include/asm-arm/arch-omap/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
22 * are different.
23 */
24
25#ifndef __ASM_ARCH_OMAP1510_IRQS_H
26#define __ASM_ARCH_OMAP1510_IRQS_H
27
28/*
29 * IRQ numbers for interrupt handler 1
30 *
31 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
32 *
33 */
34#define INT_IH2_IRQ 0
35#define INT_CAMERA 1
36#define INT_FIQ 3
37#define INT_RTDX 6
38#define INT_DSP_MMU_ABORT 7
39#define INT_HOST 8
40#define INT_ABORT 9
41#define INT_DSP_MAILBOX1 10
42#define INT_DSP_MAILBOX2 11
43#define INT_BRIDGE_PRIV 13
44#define INT_GPIO_BANK1 14
45#define INT_UART3 15
46#define INT_TIMER3 16
47#define INT_DMA_CH0_6 19
48#define INT_DMA_CH1_7 20
49#define INT_DMA_CH2_8 21
50#define INT_DMA_CH3 22
51#define INT_DMA_CH4 23
52#define INT_DMA_CH5 24
53#define INT_DMA_LCD 25
54#define INT_TIMER1 26
55#define INT_WD_TIMER 27
56#define INT_BRIDGE_PUB 28
57#define INT_TIMER2 30
58#define INT_LCD_CTRL 31
59
60/*
61 * OMAP-1510 specific IRQ numbers for interrupt handler 1
62 */
63#define INT_1510_RES2 2
64#define INT_1510_SPI_TX 4
65#define INT_1510_SPI_RX 5
66#define INT_1510_RES12 12
67#define INT_1510_LB_MMU 17
68#define INT_1510_RES18 18
69#define INT_1510_LOCAL_BUS 29
70
71/*
72 * OMAP-1610 specific IRQ numbers for interrupt handler 1
73 */
74#define INT_1610_IH2_FIQ 2
75#define INT_1610_McBSP2_TX 4
76#define INT_1610_McBSP2_RX 5
77#define INT_1610_LCD_LINE 12
78#define INT_1610_GPTIMER1 17
79#define INT_1610_GPTIMER2 18
80#define INT_1610_SSR_FIFO_0 29
81
82/*
83 * OMAP-730 specific IRQ numbers for interrupt handler 1
84 */
85#define INT_730_IH2_FIQ 0
86#define INT_730_IH2_IRQ 1
87#define INT_730_USB_NON_ISO 2
88#define INT_730_USB_ISO 3
89#define INT_730_ICR 4
90#define INT_730_EAC 5
91#define INT_730_GPIO_BANK1 6
92#define INT_730_GPIO_BANK2 7
93#define INT_730_GPIO_BANK3 8
94#define INT_730_McBSP2TX 10
95#define INT_730_McBSP2RX 11
96#define INT_730_McBSP2RX_OVF 12
97#define INT_730_LCD_LINE 14
98#define INT_730_GSM_PROTECT 15
99#define INT_730_TIMER3 16
100#define INT_730_GPIO_BANK5 17
101#define INT_730_GPIO_BANK6 18
102#define INT_730_SPGIO_WR 29
103
104/*
105 * IRQ numbers for interrupt handler 2
106 *
107 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
108 */
109#define IH2_BASE 32
110
111#define INT_KEYBOARD (1 + IH2_BASE)
112#define INT_uWireTX (2 + IH2_BASE)
113#define INT_uWireRX (3 + IH2_BASE)
114#define INT_I2C (4 + IH2_BASE)
115#define INT_MPUIO (5 + IH2_BASE)
116#define INT_USB_HHC_1 (6 + IH2_BASE)
117#define INT_McBSP3TX (10 + IH2_BASE)
118#define INT_McBSP3RX (11 + IH2_BASE)
119#define INT_McBSP1TX (12 + IH2_BASE)
120#define INT_McBSP1RX (13 + IH2_BASE)
121#define INT_UART1 (14 + IH2_BASE)
122#define INT_UART2 (15 + IH2_BASE)
123#define INT_BT_MCSI1TX (16 + IH2_BASE)
124#define INT_BT_MCSI1RX (17 + IH2_BASE)
125#define INT_USB_W2FC (20 + IH2_BASE)
126#define INT_1WIRE (21 + IH2_BASE)
127#define INT_OS_TIMER (22 + IH2_BASE)
128#define INT_MMC (23 + IH2_BASE)
129#define INT_GAUGE_32K (24 + IH2_BASE)
130#define INT_RTC_TIMER (25 + IH2_BASE)
131#define INT_RTC_ALARM (26 + IH2_BASE)
132#define INT_MEM_STICK (27 + IH2_BASE)
133#define INT_DSP_MMU (28 + IH2_BASE)
134
135/*
136 * OMAP-1510 specific IRQ numbers for interrupt handler 2
137 */
138#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
139#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
140
141/*
142 * OMAP-1610 specific IRQ numbers for interrupt handler 2
143 */
144#define INT_1610_FAC (0 + IH2_BASE)
145#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
146#define INT_1610_USB_OTG (8 + IH2_BASE)
147#define INT_1610_SoSSI (9 + IH2_BASE)
148#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
149#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
150#define INT_1610_STI (32 + IH2_BASE)
151#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
152#define INT_1610_GPTIMER3 (34 + IH2_BASE)
153#define INT_1610_GPTIMER4 (35 + IH2_BASE)
154#define INT_1610_GPTIMER5 (36 + IH2_BASE)
155#define INT_1610_GPTIMER6 (37 + IH2_BASE)
156#define INT_1610_GPTIMER7 (38 + IH2_BASE)
157#define INT_1610_GPTIMER8 (39 + IH2_BASE)
158#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
159#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
160#define INT_1610_MMC2 (42 + IH2_BASE)
161#define INT_1610_CF (43 + IH2_BASE)
162#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
163#define INT_1610_SPI (49 + IH2_BASE)
164#define INT_1610_DMA_CH6 (53 + IH2_BASE)
165#define INT_1610_DMA_CH7 (54 + IH2_BASE)
166#define INT_1610_DMA_CH8 (55 + IH2_BASE)
167#define INT_1610_DMA_CH9 (56 + IH2_BASE)
168#define INT_1610_DMA_CH10 (57 + IH2_BASE)
169#define INT_1610_DMA_CH11 (58 + IH2_BASE)
170#define INT_1610_DMA_CH12 (59 + IH2_BASE)
171#define INT_1610_DMA_CH13 (60 + IH2_BASE)
172#define INT_1610_DMA_CH14 (61 + IH2_BASE)
173#define INT_1610_DMA_CH15 (62 + IH2_BASE)
174#define INT_1610_NAND (63 + IH2_BASE)
175
176/*
177 * OMAP-730 specific IRQ numbers for interrupt handler 2
178 */
179#define INT_730_HW_ERRORS (0 + IH2_BASE)
180#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
181#define INT_730_CFCD (2 + IH2_BASE)
182#define INT_730_CFIREQ (3 + IH2_BASE)
183#define INT_730_I2C (4 + IH2_BASE)
184#define INT_730_PCC (5 + IH2_BASE)
185#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
186#define INT_730_SPI_100K_1 (7 + IH2_BASE)
187#define INT_730_SYREN_SPI (8 + IH2_BASE)
188#define INT_730_VLYNQ (9 + IH2_BASE)
189#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
190#define INT_730_McBSP1TX (11 + IH2_BASE)
191#define INT_730_McBSP1RX (12 + IH2_BASE)
192#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
193#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
194#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
195#define INT_730_MCSI (16 + IH2_BASE)
196#define INT_730_uWireTX (17 + IH2_BASE)
197#define INT_730_uWireRX (18 + IH2_BASE)
198#define INT_730_SMC_CD (19 + IH2_BASE)
199#define INT_730_SMC_IREQ (20 + IH2_BASE)
200#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
201#define INT_730_TIMER32K (22 + IH2_BASE)
202#define INT_730_MMC_SDIO (23 + IH2_BASE)
203#define INT_730_UPLD (24 + IH2_BASE)
204#define INT_730_USB_HHC_1 (27 + IH2_BASE)
205#define INT_730_USB_HHC_2 (28 + IH2_BASE)
206#define INT_730_USB_GENI (29 + IH2_BASE)
207#define INT_730_USB_OTG (30 + IH2_BASE)
208#define INT_730_CAMERA_IF (31 + IH2_BASE)
209#define INT_730_RNG (32 + IH2_BASE)
210#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
211#define INT_730_DBB_RF_EN (34 + IH2_BASE)
212#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
213#define INT_730_SHA1_MD5 (36 + IH2_BASE)
214#define INT_730_SPI_100K_2 (37 + IH2_BASE)
215#define INT_730_RNG_IDLE (38 + IH2_BASE)
216#define INT_730_MPUIO (39 + IH2_BASE)
217#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
218#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
219#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
220#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
221#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
222#define INT_730_DMA_CH6 (53 + IH2_BASE)
223#define INT_730_DMA_CH7 (54 + IH2_BASE)
224#define INT_730_DMA_CH8 (55 + IH2_BASE)
225#define INT_730_DMA_CH9 (56 + IH2_BASE)
226#define INT_730_DMA_CH10 (57 + IH2_BASE)
227#define INT_730_DMA_CH11 (58 + IH2_BASE)
228#define INT_730_DMA_CH12 (59 + IH2_BASE)
229#define INT_730_DMA_CH13 (60 + IH2_BASE)
230#define INT_730_DMA_CH14 (61 + IH2_BASE)
231#define INT_730_DMA_CH15 (62 + IH2_BASE)
232#define INT_730_NAND (63 + IH2_BASE)
233
234/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
235 * 16 MPUIO lines */
236#define OMAP_MAX_GPIO_LINES 192
237#define IH_GPIO_BASE (128 + IH2_BASE)
238#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
239#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
240
241#ifndef __ASSEMBLY__
242extern void omap_init_irq(void);
243#endif
244
245/*
246 * The definition of NR_IRQS is in board-specific header file, which is
247 * included via hardware.h
248 */
249#include <asm/arch/hardware.h>
250
251#ifndef NR_IRQS
252#define NR_IRQS IH_BOARD_BASE
253#endif
254
255#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
new file mode 100644
index 000000000000..305bdeb16ab8
--- /dev/null
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -0,0 +1,257 @@
1/*
2 * linux/include/asm-arm/arch-omap/gpio.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <asm/arch/hardware.h>
28
29#define OMAP730_MCBSP1_BASE 0xfffb1000
30#define OMAP730_MCBSP2_BASE 0xfffb1800
31
32#define OMAP1510_MCBSP1_BASE 0xe1011800
33#define OMAP1510_MCBSP2_BASE 0xfffb1000
34#define OMAP1510_MCBSP3_BASE 0xe1017000
35
36#define OMAP1610_MCBSP1_BASE 0xe1011800
37#define OMAP1610_MCBSP2_BASE 0xfffb1000
38#define OMAP1610_MCBSP3_BASE 0xe1017000
39
40#define OMAP_MCBSP_REG_DRR2 0x00
41#define OMAP_MCBSP_REG_DRR1 0x02
42#define OMAP_MCBSP_REG_DXR2 0x04
43#define OMAP_MCBSP_REG_DXR1 0x06
44#define OMAP_MCBSP_REG_SPCR2 0x08
45#define OMAP_MCBSP_REG_SPCR1 0x0a
46#define OMAP_MCBSP_REG_RCR2 0x0c
47#define OMAP_MCBSP_REG_RCR1 0x0e
48#define OMAP_MCBSP_REG_XCR2 0x10
49#define OMAP_MCBSP_REG_XCR1 0x12
50#define OMAP_MCBSP_REG_SRGR2 0x14
51#define OMAP_MCBSP_REG_SRGR1 0x16
52#define OMAP_MCBSP_REG_MCR2 0x18
53#define OMAP_MCBSP_REG_MCR1 0x1a
54#define OMAP_MCBSP_REG_RCERA 0x1c
55#define OMAP_MCBSP_REG_RCERB 0x1e
56#define OMAP_MCBSP_REG_XCERA 0x20
57#define OMAP_MCBSP_REG_XCERB 0x22
58#define OMAP_MCBSP_REG_PCR0 0x24
59#define OMAP_MCBSP_REG_RCERC 0x26
60#define OMAP_MCBSP_REG_RCERD 0x28
61#define OMAP_MCBSP_REG_XCERC 0x2A
62#define OMAP_MCBSP_REG_XCERD 0x2C
63#define OMAP_MCBSP_REG_RCERE 0x2E
64#define OMAP_MCBSP_REG_RCERF 0x30
65#define OMAP_MCBSP_REG_XCERE 0x32
66#define OMAP_MCBSP_REG_XCERF 0x34
67#define OMAP_MCBSP_REG_RCERG 0x36
68#define OMAP_MCBSP_REG_RCERH 0x38
69#define OMAP_MCBSP_REG_XCERG 0x3A
70#define OMAP_MCBSP_REG_XCERH 0x3C
71
72#define OMAP_MAX_MCBSP_COUNT 3
73
74#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
75#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
76
77/************************** McBSP SPCR1 bit definitions ***********************/
78#define RRST 0x0001
79#define RRDY 0x0002
80#define RFULL 0x0004
81#define RSYNC_ERR 0x0008
82#define RINTM(value) ((value)<<4) /* bits 4:5 */
83#define ABIS 0x0040
84#define DXENA 0x0080
85#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
86#define RJUST(value) ((value)<<13) /* bits 13:14 */
87#define DLB 0x8000
88
89/************************** McBSP SPCR2 bit definitions ***********************/
90#define XRST 0x0001
91#define XRDY 0x0002
92#define XEMPTY 0x0004
93#define XSYNC_ERR 0x0008
94#define XINTM(value) ((value)<<4) /* bits 4:5 */
95#define GRST 0x0040
96#define FRST 0x0080
97#define SOFT 0x0100
98#define FREE 0x0200
99
100/************************** McBSP PCR bit definitions *************************/
101#define CLKRP 0x0001
102#define CLKXP 0x0002
103#define FSRP 0x0004
104#define FSXP 0x0008
105#define DR_STAT 0x0010
106#define DX_STAT 0x0020
107#define CLKS_STAT 0x0040
108#define SCLKME 0x0080
109#define CLKRM 0x0100
110#define CLKXM 0x0200
111#define FSRM 0x0400
112#define FSXM 0x0800
113#define RIOEN 0x1000
114#define XIOEN 0x2000
115#define IDLE_EN 0x4000
116
117/************************** McBSP RCR1 bit definitions ************************/
118#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
119#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
120
121/************************** McBSP XCR1 bit definitions ************************/
122#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
123#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
124
125/*************************** McBSP RCR2 bit definitions ***********************/
126#define RDATDLY(value) (value) /* Bits 0:1 */
127#define RFIG 0x0004
128#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
129#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
130#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
131#define RPHASE 0x8000
132
133/*************************** McBSP XCR2 bit definitions ***********************/
134#define XDATDLY(value) (value) /* Bits 0:1 */
135#define XFIG 0x0004
136#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
137#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
138#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
139#define XPHASE 0x8000
140
141/************************* McBSP SRGR1 bit definitions ************************/
142#define CLKGDV(value) (value) /* Bits 0:7 */
143#define FWID(value) ((value)<<8) /* Bits 8:15 */
144
145/************************* McBSP SRGR2 bit definitions ************************/
146#define FPER(value) (value) /* Bits 0:11 */
147#define FSGM 0x1000
148#define CLKSM 0x2000
149#define CLKSP 0x4000
150#define GSYNC 0x8000
151
152/************************* McBSP MCR1 bit definitions *************************/
153#define RMCM 0x0001
154#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
155#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
156#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
157
158/************************* McBSP MCR2 bit definitions *************************/
159#define XMCM(value) (value) /* Bits 0:1 */
160#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
161#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
162#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
163
164
165/* we don't do multichannel for now */
166struct omap_mcbsp_reg_cfg {
167 u16 spcr2;
168 u16 spcr1;
169 u16 rcr2;
170 u16 rcr1;
171 u16 xcr2;
172 u16 xcr1;
173 u16 srgr2;
174 u16 srgr1;
175 u16 mcr2;
176 u16 mcr1;
177 u16 pcr0;
178 u16 rcerc;
179 u16 rcerd;
180 u16 xcerc;
181 u16 xcerd;
182 u16 rcere;
183 u16 rcerf;
184 u16 xcere;
185 u16 xcerf;
186 u16 rcerg;
187 u16 rcerh;
188 u16 xcerg;
189 u16 xcerh;
190};
191
192typedef enum {
193 OMAP_MCBSP1 = 0,
194 OMAP_MCBSP2,
195 OMAP_MCBSP3,
196} omap_mcbsp_id;
197
198typedef enum {
199 OMAP_MCBSP_WORD_8 = 0,
200 OMAP_MCBSP_WORD_12,
201 OMAP_MCBSP_WORD_16,
202 OMAP_MCBSP_WORD_20,
203 OMAP_MCBSP_WORD_24,
204 OMAP_MCBSP_WORD_32,
205} omap_mcbsp_word_length;
206
207typedef enum {
208 OMAP_MCBSP_CLK_RISING = 0,
209 OMAP_MCBSP_CLK_FALLING,
210} omap_mcbsp_clk_polarity;
211
212typedef enum {
213 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
214 OMAP_MCBSP_FS_ACTIVE_LOW,
215} omap_mcbsp_fs_polarity;
216
217typedef enum {
218 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
219 OMAP_MCBSP_CLK_STP_MODE_DELAY,
220} omap_mcbsp_clk_stp_mode;
221
222
223/******* SPI specific mode **********/
224typedef enum {
225 OMAP_MCBSP_SPI_MASTER = 0,
226 OMAP_MCBSP_SPI_SLAVE,
227} omap_mcbsp_spi_mode;
228
229struct omap_mcbsp_spi_cfg {
230 omap_mcbsp_spi_mode spi_mode;
231 omap_mcbsp_clk_polarity rx_clock_polarity;
232 omap_mcbsp_clk_polarity tx_clock_polarity;
233 omap_mcbsp_fs_polarity fsx_polarity;
234 u8 clk_div;
235 omap_mcbsp_clk_stp_mode clk_stp_mode;
236 omap_mcbsp_word_length word_length;
237};
238
239void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
240int omap_mcbsp_request(unsigned int id);
241void omap_mcbsp_free(unsigned int id);
242void omap_mcbsp_start(unsigned int id);
243void omap_mcbsp_stop(unsigned int id);
244void omap_mcbsp_xmit_word(unsigned int id, u32 word);
245u32 omap_mcbsp_recv_word(unsigned int id);
246
247int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
248int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
249
250/* SPI specific API */
251void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
252
253/* Polled read/write functions */
254int omap_mcbsp_pollread(unsigned int id, u16 * buf);
255int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
256
257#endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
new file mode 100644
index 000000000000..f6b57dd846a3
--- /dev/null
+++ b/include/asm-arm/arch-omap/memory.h
@@ -0,0 +1,87 @@
1/*
2 * linux/include/asm-arm/arch-omap/memory.h
3 *
4 * Memory map for OMAP-1510 and 1610
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
10 * Copyright (C) 1999 ARM Limited
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ASM_ARCH_MEMORY_H
34#define __ASM_ARCH_MEMORY_H
35
36/*
37 * Physical DRAM offset.
38 */
39#define PHYS_OFFSET (0x10000000UL)
40
41/*
42 * OMAP-1510 Local Bus address offset
43 */
44#define OMAP1510_LB_OFFSET (0x30000000UL)
45
46/*
47 * Conversion between SDRAM and fake PCI bus, used by USB
48 * NOTE: Physical address must be converted to Local Bus address
49 * on OMAP-1510 only
50 */
51
52/*
53 * Bus address is physical address, except for OMAP-1510 Local Bus.
54 */
55#define __virt_to_bus(x) __virt_to_phys(x)
56#define __bus_to_virt(x) __phys_to_virt(x)
57
58/*
59 * OMAP-1510 bus address is translated into a Local Bus address if the
60 * OMAP bus type is lbus. We do the address translation based on the
61 * device overriding the defaults used in the dma-mapping API.
62 * Note that the is_lbus_device() test is not very efficient on 1510
63 * because of the strncmp().
64 */
65#ifdef CONFIG_ARCH_OMAP1510
66
67#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
68#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
69#define is_lbus_device(dev) (cpu_is_omap1510() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
70
71#define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \
72 (dma_addr_t)virt_to_lbus(page_address(page)) : \
73 (dma_addr_t)__virt_to_bus(page_address(page));})
74
75#define __arch_dma_to_virt(dev, addr) ({is_lbus_device(dev) ? \
76 lbus_to_virt(addr) : \
77 __bus_to_virt(addr);})
78
79#define __arch_virt_to_dma(dev, addr) ({is_lbus_device(dev) ? \
80 virt_to_lbus(addr) : \
81 __virt_to_bus(addr);})
82
83#endif /* CONFIG_ARCH_OMAP1510 */
84
85#define PHYS_TO_NID(addr) (0)
86#endif
87
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
new file mode 100644
index 000000000000..39f99decbb7b
--- /dev/null
+++ b/include/asm-arm/arch-omap/mux.h
@@ -0,0 +1,561 @@
1/*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2003 Nokia Corporation
8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * NOTE: Please use the following naming style for new pin entries.
26 * For example, W8_1610_MMC2_DAT0, where:
27 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */
39
40#ifndef __ASM_ARCH_MUX_H
41#define __ASM_ARCH_MUX_H
42
43#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
44#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
45
46#ifdef CONFIG_OMAP_MUX_DEBUG
47#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
48 .mux_reg = FUNC_MUX_CTRL_##reg, \
49 .mask_offset = mode_offset, \
50 .mask = mode,
51
52#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
53 .pull_reg = PULL_DWN_CTRL_##reg, \
54 .pull_bit = bit, \
55 .pull_val = status,
56
57#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status,
60
61#else
62
63#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
64 .mask_offset = mode_offset, \
65 .mask = mode,
66
67#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
70
71#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
72 .pu_pd_val = status,
73
74#endif /* CONFIG_OMAP_MUX_DEBUG */
75
76#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
77 pull_reg, pull_bit, pull_status, \
78 pu_pd_reg, pu_pd_status, debug_status) \
79{ \
80 .name = desc, \
81 .debug = debug_status, \
82 MUX_REG(mux_reg, mode_offset, mode) \
83 PULL_REG(pull_reg, pull_bit, pull_status) \
84 PU_PD_REG(pu_pd_reg, pu_pd_status) \
85},
86
87#define PULL_DISABLED 0
88#define PULL_ENABLED 1
89
90#define PULL_DOWN 0
91#define PULL_UP 1
92
93typedef struct {
94 char *name;
95 unsigned char busy;
96 unsigned char debug;
97
98 const char *mux_reg_name;
99 const unsigned int mux_reg;
100 const unsigned char mask_offset;
101 const unsigned char mask;
102
103 const char *pull_name;
104 const unsigned int pull_reg;
105 const unsigned char pull_val;
106 const unsigned char pull_bit;
107
108 const char *pu_pd_name;
109 const unsigned int pu_pd_reg;
110 const unsigned char pu_pd_val;
111} reg_cfg_set;
112
113/*
114 * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
115 * device. See also reg_cfg_table below for the register values.
116 */
117typedef enum {
118 /* UART1 (BT_UART_GATING)*/
119 UART1_TX = 0,
120 UART1_RTS,
121
122 /* UART2 (COM_UART_GATING)*/
123 UART2_TX,
124 UART2_RX,
125 UART2_CTS,
126 UART2_RTS,
127
128 /* UART3 (GIGA_UART_GATING) */
129 UART3_TX,
130 UART3_RX,
131 UART3_CTS,
132 UART3_RTS,
133 UART3_CLKREQ,
134 UART3_BCLK, /* 12MHz clock out */
135 Y15_1610_UART3_RTS,
136
137 /* PWT & PWL */
138 PWT,
139 PWL,
140
141 /* USB master generic */
142 R18_USB_VBUS,
143 R18_1510_USB_GPIO0,
144 W4_USB_PUEN,
145 W4_USB_CLKO,
146 W4_USB_HIGHZ,
147 W4_GPIO58,
148
149 /* USB1 master */
150 USB1_SUSP,
151 USB1_SEO,
152 W13_1610_USB1_SE0,
153 USB1_TXEN,
154 USB1_TXD,
155 USB1_VP,
156 USB1_VM,
157 USB1_RCV,
158 USB1_SPEED,
159 R13_1610_USB1_SPEED,
160 R13_1710_USB1_SE0,
161
162 /* USB2 master */
163 USB2_SUSP,
164 USB2_VP,
165 USB2_TXEN,
166 USB2_VM,
167 USB2_RCV,
168 USB2_SEO,
169 USB2_TXD,
170
171 /* OMAP-1510 GPIO */
172 R18_1510_GPIO0,
173 R19_1510_GPIO1,
174 M14_1510_GPIO2,
175
176 /* OMAP1610 GPIO */
177 P18_1610_GPIO3,
178 Y15_1610_GPIO17,
179
180 /* OMAP-1710 GPIO */
181 R18_1710_GPIO0,
182 V2_1710_GPIO10,
183 N21_1710_GPIO14,
184 W15_1710_GPIO40,
185
186 /* MPUIO */
187 MPUIO2,
188 MPUIO4,
189 MPUIO5,
190 T20_1610_MPUIO5,
191 W11_1610_MPUIO6,
192 V10_1610_MPUIO7,
193 W11_1610_MPUIO9,
194 V10_1610_MPUIO10,
195 W10_1610_MPUIO11,
196 E20_1610_MPUIO13,
197 U20_1610_MPUIO14,
198 E19_1610_MPUIO15,
199
200 /* MCBSP2 */
201 MCBSP2_CLKR,
202 MCBSP2_CLKX,
203 MCBSP2_DR,
204 MCBSP2_DX,
205 MCBSP2_FSR,
206 MCBSP2_FSX,
207
208 /* MCBSP3 */
209 MCBSP3_CLKX,
210
211 /* Misc ballouts */
212 BALLOUT_V8_ARMIO3,
213
214 /* OMAP-1610 MMC2 */
215 W8_1610_MMC2_DAT0,
216 V8_1610_MMC2_DAT1,
217 W15_1610_MMC2_DAT2,
218 R10_1610_MMC2_DAT3,
219 Y10_1610_MMC2_CLK,
220 Y8_1610_MMC2_CMD,
221 V9_1610_MMC2_CMDDIR,
222 V5_1610_MMC2_DATDIR0,
223 W19_1610_MMC2_DATDIR1,
224 R18_1610_MMC2_CLKIN,
225
226 /* OMAP-1610 External Trace Interface */
227 M19_1610_ETM_PSTAT0,
228 L15_1610_ETM_PSTAT1,
229 L18_1610_ETM_PSTAT2,
230 L19_1610_ETM_D0,
231 J19_1610_ETM_D6,
232 J18_1610_ETM_D7,
233
234 /* OMAP-1610 GPIO */
235 P20_1610_GPIO4,
236 V9_1610_GPIO7,
237 W8_1610_GPIO9,
238 N19_1610_GPIO13,
239 P10_1610_GPIO22,
240 V5_1610_GPIO24,
241 AA20_1610_GPIO_41,
242 W19_1610_GPIO48,
243 M7_1610_GPIO62,
244
245 /* OMAP-1610 uWire */
246 V19_1610_UWIRE_SCLK,
247 U18_1610_UWIRE_SDI,
248 W21_1610_UWIRE_SDO,
249 N14_1610_UWIRE_CS0,
250 P15_1610_UWIRE_CS0,
251 N15_1610_UWIRE_CS1,
252
253 /* OMAP-1610 Flash */
254 L3_1610_FLASH_CS2B_OE,
255 M8_1610_FLASH_CS2B_WE,
256
257 /* First MMC */
258 MMC_CMD,
259 MMC_DAT1,
260 MMC_DAT2,
261 MMC_DAT0,
262 MMC_CLK,
263 MMC_DAT3,
264
265 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
266 M15_1710_MMC_CLKI,
267 P19_1710_MMC_CMDDIR,
268 P20_1710_MMC_DATDIR0,
269
270 /* OMAP-1610 USB0 alternate pin configuration */
271 W9_USB0_TXEN,
272 AA9_USB0_VP,
273 Y5_USB0_RCV,
274 R9_USB0_VM,
275 V6_USB0_TXD,
276 W5_USB0_SE0,
277 V9_USB0_SPEED,
278 V9_USB0_SUSP,
279
280 /* USB2 */
281 W9_USB2_TXEN,
282 AA9_USB2_VP,
283 Y5_USB2_RCV,
284 R9_USB2_VM,
285 V6_USB2_TXD,
286 W5_USB2_SE0,
287
288 /* UART1 1610 */
289
290 R13_1610_UART1_TX,
291 V14_1610_UART1_RX,
292 R14_1610_UART1_CTS,
293 AA15_1610_UART1_RTS,
294
295 /* I2C OMAP-1610 */
296 I2C_SCL,
297 I2C_SDA,
298
299 /* Keypad */
300 F18_1610_KBC0,
301 D20_1610_KBC1,
302 D19_1610_KBC2,
303 E18_1610_KBC3,
304 C21_1610_KBC4,
305 G18_1610_KBR0,
306 F19_1610_KBR1,
307 H14_1610_KBR2,
308 E20_1610_KBR3,
309 E19_1610_KBR4,
310 N19_1610_KBR5,
311
312 /* Power management */
313 T20_1610_LOW_PWR,
314
315 /* MCLK Settings */
316 V5_1710_MCLK_ON,
317 V5_1710_MCLK_OFF,
318 R10_1610_MCLK_ON,
319 R10_1610_MCLK_OFF,
320
321 /* CompactFlash controller */
322 P11_1610_CF_CD2,
323 R11_1610_CF_IOIS16,
324 V10_1610_CF_IREQ,
325 W10_1610_CF_RESET,
326 W11_1610_CF_CD1,
327} reg_cfg_t;
328
329#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
330
331/*
332 * Table of various FUNC_MUX and PULL_DWN combinations for each device.
333 * See also reg_cfg_t above for the lookup table.
334 */
335static reg_cfg_set __initdata_or_module
336reg_cfg_table[] = {
337/*
338 * description mux mode mux pull pull pull pu_pd pu dbg
339 * reg offset mode reg bit ena reg
340 */
341MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
342MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
343
344/* UART2 (COM_UART_GATING), conflicts with USB2 */
345MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
346MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
347MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
348MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
349
350/* UART3 (GIGA_UART_GATING) */
351MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
352MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
353MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
354MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
355MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
356MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
357MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
358
359/* PWT & PWL, conflicts with UART3 */
360MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
361MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
362
363/* USB internal master generic */
364MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
365MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
366/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
367MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
368MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
369MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
370MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
371
372/* USB1 master */
373MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
374MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
375MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
376MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
377MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
378MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
379MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
380MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
381MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
382MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
383MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
384
385/* USB2 master */
386MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
387MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
388MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
389MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
390MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
391MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
392MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
393
394/* OMAP-1510 GPIO */
395MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
396MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
397MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
398
399/* OMAP1610 GPIO */
400MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
401MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
402
403/* OMAP-1710 GPIO */
404MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
405MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
406MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
407MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
408
409/* MPUIO */
410MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
411MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
412MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
413
414MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
415MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
416MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
417MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
418MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
419MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
420MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
421MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
422MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
423
424/* MCBSP2 */
425MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
426MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
427MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
428MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
429MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
430MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
431
432/* MCBSP3 NOTE: Mode must 1 for clock */
433MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
434
435/* Misc ballouts */
436MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
437
438/* OMAP-1610 MMC2 */
439MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
440MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
441MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
442MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
443MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
444MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
445MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
446MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
447MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
448MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
449
450/* OMAP-1610 External Trace Interface */
451MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
452MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
453MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
454MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
455MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
456MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
457
458/* OMAP-1610 GPIO */
459MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
460MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
461MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
462MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
463MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
464MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
465MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
466MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
467MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
468
469/* OMAP-1610 uWire */
470MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
471MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
472MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
473MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
474MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
475MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
476
477/* OMAP-1610 Flash */
478MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
479MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
480
481/* First MMC interface, same on 1510, 1610 and 1710 */
482MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
483MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
484MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
485MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
486MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
487MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
488MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
489MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
490MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
491
492/* OMAP-1610 USB0 alternate configuration */
493MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
494MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
495MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
496MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
497MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
498MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
499MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
500MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
501
502/* USB2 interface */
503MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
504MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
505MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
506MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
507MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
508MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
509
510
511/* UART1 */
512MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
513MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
514MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
515MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
516
517/* I2C interface */
518MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
519MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
520
521/* Keypad */
522MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
523MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
524MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
525MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
526MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
527MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
528MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
529MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
530MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
531MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
532MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
533
534/* Power management */
535MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
536
537/* MCLK Settings */
538MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
539MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
540MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
541MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
542
543/* CompactFlash controller, conflicts with MMC1 */
544MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
545MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
546MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
547MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
548MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
549};
550
551#endif /* __MUX_C__ */
552
553#ifdef CONFIG_OMAP_MUX
554/* setup pin muxing in Linux */
555extern int omap_cfg_reg(reg_cfg_t reg_cfg);
556#else
557/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
558static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
559#endif
560
561#endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
new file mode 100644
index 000000000000..f491a48ef2e1
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -0,0 +1,61 @@
1/* linux/include/asm-arm/arch-omap/omap1510.h
2 *
3 * Hardware definitions for TI OMAP1510 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP1510_H
29#define __ASM_ARCH_OMAP1510_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP1510_SRAM_BASE 0xD0000000
40#define OMAP1510_SRAM_SIZE (SZ_128K + SZ_64K)
41#define OMAP1510_SRAM_START 0x20000000
42
43#define OMAP1510_DSP_BASE 0xE0000000
44#define OMAP1510_DSP_SIZE 0x28000
45#define OMAP1510_DSP_START 0xE0000000
46
47#define OMAP1510_DSPREG_BASE 0xE1000000
48#define OMAP1510_DSPREG_SIZE SZ_128K
49#define OMAP1510_DSPREG_START 0xE1000000
50
51/*
52 * ----------------------------------------------------------------------------
53 * Memory used by power management
54 * ----------------------------------------------------------------------------
55 */
56
57#define OMAP1510_SRAM_IDLE_SUSPEND (OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200)
58#define OMAP1510_SRAM_API_SUSPEND (OMAP1510_SRAM_IDLE_SUSPEND + 0x100)
59
60#endif /* __ASM_ARCH_OMAP1510_H */
61
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
new file mode 100644
index 000000000000..88b1fe43ae9e
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -0,0 +1,187 @@
1/* linux/include/asm-arm/arch-omap/omap16xx.h
2 *
3 * Hardware definitions for TI OMAP1610/5912/1710 processors.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP16XX_H
29#define __ASM_ARCH_OMAP16XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP16XX_SRAM_BASE 0xD0000000
40#define OMAP1610_SRAM_SIZE (SZ_16K)
41#define OMAP5912_SRAM_SIZE 0x3E800
42#define OMAP16XX_SRAM_START 0x20000000
43
44#define OMAP16XX_DSP_BASE 0xE0000000
45#define OMAP16XX_DSP_SIZE 0x28000
46#define OMAP16XX_DSP_START 0xE0000000
47
48#define OMAP16XX_DSPREG_BASE 0xE1000000
49#define OMAP16XX_DSPREG_SIZE SZ_128K
50#define OMAP16XX_DSPREG_START 0xE1000000
51
52/*
53 * ----------------------------------------------------------------------------
54 * Memory used by power management
55 * ----------------------------------------------------------------------------
56 */
57
58#define OMAP1610_SRAM_IDLE_SUSPEND (OMAP16XX_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
59#define OMAP1610_SRAM_API_SUSPEND (OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
60#define OMAP5912_SRAM_IDLE_SUSPEND (OMAP16XX_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
61#define OMAP5912_SRAM_API_SUSPEND (OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
62
63/*
64 * ---------------------------------------------------------------------------
65 * Interrupts
66 * ---------------------------------------------------------------------------
67 */
68#define OMAP_IH2_0_BASE (0xfffe0000)
69#define OMAP_IH2_1_BASE (0xfffe0100)
70#define OMAP_IH2_2_BASE (0xfffe0200)
71#define OMAP_IH2_3_BASE (0xfffe0300)
72
73#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
74#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
75#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
76#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
77#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
78#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
79#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
80
81#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
82#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
83#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
84#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
85#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
86#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
87#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
88
89#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
90#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
91#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
92#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
93#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
94#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
95#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
96
97#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
98#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
99#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
100#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
101#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
102#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
103#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
104
105/*
106 * ----------------------------------------------------------------------------
107 * Clocks
108 * ----------------------------------------------------------------------------
109 */
110#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
111
112/*
113 * ----------------------------------------------------------------------------
114 * Pin configuration registers
115 * ----------------------------------------------------------------------------
116 */
117#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
118#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
119#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
120#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
121#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
122
123/*
124 * ----------------------------------------------------------------------------
125 * System control registers
126 * ----------------------------------------------------------------------------
127 */
128#define OMAP1610_RESET_CONTROL 0xfffe1140
129
130/*
131 * ---------------------------------------------------------------------------
132 * TIPB bus interface
133 * ---------------------------------------------------------------------------
134 */
135#define TIPB_SWITCH_BASE (0xfffbc800)
136#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
137
138/* UART3 Registers Maping through MPU bus */
139#define UART3_RHR (OMAP_UART3_BASE + 0)
140#define UART3_THR (OMAP_UART3_BASE + 0)
141#define UART3_DLL (OMAP_UART3_BASE + 0)
142#define UART3_IER (OMAP_UART3_BASE + 4)
143#define UART3_DLH (OMAP_UART3_BASE + 4)
144#define UART3_IIR (OMAP_UART3_BASE + 8)
145#define UART3_FCR (OMAP_UART3_BASE + 8)
146#define UART3_EFR (OMAP_UART3_BASE + 8)
147#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
148#define UART3_MCR (OMAP_UART3_BASE + 0x10)
149#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
150#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
151#define UART3_LSR (OMAP_UART3_BASE + 0x14)
152#define UART3_TCR (OMAP_UART3_BASE + 0x18)
153#define UART3_MSR (OMAP_UART3_BASE + 0x18)
154#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
155#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
156#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
157#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
158#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
159#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
160#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
161#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
162#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
163#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
164#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
165#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
166#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
167#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
168#define UART3_BLR (OMAP_UART3_BASE + 0x38)
169#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
170#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
171#define UART3_SCR (OMAP_UART3_BASE + 0x40)
172#define UART3_SSR (OMAP_UART3_BASE + 0x44)
173#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
174#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
175#define UART3_MVR (OMAP_UART3_BASE + 0x50)
176
177/*
178 * ----------------------------------------------------------------------------
179 * Pulse-Width Light
180 * ----------------------------------------------------------------------------
181 */
182#define OMAP16XX_PWL_BASE (0xfffb5800)
183#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
184#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
185
186#endif /* __ASM_ARCH_OMAP16XX_H */
187
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
new file mode 100644
index 000000000000..599ab00f5488
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap730.h
@@ -0,0 +1,106 @@
1/* linux/include/asm-arm/arch-omap/omap730.h
2 *
3 * Hardware definitions for TI OMAP730 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP730_H
29#define __ASM_ARCH_OMAP730_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP730_SRAM_BASE 0xD0000000
40#define OMAP730_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K)
41#define OMAP730_SRAM_START 0x20000000
42
43#define OMAP730_DSP_BASE 0xE0000000
44#define OMAP730_DSP_SIZE 0x50000
45#define OMAP730_DSP_START 0xE0000000
46
47#define OMAP730_DSPREG_BASE 0xE1000000
48#define OMAP730_DSPREG_SIZE SZ_128K
49#define OMAP730_DSPREG_START 0xE1000000
50
51/*
52 * ----------------------------------------------------------------------------
53 * OMAP730 specific configuration registers
54 * ----------------------------------------------------------------------------
55 */
56#define OMAP730_CONFIG_BASE 0xfffe1000
57#define OMAP730_IO_CONF_0 0xfffe1070
58#define OMAP730_IO_CONF_1 0xfffe1074
59#define OMAP730_IO_CONF_2 0xfffe1078
60#define OMAP730_IO_CONF_3 0xfffe107c
61#define OMAP730_IO_CONF_4 0xfffe1080
62#define OMAP730_IO_CONF_5 0xfffe1084
63#define OMAP730_IO_CONF_6 0xfffe1088
64#define OMAP730_IO_CONF_7 0xfffe108c
65#define OMAP730_IO_CONF_8 0xfffe1090
66#define OMAP730_IO_CONF_9 0xfffe1094
67#define OMAP730_IO_CONF_10 0xfffe1098
68#define OMAP730_IO_CONF_11 0xfffe109c
69#define OMAP730_IO_CONF_12 0xfffe10a0
70#define OMAP730_IO_CONF_13 0xfffe10a4
71
72#define OMAP730_MODE_1 0xfffe1010
73#define OMAP730_MODE_2 0xfffe1014
74
75/* CSMI specials: in terms of base + offset */
76#define OMAP730_MODE2_OFFSET 0x14
77
78/*
79 * ----------------------------------------------------------------------------
80 * OMAP730 traffic controller configuration registers
81 * ----------------------------------------------------------------------------
82 */
83#define OMAP730_FLASH_CFG_0 0xfffecc10
84#define OMAP730_FLASH_ACFG_0 0xfffecc50
85#define OMAP730_FLASH_CFG_1 0xfffecc14
86#define OMAP730_FLASH_ACFG_1 0xfffecc54
87
88/*
89 * ----------------------------------------------------------------------------
90 * OMAP730 DSP control registers
91 * ----------------------------------------------------------------------------
92 */
93#define OMAP730_ICR_BASE 0xfffbb800
94#define OMAP730_DSP_M_CTL 0xfffbb804
95#define OMAP730_DSP_MMU_BASE 0xfffed200
96
97/*
98 * ----------------------------------------------------------------------------
99 * OMAP730 PCC_UPLD configuration registers
100 * ----------------------------------------------------------------------------
101 */
102#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
103#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
104
105#endif /* __ASM_ARCH_OMAP730_H */
106
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
new file mode 100644
index 000000000000..face9ad41e97
--- /dev/null
+++ b/include/asm-arm/arch-omap/param.h
@@ -0,0 +1,8 @@
1/*
2 * linux/include/asm-arm/arch-omap/param.h
3 *
4 */
5
6#ifdef CONFIG_OMAP_32K_TIMER_HZ
7#define HZ CONFIG_OMAP_32K_TIMER_HZ
8#endif
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
new file mode 100644
index 000000000000..f209fc0953fb
--- /dev/null
+++ b/include/asm-arm/arch-omap/pm.h
@@ -0,0 +1,229 @@
1/*
2 * linux/include/asm/arch-omap/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08
45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Powermanagement bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES 0x00000fff
56#define PERIPHERAL_ENABLE 0x2
57
58#define SELF_REFRESH_MODE 0x0c000001
59#define IDLE_EMIFS_REQUEST 0xc
60#define MODEM_32K_EN 0x1
61#define PER_EN 0x1
62
63#define CPU_SUSPEND_SIZE 200
64#define ULPD_LOW_POWER_EN 0x0001
65
66#define DSP_IDLE_DELAY 10
67#define DSP_IDLE 0x0040
68#define DSP_RST 0x0004
69#define DSP_ENABLE 0x0002
70#define SUFFICIENT_DSP_RESET_TIME 1000
71#define DEFAULT_MPUI_CONFIG 0x05cf
72#define ENABLE_XORCLK 0x2
73#define DSP_CLOCK_ENABLE 0x2000
74#define DSP_IDLE_MODE 0x2
75#define TC_IDLE_REQUEST (0x0000000c)
76
77#define IRQ_LEVEL2 (1<<0)
78#define IRQ_KEYBOARD (1<<1)
79#define IRQ_UART2 (1<<15)
80
81#define PDE_BIT 0x08
82#define PWD_EN_BIT 0x04
83#define EN_PERCK_BIT 0x04
84
85#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
86#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
87#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
88#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
89#define OMAP1510_ULPD_LOW_POWER_REQ 0x0001
90
91#define OMAP1610_DEEP_SLEEP_REQUEST 0x17c7
92#define OMAP1610_BIG_SLEEP_REQUEST TBD
93#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
94#define OMAP1610_IDLE_CLOCK_DOMAINS 0x09c7
95#define OMAP1610_ULPD_LOW_POWER_REQ 0x3
96
97#ifndef OMAP1510_SRAM_IDLE_SUSPEND
98#define OMAP1510_SRAM_IDLE_SUSPEND 0
99#endif
100#ifndef OMAP1610_SRAM_IDLE_SUSPEND
101#define OMAP1610_SRAM_IDLE_SUSPEND 0
102#endif
103#ifndef OMAP5912_SRAM_IDLE_SUSPEND
104#define OMAP5912_SRAM_IDLE_SUSPEND 0
105#endif
106
107#ifndef OMAP1510_SRAM_API_SUSPEND
108#define OMAP1510_SRAM_API_SUSPEND 0
109#endif
110#ifndef OMAP1610_SRAM_API_SUSPEND
111#define OMAP1610_SRAM_API_SUSPEND 0
112#endif
113#ifndef OMAP5912_SRAM_API_SUSPEND
114#define OMAP5912_SRAM_API_SUSPEND 0
115#endif
116
117#if !defined(CONFIG_ARCH_OMAP1510) && \
118 !defined(CONFIG_ARCH_OMAP16XX)
119#error "Power management for this processor not implemented yet"
120#endif
121
122#ifndef __ASSEMBLER__
123extern void omap_pm_idle(void);
124extern void omap_pm_suspend(void);
125extern int omap1510_cpu_suspend(unsigned short, unsigned short);
126extern int omap1610_cpu_suspend(unsigned short, unsigned short);
127extern int omap1510_idle_loop_suspend(void);
128extern int omap1610_idle_loop_suspend(void);
129extern unsigned int omap1510_cpu_suspend_sz;
130extern unsigned int omap1510_idle_loop_suspend_sz;
131extern unsigned int omap1610_cpu_suspend_sz;
132extern unsigned int omap1610_idle_loop_suspend_sz;
133
134#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
135#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
136#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
137
138#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
139#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
140#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
141
142#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
143#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
144#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
145
146#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
147#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
148#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
149
150/*
151 * List of global OMAP registers to preserve.
152 * More ones like CP and general purpose register values are preserved
153 * with the stack pointer in sleep.S.
154 */
155
156enum arm_save_state {
157 ARM_SLEEP_SAVE_START = 0,
158 /*
159 * MPU control registers 32 bits
160 */
161 ARM_SLEEP_SAVE_ARM_CKCTL,
162 ARM_SLEEP_SAVE_ARM_IDLECT1,
163 ARM_SLEEP_SAVE_ARM_IDLECT2,
164 ARM_SLEEP_SAVE_ARM_EWUPCT,
165 ARM_SLEEP_SAVE_ARM_RSTCT1,
166 ARM_SLEEP_SAVE_ARM_RSTCT2,
167 ARM_SLEEP_SAVE_ARM_SYSST,
168 ARM_SLEEP_SAVE_SIZE
169};
170
171enum ulpd_save_state {
172 ULPD_SLEEP_SAVE_START = 0,
173 /*
174 * ULPD registers 16 bits
175 */
176 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
177 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
178 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
179 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
180 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
181 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
182 ULPD_SLEEP_SAVE_SIZE
183};
184
185enum mpui1510_save_state {
186 MPUI1510_SLEEP_SAVE_START = 0,
187 /*
188 * MPUI registers 32 bits
189 */
190 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
191 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
192 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
193 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
194 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
195 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
196 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
197 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
198#if defined(CONFIG_ARCH_OMAP1510)
199 MPUI1510_SLEEP_SAVE_SIZE
200#else
201 MPUI1510_SLEEP_SAVE_SIZE = 0
202#endif
203};
204
205enum mpui1610_save_state {
206 MPUI1610_SLEEP_SAVE_START = 0,
207 /*
208 * MPUI registers 32 bits
209 */
210 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
211 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
212 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
213 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
214 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
215 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
216 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
217 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
218 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
219 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
220 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
221#if defined(CONFIG_ARCH_OMAP16XX)
222 MPUI1610_SLEEP_SAVE_SIZE
223#else
224 MPUI1610_SLEEP_SAVE_SIZE = 0
225#endif
226};
227
228#endif /* ASSEMBLER */
229#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
new file mode 100644
index 000000000000..17a2c4825f07
--- /dev/null
+++ b/include/asm-arm/arch-omap/system.h
@@ -0,0 +1,20 @@
1/*
2 * Copied from linux/include/asm-arm/arch-sa1100/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7#include <linux/config.h>
8#include <asm/arch/hardware.h>
9
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
14
15static inline void arch_reset(char mode)
16{
17 omap_writew(1, ARM_RSTCT1);
18}
19
20#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
new file mode 100644
index 000000000000..8ded218cbea5
--- /dev/null
+++ b/include/asm-arm/arch-omap/tc.h
@@ -0,0 +1,108 @@
1/*
2 * linux/include/asm-arm/arch-omap/tc.h
3 *
4 * OMAP Traffic Controller
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __ASM_ARCH_TC_H
25#define __ASM_ARCH_TC_H
26
27#define TCMIF_BASE 0xfffecc00
28#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
29#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
30#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
31#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
32#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
33#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
34#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
35#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
36#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
37#define EMIFF_MRS (TCMIF_BASE + 0x24)
38#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
39#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
40#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
41#define TC_ENDIANISM (TCMIF_BASE + 0x34)
42#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
43#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
44#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
45#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
46#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
47#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
48#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
49
50/* external EMIFS chipselect regions */
51#define OMAP_CS0_PHYS 0x00000000
52#define OMAP_CS0_SIZE SZ_64M
53
54#define OMAP_CS1_PHYS 0x04000000
55#define OMAP_CS1_SIZE SZ_64M
56
57#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
58#define OMAP_CS1A_SIZE SZ_32M
59
60#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
61#define OMAP_CS1B_SIZE SZ_32M
62
63#define OMAP_CS2_PHYS 0x08000000
64#define OMAP_CS2_SIZE SZ_64M
65
66#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
67#define OMAP_CS2A_SIZE SZ_32M
68
69#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
70#define OMAP_CS2B_SIZE SZ_32M
71
72#define OMAP_CS3_PHYS 0x0c000000
73#define OMAP_CS3_SIZE SZ_64M
74
75#ifndef __ASSEMBLER__
76
77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG)
79
80#define OMAP_EMIFS_CONFIG_FR (1 << 4)
81#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
82#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
83#define OMAP_EMIFS_CONFIG_BM (1 << 1)
84#define OMAP_EMIFS_CONFIG_WP (1 << 0)
85
86#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n)))
87#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n)))
88
89/* Almost all documentation for chip and board memory maps assumes
90 * BM is clear. Most devel boards have a switch to control booting
91 * from NOR flash (using external chipselect 3) rather than mask ROM,
92 * which uses BM to interchange the physical CS0 and CS3 addresses.
93 */
94static inline u32 omap_cs0_phys(void)
95{
96 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
97 ? OMAP_CS3_PHYS : 0;
98}
99
100static inline u32 omap_cs3_phys(void)
101{
102 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
103 ? 0 : OMAP_CS3_PHYS;
104}
105
106#endif /* __ASSEMBLER__ */
107
108#endif /* __ASM_ARCH_TC_H */
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
new file mode 100644
index 000000000000..b61ddb491e83
--- /dev/null
+++ b/include/asm-arm/arch-omap/timex.h
@@ -0,0 +1,33 @@
1/*
2 * linux/include/asm-arm/arch-omap/timex.h
3 *
4 * Copyright (C) 2000 RidgeRun, Inc.
5 * Author: Greg Lonnon <glonnon@ridgerun.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H
30
31#define CLOCK_TICK_RATE (HZ * 100000UL)
32
33#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
new file mode 100644
index 000000000000..0f97bb2e8fce
--- /dev/null
+++ b/include/asm-arm/arch-omap/tps65010.h
@@ -0,0 +1,80 @@
1/* linux/include/asm-arm/arch-omap/tps65010.h
2 *
3 * Functions to access TPS65010 power management device.
4 *
5 * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_TPS65010_H
29#define __ASM_ARCH_TPS65010_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Macros used by exported functions
34 * ----------------------------------------------------------------------------
35 */
36
37#define LED1 1
38#define LED2 2
39#define OFF 0
40#define ON 1
41#define BLINK 2
42#define GPIO1 1
43#define GPIO2 2
44#define GPIO3 3
45#define GPIO4 4
46#define LOW 0
47#define HIGH 1
48
49/*
50 * ----------------------------------------------------------------------------
51 * Exported functions
52 * ----------------------------------------------------------------------------
53 */
54
55/* Draw from VBUS:
56 * 0 mA -- DON'T DRAW (might supply power instead)
57 * 100 mA -- usb unit load (slowest charge rate)
58 * 500 mA -- usb high power (fast battery charge)
59 */
60extern int tps65010_set_vbus_draw(unsigned mA);
61
62/* tps65010_set_gpio_out_value parameter:
63 * gpio: GPIO1, GPIO2, GPIO3 or GPIO4
64 * value: LOW or HIGH
65 */
66extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
67
68/* tps65010_set_led parameter:
69 * led: LED1 or LED2
70 * mode: ON, OFF or BLINK
71 */
72extern int tps65010_set_led(unsigned led, unsigned mode);
73
74/* tps65010_set_low_pwr parameter:
75 * mode: ON or OFF
76 */
77extern int tps65010_set_low_pwr(unsigned mode);
78
79#endif /* __ASM_ARCH_TPS65010_H */
80
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
new file mode 100644
index 000000000000..3e640aba8c20
--- /dev/null
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -0,0 +1,82 @@
1/*
2 * linux/include/asm-arm/arch-omap/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/config.h>
21#include <linux/types.h>
22#include <linux/serial_reg.h>
23#include <asm/arch/hardware.h>
24
25unsigned int system_rev;
26
27#define UART_OMAP_MDR1 0x08 /* mode definition register */
28#define OMAP_ID_730 0x355F
29#define ID_MASK 0x7fff
30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
32
33static void
34putstr(const char *s)
35{
36 volatile u8 * uart = 0;
37 int shift;
38
39#ifdef CONFIG_OMAP_LL_DEBUG_UART3
40 uart = (volatile u8 *)(OMAP_UART3_BASE);
41#elif CONFIG_OMAP_LL_DEBUG_UART2
42 uart = (volatile u8 *)(OMAP_UART2_BASE);
43#else
44 uart = (volatile u8 *)(OMAP_UART1_BASE);
45#endif
46
47 /* Determine which serial port to use */
48 do {
49 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
50 unsigned int omap_id = omap_get_id();
51
52 if (omap_id == OMAP_ID_730)
53 shift = 0;
54 else
55 shift = 2;
56
57 if (check_port(uart, shift))
58 break;
59 /* Silent boot if no serial ports are enabled. */
60 return;
61 } while (0);
62
63 /*
64 * Now, xmit each character
65 */
66 while (*s) {
67 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
68 barrier();
69 uart[UART_TX << shift] = *s;
70 if (*s++ == '\n') {
71 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
72 barrier();
73 uart[UART_TX << shift] = '\r';
74 }
75 }
76}
77
78/*
79 * nothing to do
80 */
81#define arch_decomp_setup()
82#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
new file mode 100644
index 000000000000..1438c6cef0ca
--- /dev/null
+++ b/include/asm-arm/arch-omap/usb.h
@@ -0,0 +1,108 @@
1// include/asm-arm/mach-omap/usb.h
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <asm/arch/board.h>
7
8/*-------------------------------------------------------------------------*/
9
10#define OTG_BASE 0xfffb0400
11#define UDC_BASE 0xfffb4000
12#define OMAP_OHCI_BASE 0xfffba000
13
14/*-------------------------------------------------------------------------*/
15
16/*
17 * OTG and transceiver registers, for OMAPs starting with ARM926
18 */
19#define OTG_REG32(offset) __REG32(OTG_BASE + (offset))
20#define OTG_REG16(offset) __REG16(OTG_BASE + (offset))
21
22#define OTG_REV_REG OTG_REG32(0x00)
23#define OTG_SYSCON_1_REG OTG_REG32(0x04)
24# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
25# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
26# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
27# define OTG_IDLE_EN (1 << 15)
28# define HST_IDLE_EN (1 << 14)
29# define DEV_IDLE_EN (1 << 13)
30# define OTG_RESET_DONE (1 << 2)
31#define OTG_SYSCON_2_REG OTG_REG32(0x08)
32# define OTG_EN (1 << 31)
33# define USBX_SYNCHRO (1 << 30)
34# define OTG_MST16 (1 << 29)
35# define SRP_GPDATA (1 << 28)
36# define SRP_GPDVBUS (1 << 27)
37# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
38# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
39# define B_ASE_BRST(w) (((w)>>16)&0x07)
40# define SRP_DPW (1 << 14)
41# define SRP_DATA (1 << 13)
42# define SRP_VBUS (1 << 12)
43# define OTG_PADEN (1 << 10)
44# define HMC_PADEN (1 << 9)
45# define UHOST_EN (1 << 8)
46# define HMC_TLLSPEED (1 << 7)
47# define HMC_TLLATTACH (1 << 6)
48# define OTG_HMC(w) (((w)>>0)&0x3f)
49#define OTG_CTRL_REG OTG_REG32(0x0c)
50# define OTG_ASESSVLD (1 << 20)
51# define OTG_BSESSEND (1 << 19)
52# define OTG_BSESSVLD (1 << 18)
53# define OTG_VBUSVLD (1 << 17)
54# define OTG_ID (1 << 16)
55# define OTG_DRIVER_SEL (1 << 15)
56# define OTG_A_SETB_HNPEN (1 << 12)
57# define OTG_A_BUSREQ (1 << 11)
58# define OTG_B_HNPEN (1 << 9)
59# define OTG_B_BUSREQ (1 << 8)
60# define OTG_BUSDROP (1 << 7)
61# define OTG_PULLDOWN (1 << 5)
62# define OTG_PULLUP (1 << 4)
63# define OTG_DRV_VBUS (1 << 3)
64# define OTG_PD_VBUS (1 << 2)
65# define OTG_PU_VBUS (1 << 1)
66# define OTG_PU_ID (1 << 0)
67#define OTG_IRQ_EN_REG OTG_REG16(0x10)
68# define DRIVER_SWITCH (1 << 15)
69# define A_VBUS_ERR (1 << 13)
70# define A_REQ_TMROUT (1 << 12)
71# define A_SRP_DETECT (1 << 11)
72# define B_HNP_FAIL (1 << 10)
73# define B_SRP_TMROUT (1 << 9)
74# define B_SRP_DONE (1 << 8)
75# define B_SRP_STARTED (1 << 7)
76# define OPRT_CHG (1 << 0)
77#define OTG_IRQ_SRC_REG OTG_REG16(0x14)
78 // same bits as in IRQ_EN
79#define OTG_OUTCTRL_REG OTG_REG16(0x18)
80# define OTGVPD (1 << 14)
81# define OTGVPU (1 << 13)
82# define OTGPUID (1 << 12)
83# define USB2VDR (1 << 10)
84# define USB2PDEN (1 << 9)
85# define USB2PUEN (1 << 8)
86# define USB1VDR (1 << 6)
87# define USB1PDEN (1 << 5)
88# define USB1PUEN (1 << 4)
89# define USB0VDR (1 << 2)
90# define USB0PDEN (1 << 1)
91# define USB0PUEN (1 << 0)
92#define OTG_TEST_REG OTG_REG16(0x20)
93#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc)
94
95/*-------------------------------------------------------------------------*/
96
97#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064)
98# define CONF_USB2_UNI_R (1 << 8)
99# define CONF_USB1_UNI_R (1 << 7)
100# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
101# define CONF_USB0_ISOLATE_R (1 << 3)
102# define CONF_USB_PWRDN_DM_R (1 << 2)
103# define CONF_USB_PWRDN_DP_R (1 << 1)
104
105
106
107
108#endif /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h
new file mode 100644
index 000000000000..c6a83581a2fc
--- /dev/null
+++ b/include/asm-arm/arch-omap/vmalloc.h
@@ -0,0 +1,33 @@
1/*
2 * linux/include/asm-arm/arch-omap/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Just any arbitrary offset to the start of the vmalloc VM area: the
23 * current 8MB value just means that there will be a 8MB "hole" after the
24 * physical memory until the kernel virtual memory starts. That means that
25 * any out-of-bounds memory accesses will hopefully be caught.
26 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
27 * area for the same reason. ;)
28 */
29#define VMALLOC_OFFSET (8*1024*1024)
30#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
31#define VMALLOC_VMADDR(x) ((unsigned long)(x))
32#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
33
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 16:00:08 -0500