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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-28 17:40:39 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-28 17:40:39 -0400
commitebdea46fecae40c4d7effcd33f40918a37a1df4b (patch)
treee4312bf7f1f3d184738963a0ec300aa9fdfd55c1 /include/asm-arm/arch-omap/irqs.h
parentfecf3404f4aba6d0edeba31eeb018cbb6326dff2 (diff)
parent250d375d1da45a5e08ab8baf5eaa7eb258afd82b (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits) [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms [ARM] 3855/1: Add generic time support [ARM] 3873/1: S3C24XX: Add irq_chip names [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23 [ARM] nommu: confirms the CR_V bit in nommu mode [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. [ARM] 3870/1: AT91: Start removing static memory mappings [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards [ARM] 3868/1: AT91 hardware header update [ARM] 3867/1: AT91 GPIO update [ARM] 3866/1: AT91 clock update [ARM] 3865/1: AT91RM9200 header updates [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series [ARM] kthread: switch arch/arm/kernel/apm.c [ARM] Off-by-one in arch/arm/common/icst* [ARM] 3864/1: Refactore sharpsl_pm [ARM] 3863/1: Add Locomo SPI Device [ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h ...
Diffstat (limited to 'include/asm-arm/arch-omap/irqs.h')
-rw-r--r--include/asm-arm/arch-omap/irqs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 2542495d8a43..c5bb05a69b81 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -237,6 +237,7 @@
237#define INT_24XX_SDMA_IRQ1 13 237#define INT_24XX_SDMA_IRQ1 13
238#define INT_24XX_SDMA_IRQ2 14 238#define INT_24XX_SDMA_IRQ2 14
239#define INT_24XX_SDMA_IRQ3 15 239#define INT_24XX_SDMA_IRQ3 15
240#define INT_24XX_CAM_IRQ 24
240#define INT_24XX_DSS_IRQ 25 241#define INT_24XX_DSS_IRQ 25
241#define INT_24XX_GPIO_BANK1 29 242#define INT_24XX_GPIO_BANK1 29
242#define INT_24XX_GPIO_BANK2 30 243#define INT_24XX_GPIO_BANK2 30
@@ -261,6 +262,7 @@
261#define INT_24XX_UART1_IRQ 72 262#define INT_24XX_UART1_IRQ 72
262#define INT_24XX_UART2_IRQ 73 263#define INT_24XX_UART2_IRQ 73
263#define INT_24XX_UART3_IRQ 74 264#define INT_24XX_UART3_IRQ 74
265#define INT_24XX_MMC_IRQ 83
264 266
265/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and 267/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
266 * 16 MPUIO lines */ 268 * 16 MPUIO lines */