diff options
author | Tony Lindgren <tony@atomide.com> | 2006-06-26 19:16:15 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2006-06-26 19:16:15 -0400 |
commit | 7ff879dbcd2083c95933a56bce65ae45ecab3f35 (patch) | |
tree | ba34240578d5d8cebf58ad9e5f23d22d3eed2d5a /include/asm-arm/arch-omap/dma.h | |
parent | 6dc3c8f20159530d5553d0f8decc9454916d7495 (diff) |
ARM: OMAP: Fix DMA channel irq handling for omap24xx
- DMA CSR register is cleared by reading on omap1, but on
omap2 it is cleard by writing to it.
- DMA TOUT interrupt does not exist on omap24xx, rename it
- Add SECURE and MISALIGNED errors by default for omap24xx
- Add defines for external DMA request lines
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/asm-arm/arch-omap/dma.h')
-rw-r--r-- | include/asm-arm/arch-omap/dma.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index e081400b658e..1b1b02307e77 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h | |||
@@ -185,8 +185,8 @@ | |||
185 | /* DMA channels for 24xx */ | 185 | /* DMA channels for 24xx */ |
186 | #define OMAP24XX_DMA_NO_DEVICE 0 | 186 | #define OMAP24XX_DMA_NO_DEVICE 0 |
187 | #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ | 187 | #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ |
188 | #define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */ | 188 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ |
189 | #define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */ | 189 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ |
190 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ | 190 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ |
191 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ | 191 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ |
192 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ | 192 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ |
@@ -197,7 +197,9 @@ | |||
197 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ | 197 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ |
198 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ | 198 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ |
199 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ | 199 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ |
200 | 200 | #define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ | |
201 | #define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ | ||
202 | #define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ | ||
201 | #define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ | 203 | #define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ |
202 | #define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ | 204 | #define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ |
203 | #define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ | 205 | #define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ |
@@ -244,6 +246,7 @@ | |||
244 | #define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ | 246 | #define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ |
245 | #define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ | 247 | #define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ |
246 | #define OMAP24XX_DMA_MS 63 /* SDMA_62 */ | 248 | #define OMAP24XX_DMA_MS 63 /* SDMA_62 */ |
249 | #define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | ||
247 | 250 | ||
248 | /*----------------------------------------------------------------------------*/ | 251 | /*----------------------------------------------------------------------------*/ |
249 | 252 | ||
@@ -274,7 +277,7 @@ | |||
274 | #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) | 277 | #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) |
275 | #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) | 278 | #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) |
276 | 279 | ||
277 | #define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */ | 280 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) |
278 | #define OMAP_DMA_DROP_IRQ (1 << 1) | 281 | #define OMAP_DMA_DROP_IRQ (1 << 1) |
279 | #define OMAP_DMA_HALF_IRQ (1 << 2) | 282 | #define OMAP_DMA_HALF_IRQ (1 << 2) |
280 | #define OMAP_DMA_FRAME_IRQ (1 << 3) | 283 | #define OMAP_DMA_FRAME_IRQ (1 << 3) |