diff options
| author | Juergen Beisert <j.beisert@pengutronix.de> | 2008-07-05 04:02:54 -0400 |
|---|---|---|
| committer | Robert Schwebel <r.schwebel@pengutronix.de> | 2008-07-05 04:02:54 -0400 |
| commit | 259bcaae9a2f28d7e3303b202b64a1fb0a9ab9e4 (patch) | |
| tree | 8e86bf18877c7e430bd1994489c91701f625e9a6 /include/asm-arm/arch-mxc/mxc.h | |
| parent | 9e8a30dce1bd38cf7b941c707da504d28a907f5c (diff) | |
MXC arch: Simplify architecture's irq sources
Simplify architecture's irq headers and sources, to share these files
between MXC3 and MXC2.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Diffstat (limited to 'include/asm-arm/arch-mxc/mxc.h')
| -rw-r--r-- | include/asm-arm/arch-mxc/mxc.h | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h index 1df4e2f24920..3e1c4ded18e2 100644 --- a/include/asm-arm/arch-mxc/mxc.h +++ b/include/asm-arm/arch-mxc/mxc.h | |||
| @@ -29,42 +29,4 @@ | |||
| 29 | # define cpu_is_mx31() (0) | 29 | # define cpu_is_mx31() (0) |
| 30 | #endif | 30 | #endif |
| 31 | 31 | ||
| 32 | /* | ||
| 33 | ***************************************** | ||
| 34 | * AVIC Registers * | ||
| 35 | ***************************************** | ||
| 36 | */ | ||
| 37 | #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) | ||
| 38 | #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ | ||
| 39 | #define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */ | ||
| 40 | #define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */ | ||
| 41 | #define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */ | ||
| 42 | #define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */ | ||
| 43 | #define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ | ||
| 44 | #define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ | ||
| 45 | #define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ | ||
| 46 | #define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ | ||
| 47 | #define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */ | ||
| 48 | #define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */ | ||
| 49 | #define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */ | ||
| 50 | #define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */ | ||
| 51 | #define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */ | ||
| 52 | #define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */ | ||
| 53 | #define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */ | ||
| 54 | #define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ | ||
| 55 | #define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ | ||
| 56 | #define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ | ||
| 57 | #define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */ | ||
| 58 | #define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */ | ||
| 59 | #define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */ | ||
| 60 | #define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */ | ||
| 61 | #define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */ | ||
| 62 | #define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */ | ||
| 63 | #define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */ | ||
| 64 | |||
| 65 | #define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20) | ||
| 66 | #define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24) | ||
| 67 | #define IIM_PROD_REV_SH 3 | ||
| 68 | #define IIM_PROD_REV_LEN 5 | ||
| 69 | |||
| 70 | #endif /* __ASM_ARCH_MXC_H__ */ | 32 | #endif /* __ASM_ARCH_MXC_H__ */ |