diff options
| author | Robert Schwebel <robert@schwebel.de> | 2008-03-28 05:59:08 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-03-31 14:46:48 -0400 |
| commit | f304fc422d9f159badb0edfa5921611a2fa371c7 (patch) | |
| tree | 1ee85d115cdcf7b80b7a6e811da02c526ea91278 /include/asm-arm/arch-mxc/board-mx31ads.h | |
| parent | 05dda977f2574c3341abef9b74c27d2b362e1e3a (diff) | |
[ARM] 4876/1: i.MXC family: Clean up
From: Juergen Beisert <j.beisert@pengutronix.de>
Clean up current header files from doxygen style comments. There are
probably more such comments left, but we start with these.
Things happend since last review:
- needless blank lines removed (note by Russell King)
- re-format comments (note by Ross Wille)
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Ross Wille <wille@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-mxc/board-mx31ads.h')
| -rw-r--r-- | include/asm-arm/arch-mxc/board-mx31ads.h | 124 |
1 files changed, 47 insertions, 77 deletions
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h index be29b83ad4ae..8590127760a8 100644 --- a/include/asm-arm/arch-mxc/board-mx31ads.h +++ b/include/asm-arm/arch-mxc/board-mx31ads.h | |||
| @@ -11,107 +11,77 @@ | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 13 | 13 | ||
| 14 | /*! | 14 | /* Base address of PBC controller */ |
| 15 | * @name PBC Controller parameters | ||
| 16 | */ | ||
| 17 | /*! @{ */ | ||
| 18 | /*! | ||
| 19 | * Base address of PBC controller | ||
| 20 | */ | ||
| 21 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) | 15 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) |
| 22 | /* Offsets for the PBC Controller register */ | 16 | /* Offsets for the PBC Controller register */ |
| 23 | /*! | 17 | |
| 24 | * PBC Board status register offset | 18 | /* PBC Board status register offset */ |
| 25 | */ | ||
| 26 | #define PBC_BSTAT 0x000002 | 19 | #define PBC_BSTAT 0x000002 |
| 27 | /*! | 20 | |
| 28 | * PBC Board control register 1 set address. | 21 | /* PBC Board control register 1 set address */ |
| 29 | */ | ||
| 30 | #define PBC_BCTRL1_SET 0x000004 | 22 | #define PBC_BCTRL1_SET 0x000004 |
| 31 | /*! | 23 | |
| 32 | * PBC Board control register 1 clear address. | 24 | /* PBC Board control register 1 clear address */ |
| 33 | */ | ||
| 34 | #define PBC_BCTRL1_CLEAR 0x000006 | 25 | #define PBC_BCTRL1_CLEAR 0x000006 |
| 35 | /*! | 26 | |
| 36 | * PBC Board control register 2 set address. | 27 | /* PBC Board control register 2 set address */ |
| 37 | */ | ||
| 38 | #define PBC_BCTRL2_SET 0x000008 | 28 | #define PBC_BCTRL2_SET 0x000008 |
| 39 | /*! | 29 | |
| 40 | * PBC Board control register 2 clear address. | 30 | /* PBC Board control register 2 clear address */ |
| 41 | */ | ||
| 42 | #define PBC_BCTRL2_CLEAR 0x00000A | 31 | #define PBC_BCTRL2_CLEAR 0x00000A |
| 43 | /*! | 32 | |
| 44 | * PBC Board control register 3 set address. | 33 | /* PBC Board control register 3 set address */ |
| 45 | */ | ||
| 46 | #define PBC_BCTRL3_SET 0x00000C | 34 | #define PBC_BCTRL3_SET 0x00000C |
| 47 | /*! | 35 | |
| 48 | * PBC Board control register 3 clear address. | 36 | /* PBC Board control register 3 clear address */ |
| 49 | */ | ||
| 50 | #define PBC_BCTRL3_CLEAR 0x00000E | 37 | #define PBC_BCTRL3_CLEAR 0x00000E |
| 51 | /*! | 38 | |
| 52 | * PBC Board control register 4 set address. | 39 | /* PBC Board control register 4 set address */ |
| 53 | */ | ||
| 54 | #define PBC_BCTRL4_SET 0x000010 | 40 | #define PBC_BCTRL4_SET 0x000010 |
| 55 | /*! | 41 | |
| 56 | * PBC Board control register 4 clear address. | 42 | /* PBC Board control register 4 clear address */ |
| 57 | */ | ||
| 58 | #define PBC_BCTRL4_CLEAR 0x000012 | 43 | #define PBC_BCTRL4_CLEAR 0x000012 |
| 59 | /*! | 44 | |
| 60 | * PBC Board status register 1. | 45 | /* PBC Board status register 1 */ |
| 61 | */ | ||
| 62 | #define PBC_BSTAT1 0x000014 | 46 | #define PBC_BSTAT1 0x000014 |
| 63 | /*! | 47 | |
| 64 | * PBC Board interrupt status register. | 48 | /* PBC Board interrupt status register */ |
| 65 | */ | ||
| 66 | #define PBC_INTSTATUS 0x000016 | 49 | #define PBC_INTSTATUS 0x000016 |
| 67 | /*! | 50 | |
| 68 | * PBC Board interrupt current status register. | 51 | /* PBC Board interrupt current status register */ |
| 69 | */ | ||
| 70 | #define PBC_INTCURR_STATUS 0x000018 | 52 | #define PBC_INTCURR_STATUS 0x000018 |
| 71 | /*! | 53 | |
| 72 | * PBC Interrupt mask register set address. | 54 | /* PBC Interrupt mask register set address */ |
| 73 | */ | ||
| 74 | #define PBC_INTMASK_SET 0x00001A | 55 | #define PBC_INTMASK_SET 0x00001A |
| 75 | /*! | 56 | |
| 76 | * PBC Interrupt mask register clear address. | 57 | /* PBC Interrupt mask register clear address */ |
| 77 | */ | ||
| 78 | #define PBC_INTMASK_CLEAR 0x00001C | 58 | #define PBC_INTMASK_CLEAR 0x00001C |
| 79 | 59 | ||
| 80 | /*! | 60 | /* External UART A */ |
| 81 | * External UART A. | ||
| 82 | */ | ||
| 83 | #define PBC_SC16C652_UARTA 0x010000 | 61 | #define PBC_SC16C652_UARTA 0x010000 |
| 84 | /*! | 62 | |
| 85 | * External UART B. | 63 | /* External UART B */ |
| 86 | */ | ||
| 87 | #define PBC_SC16C652_UARTB 0x010010 | 64 | #define PBC_SC16C652_UARTB 0x010010 |
| 88 | /*! | 65 | |
| 89 | * Ethernet Controller IO base address. | 66 | /* Ethernet Controller IO base address */ |
| 90 | */ | ||
| 91 | #define PBC_CS8900A_IOBASE 0x020000 | 67 | #define PBC_CS8900A_IOBASE 0x020000 |
| 92 | /*! | 68 | |
| 93 | * Ethernet Controller Memory base address. | 69 | /* Ethernet Controller Memory base address */ |
| 94 | */ | ||
| 95 | #define PBC_CS8900A_MEMBASE 0x021000 | 70 | #define PBC_CS8900A_MEMBASE 0x021000 |
| 96 | /*! | 71 | |
| 97 | * Ethernet Controller DMA base address. | 72 | /* Ethernet Controller DMA base address */ |
| 98 | */ | ||
| 99 | #define PBC_CS8900A_DMABASE 0x022000 | 73 | #define PBC_CS8900A_DMABASE 0x022000 |
| 100 | /*! | 74 | |
| 101 | * External chip select 0. | 75 | /* External chip select 0 */ |
| 102 | */ | ||
| 103 | #define PBC_XCS0 0x040000 | 76 | #define PBC_XCS0 0x040000 |
| 104 | /*! | 77 | |
| 105 | * LCD Display enable. | 78 | /* LCD Display enable */ |
| 106 | */ | ||
| 107 | #define PBC_LCD_EN_B 0x060000 | 79 | #define PBC_LCD_EN_B 0x060000 |
| 108 | /*! | 80 | |
| 109 | * Code test debug enable. | 81 | /* Code test debug enable */ |
| 110 | */ | ||
| 111 | #define PBC_CODE_B 0x070000 | 82 | #define PBC_CODE_B 0x070000 |
| 112 | /*! | 83 | |
| 113 | * PSRAM memory select. | 84 | /* PSRAM memory select */ |
| 114 | */ | ||
| 115 | #define PBC_PSRAM_B 0x5000000 | 85 | #define PBC_PSRAM_B 0x5000000 |
| 116 | 86 | ||
| 117 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) | 87 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) |
| @@ -139,4 +109,4 @@ | |||
| 139 | 109 | ||
| 140 | #define MXC_MAX_EXP_IO_LINES 16 | 110 | #define MXC_MAX_EXP_IO_LINES 16 |
| 141 | 111 | ||
| 142 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ | 112 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ |