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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-lh7a40x
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-lh7a40x')
-rw-r--r--include/asm-arm/arch-lh7a40x/constants.h88
-rw-r--r--include/asm-arm/arch-lh7a40x/debug-macro.S39
-rw-r--r--include/asm-arm/arch-lh7a40x/dma.h17
-rw-r--r--include/asm-arm/arch-lh7a40x/entry-macro.S67
-rw-r--r--include/asm-arm/arch-lh7a40x/hardware.h58
-rw-r--r--include/asm-arm/arch-lh7a40x/io.h21
-rw-r--r--include/asm-arm/arch-lh7a40x/irq.h11
-rw-r--r--include/asm-arm/arch-lh7a40x/irqs.h196
-rw-r--r--include/asm-arm/arch-lh7a40x/memory.h94
-rw-r--r--include/asm-arm/arch-lh7a40x/param.h9
-rw-r--r--include/asm-arm/arch-lh7a40x/registers.h193
-rw-r--r--include/asm-arm/arch-lh7a40x/system.h19
-rw-r--r--include/asm-arm/arch-lh7a40x/timex.h17
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h43
-rw-r--r--include/asm-arm/arch-lh7a40x/vmalloc.h21
15 files changed, 893 insertions, 0 deletions
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
new file mode 100644
index 000000000000..52c1cb9c39c6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -0,0 +1,88 @@
1/* include/asm-arm/arch-lh7a40x/constants.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ASM_ARCH_CONSTANTS_H
13#define __ASM_ARCH_CONSTANTS_H
14
15#include <linux/config.h>
16
17/* Addressing constants */
18
19 /* SoC CPU IO addressing */
20#define IO_PHYS (0x80000000)
21#define IO_VIRT (0xf8000000)
22#define IO_SIZE (0x0000B000)
23
24#ifdef CONFIG_MACH_KEV7A400
25# define CPLD_PHYS (0x20000000)
26# define CPLD_VIRT (0xf2000000)
27# define CPLD_SIZE PAGE_SIZE
28#endif
29
30#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
31
32# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */
33/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
34# define IOBARRIER_VIRT 0xf0000000
35# define IOBARRIER_SIZE PAGE_SIZE
36
37# define CF_PHYS 0x60200000
38# define CF_VIRT 0xf6020000
39# define CF_SIZE (8*1024)
40
41 /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */
42# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20))
43# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16))
44# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */
45# define CPLD00_VIRT CPLDX_VIRT (0x00)
46# define CPLD00_SIZE PAGE_SIZE
47# define CPLD02_PHYS CPLDX_PHYS (0x02)
48# define CPLD02_VIRT CPLDX_VIRT (0x02)
49# define CPLD02_SIZE PAGE_SIZE
50# define CPLD06_PHYS CPLDX_PHYS (0x06)
51# define CPLD06_VIRT CPLDX_VIRT (0x06)
52# define CPLD06_SIZE PAGE_SIZE
53# define CPLD08_PHYS CPLDX_PHYS (0x08)
54# define CPLD08_VIRT CPLDX_VIRT (0x08)
55# define CPLD08_SIZE PAGE_SIZE
56# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
57# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
58# define CPLD0C_SIZE PAGE_SIZE
59# define CPLD0E_PHYS CPLDX_PHYS (0x0e)
60# define CPLD0E_VIRT CPLDX_VIRT (0x0e)
61# define CPLD0E_SIZE PAGE_SIZE
62# define CPLD10_PHYS CPLDX_PHYS (0x10)
63# define CPLD10_VIRT CPLDX_VIRT (0x10)
64# define CPLD10_SIZE PAGE_SIZE
65# define CPLD12_PHYS CPLDX_PHYS (0x12)
66# define CPLD12_VIRT CPLDX_VIRT (0x12)
67# define CPLD12_SIZE PAGE_SIZE
68# define CPLD14_PHYS CPLDX_PHYS (0x14)
69# define CPLD14_VIRT CPLDX_VIRT (0x14)
70# define CPLD14_SIZE PAGE_SIZE
71# define CPLD16_PHYS CPLDX_PHYS (0x16)
72# define CPLD16_VIRT CPLDX_VIRT (0x16)
73# define CPLD16_SIZE PAGE_SIZE
74# define CPLD18_PHYS CPLDX_PHYS (0x18)
75# define CPLD18_VIRT CPLDX_VIRT (0x18)
76# define CPLD18_SIZE PAGE_SIZE
77# define CPLD1A_PHYS CPLDX_PHYS (0x1a)
78# define CPLD1A_VIRT CPLDX_VIRT (0x1a)
79# define CPLD1A_SIZE PAGE_SIZE
80#endif
81
82 /* Timing constants */
83
84#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
85#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
86#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
87
88#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/debug-macro.S b/include/asm-arm/arch-lh7a40x/debug-macro.S
new file mode 100644
index 000000000000..421dcd6a8506
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/debug-macro.S
@@ -0,0 +1,39 @@
1/* linux/include/asm-arm/arch-lh7a40x/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 @ It is not known if this will be appropriate for every 40x
15 @ board.
16
17 .macro addruart,rx
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 mov \rx, #0x00000700 @ offset from base
21 orreq \rx, \rx, #0x80000000 @ physical base
22 orrne \rx, \rx, #0xf8000000 @ virtual base
23 .endm
24
25 .macro senduart,rd,rx
26 strb \rd, [\rx] @ DATA
27 .endm
28
29 .macro busyuart,rd,rx @ spin while busy
301001: ldr \rd, [\rx, #0x10] @ STATUS
31 tst \rd, #1 << 3 @ BUSY (TX FIFO not empty)
32 bne 1001b @ yes, spin
33 .endm
34
35 .macro waituart,rd,rx @ wait for Tx FIFO room
361001: ldrb \rd, [\rx, #0x10] @ STATUS
37 tst \rd, #1 << 5 @ TXFF (TX FIFO full)
38 bne 1001b @ yes, spin
39 .endm
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
new file mode 100644
index 000000000000..5797f01e1844
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -0,0 +1,17 @@
1/* include/asm-arm/arch-lh7a40x/dma.h
2 *
3 * Copyright (C) 2003 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#define MAX_DMA_ADDRESS 0xffffffff
15#define MAX_DMA_CHANNELS 0 /* All DMA is internal to CPU */
16
17#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
new file mode 100644
index 000000000000..865f396aa63c
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -0,0 +1,67 @@
1/*
2 * include/asm-arm/arch-lh7a40x/entry-macro.S
3 *
4 * Low-level IRQ helper macros for LH7A40x platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
12# error "LH7A400 and LH7A404 are mutually exclusive"
13# endif
14
15# if defined (CONFIG_ARCH_LH7A400)
16 .macro disable_fiq
17 .endm
18
19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
20 mov \irqnr, #0
21 mov \base, #io_p2v(0x80000000) @ APB registers
22 ldr \irqstat, [\base, #0x500] @ PIC INTSR
23
241001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
25 bcs 1008f @ Bit set; irq found
26 add \irqnr, \irqnr, #1
27 bne 1001b @ Until no bits
28 b 1009f @ Nothing? Hmm.
291008: movs \irqstat, #1 @ Force !Z
301009:
31 .endm
32
33#elif defined(CONFIG_ARCH_LH7A404)
34
35 .macro disable_fiq
36 .endm
37
38 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
39 mov \irqnr, #0 @ VIC1 irq base
40 mov \base, #io_p2v(0x80000000) @ APB registers
41 add \base, \base, #0x8000
42 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
43 tst \tmp, #VA_VECTORED @ Direct vectored
44 bne 1002f
45 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
46 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
47 bne 1001f
48 add \base, \base, #(0xa000 - 0x8000)
49 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
50 tst \tmp, #VA_VECTORED @ Direct vectored
51 bne 1002f
52 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
53 mov \irqnr, #32 @ VIC2 irq base
54
551001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
56 bcs 1008f @ Bit set; irq found
57 add \irqnr, \irqnr, #1
58 bne 1001b @ Until no bits
59 b 1009f @ Nothing? Hmm.
601002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
611008: movs \irqstat, #1 @ Force !Z
62 str \tmp, [\base, #0x0030] @ Clear vector
631009:
64 .endm
65#endif
66
67
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
new file mode 100644
index 000000000000..aeb07c162e25
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -0,0 +1,58 @@
1/* include/asm-arm/arch-lh7a40x/hardware.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ]
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 */
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
17#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
18
19#ifdef __ASSEMBLY__
20
21# define __REG(x) io_p2v(x)
22# define __PREG(x) io_v2p(x)
23
24#else
25
26# if 0
27# define __REG(x) (*((volatile u32 *)io_p2v(x)))
28# else
29/*
30 * This __REG() version gives the same results as the one above, except
31 * that we are fooling gcc somehow so it generates far better and smaller
32 * assembly code for access to contigous registers. It's a shame that gcc
33 * doesn't guess this by itself.
34 */
35#include <asm/types.h>
36typedef struct { volatile u32 offset[4096]; } __regbase;
37# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
38# define __REG(x) __REGP(io_p2v(x))
39typedef struct { volatile u16 offset[4096]; } __regbase16;
40# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
41# define __REG16(x) __REGP16(io_p2v(x))
42typedef struct { volatile u8 offset[4096]; } __regbase8;
43# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
44# define __REG8(x) __REGP8(io_p2v(x))
45#endif
46
47/* Let's kick gcc's ass again... */
48# define __REG2(x,y) \
49 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
50 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
51
52# define __PREG(x) (io_v2p((u32)&(x)))
53
54#endif
55
56#include "registers.h"
57
58#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
new file mode 100644
index 000000000000..c13bdd9add92
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -0,0 +1,21 @@
1/* include/asm-arm/arch-lh7a40x/io.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16/* No ISA or PCI bus on this machine. */
17#define __io(a) ((void __iomem *)(a))
18#define __mem_pci(a) (a)
19#define __mem_isa(a) (a)
20
21#endif /* __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-lh7a40x/irq.h b/include/asm-arm/arch-lh7a40x/irq.h
new file mode 100644
index 000000000000..0f5f0b10f6ca
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/irq.h
@@ -0,0 +1,11 @@
1/* include/asm-arm/arch-lh7a40x/irq.h
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11void __init lh7a40x_init_board_irq (void);
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
new file mode 100644
index 000000000000..f91f3e59f3ab
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -0,0 +1,196 @@
1/* include/asm-arm/arch-lh7a40x/irqs.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12/* It is to be seen whether or not we can build a kernel for more than
13 * one board. For the time being, these macros assume that we cannot.
14 * Thus, it is OK to ifdef machine/board specific IRQ assignments.
15 */
16
17
18#ifndef __ASM_ARCH_IRQS_H
19#define __ASM_ARCH_IRQS_H
20
21#include <linux/config.h>
22
23#define FIQ_START 80
24
25#if defined (CONFIG_ARCH_LH7A400)
26
27 /* FIQs */
28
29# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */
30# define IRQ_BLINT 1 /* Battery Low */
31# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */
32# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */
33
34 /* IRQs */
35
36# define IRQ_CSINT 4 /* Audio Codec (ACI) */
37# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */
38# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */
39# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */
40# define IRQ_T1UI 8 /* Timer 1 underflow */
41# define IRQ_T2UI 9 /* Timer 2 underflow */
42# define IRQ_RTCMI 10
43# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */
44# define IRQ_UART1INTR 12
45# define IRQ_UART2INTR 13
46# define IRQ_LCDINTR 14
47# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */
48# define IRQ_UART3INTR 16
49# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */
50# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */
51# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */
52# define IRQ_USBINTR 20
53# define IRQ_DMAINTR 21
54# define IRQ_T3UI 22 /* Timer 3 underflow */
55# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */
56# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */
57# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */
58# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */
59# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */
60
61# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */
62
63 /* Given IRQ, return GPIO interrupt number 0-7 */
64# define IRQ_TO_GPIO(i) ((i) \
65 - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
66 - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
67
68#endif
69
70#if defined (CONFIG_ARCH_LH7A404)
71
72# define IRQ_BROWN 0 /* Brownout */
73# define IRQ_WDTINTR 1 /* Watchdog Timer */
74# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */
75# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */
76# define IRQ_T1UI 4 /* Timer 1 underflow */
77# define IRQ_T2UI 5 /* Timer 2 underflow */
78# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */
79# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */
80# define IRQ_DMAM2P1 8
81# define IRQ_DMAM2P2 9
82# define IRQ_DMAM2P3 10
83# define IRQ_DMAM2P4 11
84# define IRQ_DMAM2P5 12
85# define IRQ_DMAM2P6 13
86# define IRQ_DMAM2P7 14
87# define IRQ_DMAM2P8 15
88# define IRQ_DMAM2P9 16
89# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */
90# define IRQ_DMAM2M1 18
91# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */
92# define IRQ_GPIO1INTR 20
93# define IRQ_GPIO2INTR 21
94# define IRQ_GPIO3INTR 22
95# define IRQ_SOFT_V1_23 23 /* -- Unassigned */
96# define IRQ_SOFT_V1_24 24
97# define IRQ_SOFT_V1_25 25
98# define IRQ_SOFT_V1_26 26
99# define IRQ_SOFT_V1_27 27
100# define IRQ_SOFT_V1_28 28
101# define IRQ_SOFT_V1_29 29
102# define IRQ_SOFT_V1_30 30
103# define IRQ_SOFT_V1_31 31
104
105# define IRQ_BLINT 32 /* Battery Low */
106# define IRQ_BMIINTR 33 /* Battery Monitor */
107# define IRQ_MCINTR 34 /* Media Change */
108# define IRQ_TINTR 35 /* 64Hz Tick */
109# define IRQ_WEINT 36 /* Watchdog Expired */
110# define IRQ_RTCMI 37 /* Real-time Clock Match */
111# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */
112# define IRQ_UART1ERR 39 /* UART1 Error */
113# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */
114# define IRQ_UART2ERR 41 /* UART2 Error */
115# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */
116# define IRQ_UART3ERR 43 /* UART3 Error */
117# define IRQ_SCIINTR 44 /* Smart Card */
118# define IRQ_TSCINTR 45 /* Touchscreen */
119# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */
120# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */
121# define IRQ_GPIO5INTR 48
122# define IRQ_GPIO6INTR 49
123# define IRQ_GPIO7INTR 50
124# define IRQ_T3UI 51 /* Timer 3 underflow */
125# define IRQ_LCDINTR 52 /* LCD Controller */
126# define IRQ_SSPINTR 53 /* Synchronous Serial Port */
127# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */
128# define IRQ_USBINTR 55 /* USB Device Port */
129# define IRQ_USHINTR 56 /* USB Host Port */
130# define IRQ_SOFT_V2_25 57 /* -- Unassigned */
131# define IRQ_SOFT_V2_26 58
132# define IRQ_SOFT_V2_27 59
133# define IRQ_SOFT_V2_28 60
134# define IRQ_SOFT_V2_29 61
135# define IRQ_SOFT_V2_30 62
136# define IRQ_SOFT_V2_31 63
137
138# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */
139
140 /* Given IRQ, return GPIO interrupt number 0-7 */
141# define IRQ_TO_GPIO(i) ((i) \
142 - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
143 - IRQ_GPIO0INTR)
144
145 /* Vector Address constants */
146# define VA_VECTORED 0x100 /* Set for vectored interrupt */
147# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */
148# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */
149
150#endif
151
152 /* IRQ aliases */
153
154#if !defined (IRQ_GPIO0INTR)
155# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
156#endif
157#define IRQ_TICK IRQ_TINTR
158#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
159#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
160
161#ifdef CONFIG_MACH_KEV7A400
162# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
163# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */
164# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */
165# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */
166#endif
167
168#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
169# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */
170# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */
171#endif
172
173 /* System specific IRQs */
174
175#define IRQ_BOARD_START NR_IRQ_CPU
176
177#ifdef CONFIG_MACH_KEV7A400
178# define IRQ_KEV7A400_CPLD IRQ_BOARD_START
179# define NR_IRQ_BOARD 5
180# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */
181# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */
182# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */
183# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */
184# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4
185#endif
186
187#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
188# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START
189# define NR_IRQ_BOARD 2
190# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */
191# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
192#endif
193
194#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
195
196#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
new file mode 100644
index 000000000000..7e2fea372663
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -0,0 +1,94 @@
1/* include/asm-arm/arch-lh7a40x/memory.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 *
10 * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
11 *
12 */
13
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET (0xc0000000UL)
21
22/*
23 * Virtual view <-> DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29#define __virt_to_bus(x) __virt_to_phys(x)
30#define __bus_to_virt(x) __phys_to_virt(x)
31
32#ifdef CONFIG_DISCONTIGMEM
33
34#define NODES_SHIFT 4 /* Up to 16 nodes */
35
36/*
37 * Given a kernel address, find the home node of the underlying memory.
38 */
39
40# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
41# define KVADDR_TO_NID(addr) \
42 ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\
43 | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
44# else /* 2 banks per node */
45# define KVADDR_TO_NID(addr) \
46 (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
47# endif
48
49/*
50 * Given a page frame number, convert it to a node id.
51 */
52
53# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
54# define PFN_TO_NID(pfn) \
55 (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\
56 | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
57# else /* 2 banks per node */
58# define PFN_TO_NID(pfn) \
59 (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
60#endif
61
62/*
63 * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
64 * and return the mem_map of that node.
65 */
66# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
67
68/*
69 * Given a page frame number, find the owning node of the memory
70 * and return the mem_map of that node.
71 */
72# define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
73
74/*
75 * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
76 * and returns the index corresponding to the appropriate page in the
77 * node's mem_map.
78 */
79
80# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
81# define LOCAL_MAP_NR(addr) \
82 (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
83# else /* 2 banks per node */
84# define LOCAL_MAP_NR(addr) \
85 (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
86# endif
87
88#else
89
90# define PFN_TO_NID(addr) (0)
91
92#endif
93
94#endif
diff --git a/include/asm-arm/arch-lh7a40x/param.h b/include/asm-arm/arch-lh7a40x/param.h
new file mode 100644
index 000000000000..acad0bc5deba
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/param.h
@@ -0,0 +1,9 @@
1/* include/asm-arm/arch-lh7a40x/param.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
new file mode 100644
index 000000000000..2edb22e35450
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -0,0 +1,193 @@
1/* include/asm-arm/arch-lh7a40x/registers.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 * Copyright (C) 2004 Logic Product Development
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/config.h>
13#include <asm/arch/constants.h>
14
15#ifndef __ASM_ARCH_REGISTERS_H
16#define __ASM_ARCH_REGISTERS_H
17
18
19 /* Physical register base addresses */
20
21#define AC97_PHYS (0x80000000) /* AC97 Controller */
22#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
23#define USB_PHYS (0x80000200) /* USB Client */
24#define SCI_PHYS (0x80000300) /* Secure Card Interface */
25#define CSC_PHYS (0x80000400) /* Clock/State Controller */
26#define INTC_PHYS (0x80000500) /* Interrupt Controller */
27#define UART1_PHYS (0x80000600) /* UART1 Controller */
28#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
29#define UART2_PHYS (0x80000700) /* UART2 Controller */
30#define UART3_PHYS (0x80000800) /* UART3 Controller */
31#define DCDC_PHYS (0x80000900) /* DC to DC Controller */
32#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
33#define SSP_PHYS (0x80000b00) /* Synchronous ... */
34#define TIMER_PHYS (0x80000c00) /* Timer Controller */
35#define RTC_PHYS (0x80000d00) /* Real-time Clock */
36#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
37#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
38#define WDT_PHYS (0x80001400) /* Watchdog Timer */
39#define SMC_PHYS (0x80002000) /* Static Memory Controller */
40#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
41#define DMAC_PHYS (0x80002800) /* DMA Controller */
42#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
43
44 /* Physical registers of the LH7A404 */
45
46#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
47#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
48#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
49
50/*#define KBD_PHYS (0x80000e00) */
51/*#define LCDICP_PHYS (0x80001000) */
52
53
54 /* Clock/State Controller register */
55
56#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
57
58#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
59
60
61 /* Interrupt Controller registers */
62
63#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
64#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
65#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
66#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
67
68
69 /* Vectored Interrupted Controller registers */
70
71#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
72#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
73#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
74#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
75#define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
76#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
77#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
78#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
79#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
80#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
81#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
82#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
83#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
84#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
85#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
86#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
87#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
88#define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
89#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
90#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
91#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
92#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
93#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
94#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
95#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
96#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
97
98#define VIC_CNTL_ENABLE (0x20)
99
100 /* USB Host registers (Open HCI compatible) */
101
102#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
103
104
105 /* GPIO registers */
106
107#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
108#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
109#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
110#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
111#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
112
113
114 /* Static Memory Controller registers */
115
116#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
117#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
118#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
119#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
120#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
121#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
122
123
124#ifdef CONFIG_MACH_KEV7A400
125# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
126# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
127# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
128# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
129# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
130# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
131# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
132# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
133# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
134# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
135# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
136# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
137
138#endif
139
140#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
141# define CPLD_CONTROL __REG8(CPLD02_PHYS)
142# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
143# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
144# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
145# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
146# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
147# define CPLD_FLASH __REG8(CPLD10_PHYS)
148# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
149# define CPLD_REVISION __REG8(CPLD14_PHYS)
150# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
151# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
152# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
153#endif
154
155
156 /* Timer registers */
157
158#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
159#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
160#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
161#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
162
163#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
164#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
165#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
166#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
167
168#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
169
170#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
171#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
172#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
173#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
174
175#define TIMER_C_ENABLE (1<<7)
176#define TIMER_C_PERIODIC (1<<6)
177#define TIMER_C_FREERUNNING (0)
178#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
179#define TIMER_C_508KHZ (0x08)
180
181 /* GPIO registers */
182
183#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
184#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
185#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
186#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
187#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
188#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
189#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
190
191
192#endif /* _ASM_ARCH_REGISTERS_H */
193
diff --git a/include/asm-arm/arch-lh7a40x/system.h b/include/asm-arm/arch-lh7a40x/system.h
new file mode 100644
index 000000000000..e1df8aa460f2
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/system.h
@@ -0,0 +1,19 @@
1/* include/asm-arm/arch-lh7a40x/system.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle ();
14}
15
16static inline void arch_reset(char mode)
17{
18 cpu_reset (0);
19}
diff --git a/include/asm-arm/arch-lh7a40x/timex.h b/include/asm-arm/arch-lh7a40x/timex.h
new file mode 100644
index 000000000000..fa726b670829
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/timex.h
@@ -0,0 +1,17 @@
1/* include/asm-arm/arch-lh7a40x/timex.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <asm/arch/constants.h>
12
13#define CLOCK_TICK_RATE (PLL_CLOCK/6/16)
14
15/*
16#define CLOCK_TICK_RATE 3686400
17*/
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
new file mode 100644
index 000000000000..ec8ab67122f3
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -0,0 +1,43 @@
1/* include/asm-arm/arch-lh7a40x/uncompress.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <asm/arch/registers.h>
12
13#ifndef UART_R_DATA
14# define UART_R_DATA (0x00)
15#endif
16#ifndef UART_R_STATUS
17# define UART_R_STATUS (0x10)
18#endif
19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
20
21 /* Access UART with physical addresses before MMU is setup */
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
24
25static __inline__ void putc (char ch)
26{
27 while (UART_STATUS & nTxRdy)
28 ;
29 UART_DATA = ch;
30}
31
32static void putstr (const char* sz)
33{
34 for (; *sz; ++sz) {
35 putc (*sz);
36 if (*sz == '\n')
37 putc ('\r');
38 }
39}
40
41 /* NULL functions; we don't presently need them */
42#define arch_decomp_setup()
43#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h
new file mode 100644
index 000000000000..5ac607925bea
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/vmalloc.h
@@ -0,0 +1,21 @@
1/* include/asm-arm/arch-lh7a40x/vmalloc.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11/*
12 * Just any arbitrary offset to the start of the vmalloc VM area: the
13 * current 8MB value just means that there will be a 8MB "hole" after
14 * the physical memory until the kernel virtual memory starts. That
15 * means that any out-of-bounds memory accesses will hopefully be
16 * caught. The vmalloc() routines leaves a hole of 4kB (one page)
17 * between each vmalloced area for the same reason. ;)
18 */
19#define VMALLOC_OFFSET (8*1024*1024)
20#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
21#define VMALLOC_END (0xe8000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 01:05:47 -0500