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authorMarc Singer <elf@buici.com>2006-05-16 06:41:28 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-18 11:16:45 -0400
commit638b266630db8d492255d340e18d46ba6ab1b057 (patch)
tree305dbef19f1bbec6daaec98a52d38c15d47d3824 /include/asm-arm/arch-lh7a40x
parent2295196c30ea686389519f699f0ccbfbc5c3b94c (diff)
[ARM] 3401/1: lpd7a40x: platform update
Patch from Marc Singer Updates to the lpd7a40x_platform files. Includes support for new architecture, lpd7a400. Signed-off-by: Marc Singer <elf@buici.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-lh7a40x')
-rw-r--r--include/asm-arm/arch-lh7a40x/entry-macro.S70
1 files changed, 66 insertions, 4 deletions
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index a2f67c06d9c9..9fc7f4988124 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -10,11 +10,73 @@
10#include <asm/hardware.h> 10#include <asm/hardware.h>
11#include <asm/arch/irqs.h> 11#include <asm/arch/irqs.h>
12 12
13# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) 13/* In order to allow there to be support for both of the processor
14# error "LH7A400 and LH7A404 are mutually exclusive" 14 classes at the same time, we make a hack here that isn't very
15# endif 15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
16 18
17# if defined (CONFIG_ARCH_LH7A400) 19 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
21
22*/
23
24#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30
31branch_irq_lh7a400: b 1000f
32
33@ Implementation of the LH7A404 get_irqnr_and_base.
34
35 mov \irqnr, #0 @ VIC1 irq base
36 mov \base, #io_p2v(0x80000000) @ APB registers
37 add \base, \base, #0x8000
38 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
39 tst \tmp, #VA_VECTORED @ Direct vectored
40 bne 1002f
41 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
42 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
43 bne 1001f
44 add \base, \base, #(0xa000 - 0x8000)
45 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
46 tst \tmp, #VA_VECTORED @ Direct vectored
47 bne 1002f
48 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
49 mov \irqnr, #32 @ VIC2 irq base
50
511001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
52 bcs 1008f @ Bit set; irq found
53 add \irqnr, \irqnr, #1
54 bne 1001b @ Until no bits
55 b 1009f @ Nothing? Hmm.
561002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
571008: movs \irqstat, #1 @ Force !Z
58 str \tmp, [\base, #0x0030] @ Clear vector
59 b 1009f
60
61@ Implementation of the LH7A400 get_irqnr_and_base.
62
631000: mov \irqnr, #0
64 mov \base, #io_p2v(0x80000000) @ APB registers
65 ldr \irqstat, [\base, #0x500] @ PIC INTSR
66
671001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
68 bcs 1008f @ Bit set; irq found
69 add \irqnr, \irqnr, #1
70 bne 1001b @ Until no bits
71 b 1009f @ Nothing? Hmm.
721008: movs \irqstat, #1 @ Force !Z
73
741009:
75 .endm
76
77
78
79#elif defined (CONFIG_ARCH_LH7A400)
18 .macro disable_fiq 80 .macro disable_fiq
19 .endm 81 .endm
20 82