diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 11:14:15 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 04:55:48 -0400 |
commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
tree | 69689f467179891b498bd7423fcf61925173db31 /include/asm-arm/arch-ks8695 | |
parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ks8695')
25 files changed, 0 insertions, 1241 deletions
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S deleted file mode 100644 index d2583ffffa95..000000000000 --- a/include/asm-arm/arch-ks8695/debug-macro.S +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/debug-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Debug macros | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <asm/arch/hardware.h> | ||
15 | #include <asm/arch/regs-uart.h> | ||
16 | |||
17 | .macro addruart, rx | ||
18 | mrc p15, 0, \rx, c1, c0 | ||
19 | tst \rx, #1 @ MMU enabled? | ||
20 | ldreq \rx, =KS8695_UART_PA @ physical base address | ||
21 | ldrne \rx, =KS8695_UART_VA @ virtual base address | ||
22 | .endm | ||
23 | |||
24 | .macro senduart, rd, rx | ||
25 | str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register | ||
26 | .endm | ||
27 | |||
28 | .macro busyuart, rd, rx | ||
29 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
30 | tst \rd, #URLS_URTE @ Holding & Shift registers empty? | ||
31 | beq 1001b | ||
32 | .endm | ||
33 | |||
34 | .macro waituart, rd, rx | ||
35 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
36 | tst \rd, #URLS_URTHRE @ Holding Register empty? | ||
37 | beq 1001b | ||
38 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h deleted file mode 100644 index 7ad2c656e162..000000000000 --- a/include/asm-arm/arch-ks8695/devices.h +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/devices.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_DEVICES_H | ||
12 | #define __ASM_ARCH_DEVICES_H | ||
13 | |||
14 | #include <linux/pci.h> | ||
15 | |||
16 | /* Ethernet */ | ||
17 | extern void __init ks8695_add_device_wan(void); | ||
18 | extern void __init ks8695_add_device_lan(void); | ||
19 | extern void __init ks8695_add_device_hpna(void); | ||
20 | |||
21 | /* LEDs */ | ||
22 | extern short ks8695_leds_cpu; | ||
23 | extern short ks8695_leds_timer; | ||
24 | extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led); | ||
25 | |||
26 | /* PCI */ | ||
27 | #define KS8695_MODE_PCI 0 | ||
28 | #define KS8695_MODE_MINIPCI 1 | ||
29 | #define KS8695_MODE_CARDBUS 2 | ||
30 | |||
31 | struct ks8695_pci_cfg { | ||
32 | short mode; | ||
33 | int (*map_irq)(struct pci_dev *, u8, u8); | ||
34 | }; | ||
35 | extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); | ||
36 | |||
37 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h deleted file mode 100644 index e5159ed42a4b..000000000000 --- a/include/asm-arm/arch-ks8695/dma.h +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/dma.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S deleted file mode 100644 index 3993cfe67cfa..000000000000 --- a/include/asm-arm/arch-ks8695/entry-macro.S +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/entry-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * Low-level IRQ helper macros for KS8695 | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <asm/arch/hardware.h> | ||
15 | #include <asm/arch/regs-irq.h> | ||
16 | |||
17 | .macro disable_fiq | ||
18 | .endm | ||
19 | |||
20 | .macro get_irqnr_preamble, base, tmp | ||
21 | ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller | ||
22 | .endm | ||
23 | |||
24 | .macro arch_ret_to_user, tmp1, tmp2 | ||
25 | .endm | ||
26 | |||
27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
28 | ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register | ||
29 | |||
30 | teq \irqstat, #0 | ||
31 | beq 1001f | ||
32 | |||
33 | mov \irqnr, #0 | ||
34 | |||
35 | tst \irqstat, #0xff | ||
36 | moveq \irqstat, \irqstat, lsr #8 | ||
37 | addeq \irqnr, \irqnr, #8 | ||
38 | tsteq \irqstat, #0xff | ||
39 | moveq \irqstat, \irqstat, lsr #8 | ||
40 | addeq \irqnr, \irqnr, #8 | ||
41 | tsteq \irqstat, #0xff | ||
42 | moveq \irqstat, \irqstat, lsr #8 | ||
43 | addeq \irqnr, \irqnr, #8 | ||
44 | tst \irqstat, #0x0f | ||
45 | moveq \irqstat, \irqstat, lsr #4 | ||
46 | addeq \irqnr, \irqnr, #4 | ||
47 | tst \irqstat, #0x03 | ||
48 | moveq \irqstat, \irqstat, lsr #2 | ||
49 | addeq \irqnr, \irqnr, #2 | ||
50 | tst \irqstat, #0x01 | ||
51 | addeqs \irqnr, \irqnr, #1 | ||
52 | 1001: | ||
53 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h deleted file mode 100644 index 65ceea28607b..000000000000 --- a/include/asm-arm/arch-ks8695/gpio.h +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/gpio.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_GPIO_H_ | ||
12 | #define __ASM_ARCH_GPIO_H_ | ||
13 | |||
14 | #define KS8695_GPIO_0 0 | ||
15 | #define KS8695_GPIO_1 1 | ||
16 | #define KS8695_GPIO_2 2 | ||
17 | #define KS8695_GPIO_3 3 | ||
18 | #define KS8695_GPIO_4 4 | ||
19 | #define KS8695_GPIO_5 5 | ||
20 | #define KS8695_GPIO_6 6 | ||
21 | #define KS8695_GPIO_7 7 | ||
22 | #define KS8695_GPIO_8 8 | ||
23 | #define KS8695_GPIO_9 9 | ||
24 | #define KS8695_GPIO_10 10 | ||
25 | #define KS8695_GPIO_11 11 | ||
26 | #define KS8695_GPIO_12 12 | ||
27 | #define KS8695_GPIO_13 13 | ||
28 | #define KS8695_GPIO_14 14 | ||
29 | #define KS8695_GPIO_15 15 | ||
30 | |||
31 | |||
32 | /* | ||
33 | * Configure GPIO pin as external interrupt source. | ||
34 | */ | ||
35 | int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); | ||
36 | |||
37 | /* | ||
38 | * Configure the GPIO line as an input. | ||
39 | */ | ||
40 | int __init_or_module gpio_direction_input(unsigned int pin); | ||
41 | |||
42 | /* | ||
43 | * Configure the GPIO line as an output, with default state. | ||
44 | */ | ||
45 | int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); | ||
46 | |||
47 | /* | ||
48 | * Set the state of an output GPIO line. | ||
49 | */ | ||
50 | void gpio_set_value(unsigned int pin, unsigned int state); | ||
51 | |||
52 | /* | ||
53 | * Read the state of a GPIO line. | ||
54 | */ | ||
55 | int gpio_get_value(unsigned int pin); | ||
56 | |||
57 | /* | ||
58 | * Map GPIO line to IRQ number. | ||
59 | */ | ||
60 | int gpio_to_irq(unsigned int pin); | ||
61 | |||
62 | /* | ||
63 | * Map IRQ number to GPIO line. | ||
64 | */ | ||
65 | int irq_to_gpio(unsigned int irq); | ||
66 | |||
67 | |||
68 | #include <asm-generic/gpio.h> | ||
69 | |||
70 | static inline int gpio_request(unsigned int pin, const char *label) | ||
71 | { | ||
72 | return 0; | ||
73 | } | ||
74 | |||
75 | static inline void gpio_free(unsigned int pin) | ||
76 | { | ||
77 | } | ||
78 | |||
79 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h deleted file mode 100644 index cb732bff3288..000000000000 --- a/include/asm-arm/arch-ks8695/hardware.h +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/hardware.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Memory Map definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
15 | #define __ASM_ARCH_HARDWARE_H | ||
16 | |||
17 | #include <asm/sizes.h> | ||
18 | |||
19 | /* | ||
20 | * Physical RAM address. | ||
21 | */ | ||
22 | #define KS8695_SDRAM_PA 0x00000000 | ||
23 | |||
24 | |||
25 | /* | ||
26 | * We map an entire MiB with the System Configuration Registers in even | ||
27 | * though only 64KiB is needed. This makes it easier for use with the | ||
28 | * head debug code as the initial MMU setup only deals in L1 sections. | ||
29 | */ | ||
30 | #define KS8695_IO_PA 0x03F00000 | ||
31 | #define KS8695_IO_VA 0xF0000000 | ||
32 | #define KS8695_IO_SIZE SZ_1M | ||
33 | |||
34 | #define KS8695_PCIMEM_PA 0x60000000 | ||
35 | #define KS8695_PCIMEM_SIZE SZ_512M | ||
36 | |||
37 | #define KS8695_PCIIO_PA 0x80000000 | ||
38 | #define KS8695_PCIIO_SIZE SZ_64K | ||
39 | |||
40 | |||
41 | /* | ||
42 | * PCI support | ||
43 | */ | ||
44 | #define pcibios_assign_all_busses() 1 | ||
45 | |||
46 | #define PCIBIOS_MIN_IO 0 | ||
47 | #define PCIBIOS_MIN_MEM 0 | ||
48 | |||
49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h deleted file mode 100644 index 8edc4bd6aadf..000000000000 --- a/include/asm-arm/arch-ks8695/io.h +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/io.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | #define __io(a) ((void __iomem *)(a)) | ||
17 | #define __mem_pci(a) (a) | ||
18 | |||
19 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h deleted file mode 100644 index 8b1c4fe96a81..000000000000 --- a/include/asm-arm/arch-ks8695/irqs.h +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-ks8695/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_IRQS_H | ||
13 | #define __ASM_ARCH_IRQS_H | ||
14 | |||
15 | |||
16 | #define NR_IRQS 32 | ||
17 | |||
18 | /* | ||
19 | * IRQ definitions | ||
20 | */ | ||
21 | #define KS8695_IRQ_COMM_RX 0 | ||
22 | #define KS8695_IRQ_COMM_TX 1 | ||
23 | #define KS8695_IRQ_EXTERN0 2 | ||
24 | #define KS8695_IRQ_EXTERN1 3 | ||
25 | #define KS8695_IRQ_EXTERN2 4 | ||
26 | #define KS8695_IRQ_EXTERN3 5 | ||
27 | #define KS8695_IRQ_TIMER0 6 | ||
28 | #define KS8695_IRQ_TIMER1 7 | ||
29 | #define KS8695_IRQ_UART_TX 8 | ||
30 | #define KS8695_IRQ_UART_RX 9 | ||
31 | #define KS8695_IRQ_UART_LINE_STATUS 10 | ||
32 | #define KS8695_IRQ_UART_MODEM_STATUS 11 | ||
33 | #define KS8695_IRQ_LAN_RX_STOP 12 | ||
34 | #define KS8695_IRQ_LAN_TX_STOP 13 | ||
35 | #define KS8695_IRQ_LAN_RX_BUF 14 | ||
36 | #define KS8695_IRQ_LAN_TX_BUF 15 | ||
37 | #define KS8695_IRQ_LAN_RX_STATUS 16 | ||
38 | #define KS8695_IRQ_LAN_TX_STATUS 17 | ||
39 | #define KS8695_IRQ_HPNA_RX_STOP 18 | ||
40 | #define KS8695_IRQ_HPNA_TX_STOP 19 | ||
41 | #define KS8695_IRQ_HPNA_RX_BUF 20 | ||
42 | #define KS8695_IRQ_HPNA_TX_BUF 21 | ||
43 | #define KS8695_IRQ_HPNA_RX_STATUS 22 | ||
44 | #define KS8695_IRQ_HPNA_TX_STATUS 23 | ||
45 | #define KS8695_IRQ_BUS_ERROR 24 | ||
46 | #define KS8695_IRQ_WAN_RX_STOP 25 | ||
47 | #define KS8695_IRQ_WAN_TX_STOP 26 | ||
48 | #define KS8695_IRQ_WAN_RX_BUF 27 | ||
49 | #define KS8695_IRQ_WAN_TX_BUF 28 | ||
50 | #define KS8695_IRQ_WAN_RX_STATUS 29 | ||
51 | #define KS8695_IRQ_WAN_TX_STATUS 30 | ||
52 | #define KS8695_IRQ_WAN_LINK 31 | ||
53 | |||
54 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h deleted file mode 100644 index 1b542f77977a..000000000000 --- a/include/asm-arm/arch-ks8695/memory.h +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/memory.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 Memory definitions | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MEMORY_H | ||
14 | #define __ASM_ARCH_MEMORY_H | ||
15 | |||
16 | #include <asm/arch/hardware.h> | ||
17 | |||
18 | /* | ||
19 | * Physical SRAM offset. | ||
20 | */ | ||
21 | #define PHYS_OFFSET KS8695_SDRAM_PA | ||
22 | |||
23 | #ifndef __ASSEMBLY__ | ||
24 | |||
25 | #ifdef CONFIG_PCI | ||
26 | |||
27 | /* PCI mappings */ | ||
28 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) | ||
29 | #define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) | ||
30 | |||
31 | /* Platform-bus mapping */ | ||
32 | extern struct bus_type platform_bus_type; | ||
33 | #define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) | ||
34 | #define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ | ||
35 | __phys_to_virt(x) : __bus_to_virt(x); }) | ||
36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | ||
37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | ||
38 | #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) | ||
39 | |||
40 | #else | ||
41 | |||
42 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
43 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
44 | |||
45 | #endif | ||
46 | |||
47 | #endif | ||
48 | |||
49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h deleted file mode 100644 index 6b95d77aea19..000000000000 --- a/include/asm-arm/arch-ks8695/regs-gpio.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-gpio.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - GPIO control registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_GPIO_H | ||
14 | #define KS8695_GPIO_H | ||
15 | |||
16 | #define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) | ||
17 | #define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) | ||
18 | #define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) | ||
19 | |||
20 | |||
21 | #define KS8695_IOPM (0x00) /* I/O Port Mode Register */ | ||
22 | #define KS8695_IOPC (0x04) /* I/O Port Control Register */ | ||
23 | #define KS8695_IOPD (0x08) /* I/O Port Data Register */ | ||
24 | |||
25 | |||
26 | /* Port Mode Register */ | ||
27 | #define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ | ||
28 | |||
29 | /* Port Control Register */ | ||
30 | #define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ | ||
31 | #define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ | ||
32 | #define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ | ||
33 | #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ | ||
34 | #define IOPC_IOEINT3_MODE(x) ((x) << 12) | ||
35 | #define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ | ||
36 | #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ | ||
37 | #define IOPC_IOEINT2_MODE(x) ((x) << 8) | ||
38 | #define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ | ||
39 | #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ | ||
40 | #define IOPC_IOEINT1_MODE(x) ((x) << 4) | ||
41 | #define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ | ||
42 | #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ | ||
43 | #define IOPC_IOEINT0_MODE(x) ((x) << 0) | ||
44 | |||
45 | /* Trigger Modes */ | ||
46 | #define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ | ||
47 | #define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ | ||
48 | #define IOPC_TM_RISING (2) /* Rising Edge Detection */ | ||
49 | #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ | ||
50 | #define IOPC_TM_EDGE (6) /* Both Edge Detection */ | ||
51 | |||
52 | /* Port Data Register */ | ||
53 | #define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */ | ||
54 | |||
55 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h deleted file mode 100644 index 14091cdec103..000000000000 --- a/include/asm-arm/arch-ks8695/regs-hpna.h +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - HPNA Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_HPNA_H | ||
14 | #define KS8695_HPNA_H | ||
15 | |||
16 | #define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) | ||
17 | #define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) | ||
18 | #define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * HPNA registers | ||
23 | */ | ||
24 | |||
25 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h deleted file mode 100644 index 70b193f6b756..000000000000 --- a/include/asm-arm/arch-ks8695/regs-irq.h +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-irq.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - IRQ registers and bit definitions | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_IRQ_H | ||
15 | #define KS8695_IRQ_H | ||
16 | |||
17 | #define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) | ||
18 | #define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) | ||
19 | #define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * Interrupt Controller registers | ||
24 | */ | ||
25 | #define KS8695_INTMC (0x00) /* Mode Control Register */ | ||
26 | #define KS8695_INTEN (0x04) /* Interrupt Enable Register */ | ||
27 | #define KS8695_INTST (0x08) /* Interrupt Status Register */ | ||
28 | #define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ | ||
29 | #define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ | ||
30 | #define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ | ||
31 | #define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ | ||
32 | #define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ | ||
33 | #define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ | ||
34 | #define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ | ||
35 | #define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ | ||
36 | #define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ | ||
37 | #define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ | ||
38 | #define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ | ||
39 | |||
40 | |||
41 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h deleted file mode 100644 index a63bd61c64ed..000000000000 --- a/include/asm-arm/arch-ks8695/regs-lan.h +++ /dev/null | |||
@@ -1,65 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-lan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - LAN Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_LAN_H | ||
14 | #define KS8695_LAN_H | ||
15 | |||
16 | #define KS8695_LAN_OFFSET (0xF0000 + 0x8000) | ||
17 | #define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) | ||
18 | #define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * LAN registers | ||
23 | */ | ||
24 | #define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ | ||
25 | #define KS8695_LMDRXC (0x04) /* DMA Receive Control */ | ||
26 | #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ | ||
27 | #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ | ||
28 | #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
29 | #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
30 | #define KS8695_LMAL (0x18) /* MAC Station Address Low */ | ||
31 | #define KS8695_LMAH (0x1c) /* MAC Station Address High */ | ||
32 | #define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
33 | #define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
34 | |||
35 | |||
36 | /* DMA Transmit Control Register */ | ||
37 | #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ | ||
38 | #define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
39 | #define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
40 | #define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
41 | #define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
42 | #define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
43 | #define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ | ||
44 | #define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ | ||
45 | #define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ | ||
46 | #define LMDTXC_LMTE (1 << 0) /* TX Enable */ | ||
47 | |||
48 | /* DMA Receive Control Register */ | ||
49 | #define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ | ||
50 | #define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
51 | #define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
52 | #define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ | ||
53 | #define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
54 | #define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ | ||
55 | #define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ | ||
56 | #define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ | ||
57 | #define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ | ||
58 | #define LMDRXC_LMRA (1 << 2) /* Receive All */ | ||
59 | #define LMDRXC_LMRE (1 << 1) /* RX Enable */ | ||
60 | |||
61 | /* Additional Station Address High */ | ||
62 | #define LMAAH_E (1 << 31) /* Address Enabled */ | ||
63 | |||
64 | |||
65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h deleted file mode 100644 index 76b38e0862e6..000000000000 --- a/include/asm-arm/arch-ks8695/regs-mem.h +++ /dev/null | |||
@@ -1,89 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-mem.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Memory Controller registers and bit definitions | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_MEM_H | ||
14 | #define KS8695_MEM_H | ||
15 | |||
16 | #define KS8695_MEM_OFFSET (0xF0000 + 0x4000) | ||
17 | #define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) | ||
18 | #define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Memory Controller Registers | ||
23 | */ | ||
24 | #define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ | ||
25 | #define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ | ||
26 | #define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ | ||
27 | #define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ | ||
28 | #define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ | ||
29 | #define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ | ||
30 | #define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ | ||
31 | #define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ | ||
32 | #define KS8695_SDGCON (0x38) /* SDRAM General Control */ | ||
33 | #define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ | ||
34 | #define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ | ||
35 | |||
36 | |||
37 | /* External I/O Access Control Registers */ | ||
38 | #define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
39 | #define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ | ||
40 | #define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ | ||
41 | #define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ | ||
42 | #define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ | ||
43 | #define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ | ||
44 | |||
45 | /* ROM/SRAM/Flash Control Register */ | ||
46 | #define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ | ||
47 | #define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ | ||
48 | #define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ | ||
49 | #define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ | ||
50 | #define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ | ||
51 | #define PMC_NORMAL (0 << 0) | ||
52 | #define PMC_4WORD (1 << 0) | ||
53 | #define PMC_8WORD (2 << 0) | ||
54 | #define PMC_16WORD (3 << 0) | ||
55 | |||
56 | /* External I/O and ROM/SRAM/Flash General Register */ | ||
57 | #define ERGCON_TMULT (3 << 28) /* Time Multiplier */ | ||
58 | #define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ | ||
59 | #define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ | ||
60 | #define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ | ||
61 | #define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ | ||
62 | #define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ | ||
63 | |||
64 | /* SDRAM Control Register */ | ||
65 | #define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
66 | #define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ | ||
67 | #define SDCON_DBCAB (3 << 8) /* Column Address Bits */ | ||
68 | #define SDCON_DBBNUM (1 << 3) /* Number of Banks */ | ||
69 | #define SDCON_DBDBW (3 << 1) /* Data Bus Width */ | ||
70 | |||
71 | /* SDRAM General Control Register */ | ||
72 | #define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ | ||
73 | #define SDGCON_SDCAS (3 << 0) /* CAS latency */ | ||
74 | |||
75 | /* SDRAM Buffer Control Register */ | ||
76 | #define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ | ||
77 | #define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ | ||
78 | #define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ | ||
79 | #define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ | ||
80 | #define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ | ||
81 | #define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ | ||
82 | #define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ | ||
83 | #define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ | ||
84 | |||
85 | /* SDRAM Refresh Timer Register */ | ||
86 | #define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ | ||
87 | |||
88 | |||
89 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h deleted file mode 100644 index 632ca6601a94..000000000000 --- a/include/asm-arm/arch-ks8695/regs-misc.h +++ /dev/null | |||
@@ -1,97 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-misc.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Miscellaneous Registers | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_MISC_H | ||
14 | #define KS8695_MISC_H | ||
15 | |||
16 | #define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) | ||
17 | #define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) | ||
18 | #define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Miscellaneous registers | ||
23 | */ | ||
24 | #define KS8695_DID (0x00) /* Device ID */ | ||
25 | #define KS8695_RID (0x04) /* Revision ID */ | ||
26 | #define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ | ||
27 | #define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ | ||
28 | #define KS8695_WPPM (0x10) /* WAN PHY Power Management */ | ||
29 | #define KS8695_PPS (0x1c) /* PHY PowerSave */ | ||
30 | |||
31 | /* Device ID Register */ | ||
32 | #define DID_ID (0xffff << 0) /* Device ID */ | ||
33 | |||
34 | /* Revision ID Register */ | ||
35 | #define RID_SUBID (0xf << 4) /* Sub-Device ID */ | ||
36 | #define RID_REVISION (0xf << 0) /* Revision ID */ | ||
37 | |||
38 | /* HPNA Miscellaneous Control Register */ | ||
39 | #define HMC_HSS (1 << 1) /* Speed */ | ||
40 | #define HMC_HDS (1 << 0) /* Duplex */ | ||
41 | |||
42 | /* WAN Miscellaneous Control Register */ | ||
43 | #define WMC_WANC (1 << 30) /* Auto-negotiation complete */ | ||
44 | #define WMC_WANR (1 << 29) /* Auto-negotiation restart */ | ||
45 | #define WMC_WANAP (1 << 28) /* Advertise Pause */ | ||
46 | #define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ | ||
47 | #define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ | ||
48 | #define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ | ||
49 | #define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ | ||
50 | #define WMC_WLS (1 << 23) /* Link status */ | ||
51 | #define WMC_WDS (1 << 22) /* Duplex status */ | ||
52 | #define WMC_WSS (1 << 21) /* Speed status */ | ||
53 | #define WMC_WLPP (1 << 20) /* Link Partner Pause */ | ||
54 | #define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ | ||
55 | #define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ | ||
56 | #define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ | ||
57 | #define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ | ||
58 | #define WMC_WAND (1 << 15) /* Auto-negotiation disable */ | ||
59 | #define WMC_WANF100 (1 << 14) /* Force 100 */ | ||
60 | #define WMC_WANFF (1 << 13) /* Force FDX */ | ||
61 | #define WMC_WLED1S (7 << 4) /* LED1 Select */ | ||
62 | #define WLED1S_SPEED (0 << 4) | ||
63 | #define WLED1S_LINK (1 << 4) | ||
64 | #define WLED1S_DUPLEX (2 << 4) | ||
65 | #define WLED1S_COLLISION (3 << 4) | ||
66 | #define WLED1S_ACTIVITY (4 << 4) | ||
67 | #define WLED1S_FDX_COLLISION (5 << 4) | ||
68 | #define WLED1S_LINK_ACTIVITY (6 << 4) | ||
69 | #define WMC_WLED0S (7 << 0) /* LED0 Select */ | ||
70 | #define WLED0S_SPEED (0 << 0) | ||
71 | #define WLED0S_LINK (1 << 0) | ||
72 | #define WLED0S_DUPLEX (2 << 0) | ||
73 | #define WLED0S_COLLISION (3 << 0) | ||
74 | #define WLED0S_ACTIVITY (4 << 0) | ||
75 | #define WLED0S_FDX_COLLISION (5 << 0) | ||
76 | #define WLED0S_LINK_ACTIVITY (6 << 0) | ||
77 | |||
78 | /* WAN PHY Power Management Register */ | ||
79 | #define WPPM_WLPBK (1 << 14) /* Local Loopback */ | ||
80 | #define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ | ||
81 | #define WPPM_WPI (1 << 12) /* PHY isolate */ | ||
82 | #define WPPM_WFL (1 << 10) /* Force link */ | ||
83 | #define WPPM_MDIXS (1 << 9) /* MDIX Status */ | ||
84 | #define WPPM_FEF (1 << 8) /* Far End Fault */ | ||
85 | #define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ | ||
86 | #define WPPM_TXDIS (1 << 6) /* Disable transmitter */ | ||
87 | #define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ | ||
88 | #define WPPM_PD (1 << 4) /* Power Down */ | ||
89 | #define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ | ||
90 | #define WPPM_FMDX (1 << 2) /* Force MDIX */ | ||
91 | #define WPPM_LPBK (1 << 1) /* MAX Loopback */ | ||
92 | |||
93 | /* PHY Power Save Register */ | ||
94 | #define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ | ||
95 | |||
96 | |||
97 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h deleted file mode 100644 index 286d6d488df8..000000000000 --- a/include/asm-arm/arch-ks8695/regs-pci.h +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-pci.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - PCI bridge registers and bit definitions. | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #define KS8695_PCI_OFFSET (0xF0000 + 0x2000) | ||
15 | #define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) | ||
16 | #define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) | ||
17 | |||
18 | |||
19 | #define KS8695_CRCFID (0x000) /* Configuration: Identification */ | ||
20 | #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ | ||
21 | #define KS8695_CRCFRV (0x008) /* Configuration: Revision */ | ||
22 | #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ | ||
23 | #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ | ||
24 | #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ | ||
25 | #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ | ||
26 | #define KS8695_PBCA (0x100) /* Bridge Configuration Address */ | ||
27 | #define KS8695_PBCD (0x104) /* Bridge Configuration Data */ | ||
28 | #define KS8695_PBM (0x200) /* Bridge Mode */ | ||
29 | #define KS8695_PBCS (0x204) /* Bridge Control and Status */ | ||
30 | #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ | ||
31 | #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ | ||
32 | #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ | ||
33 | #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ | ||
34 | #define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ | ||
35 | #define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ | ||
36 | #define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ | ||
37 | #define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ | ||
38 | |||
39 | |||
40 | /* Configuration: Identification */ | ||
41 | |||
42 | /* Configuration: Command and Status */ | ||
43 | |||
44 | /* Configuration: Revision */ | ||
45 | |||
46 | |||
47 | |||
48 | #define CFRV_GUEST (1 << 23) | ||
49 | |||
50 | #define PBCA_TYPE1 (1) | ||
51 | #define PBCA_ENABLE (1 << 31) | ||
52 | |||
53 | |||
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h deleted file mode 100644 index 5f37be3f2f60..000000000000 --- a/include/asm-arm/arch-ks8695/regs-switch.h +++ /dev/null | |||
@@ -1,66 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-switch.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - Switch Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_SWITCH_H | ||
14 | #define KS8695_SWITCH_H | ||
15 | |||
16 | #define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) | ||
17 | #define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) | ||
18 | #define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * Switch registers | ||
23 | */ | ||
24 | #define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ | ||
25 | #define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ | ||
26 | #define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ | ||
27 | |||
28 | #define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ | ||
29 | |||
30 | #define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ | ||
31 | #define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ | ||
32 | #define KS8695_SEIAC (0x50) /* Indirect Access Control */ | ||
33 | #define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ | ||
34 | #define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ | ||
35 | #define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ | ||
36 | #define KS8695_SEAFC (0x60) /* Advance Feature Control */ | ||
37 | #define KS8695_SEDSCPH (0x64) /* TOS Priority High */ | ||
38 | #define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ | ||
39 | #define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ | ||
40 | #define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ | ||
41 | #define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ | ||
42 | #define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ | ||
43 | |||
44 | |||
45 | /* Switch Engine Control 0 */ | ||
46 | #define SEC0_LLED1S (7 << 25) /* LED1 Select */ | ||
47 | #define LLED1S_SPEED (0 << 25) | ||
48 | #define LLED1S_LINK (1 << 25) | ||
49 | #define LLED1S_DUPLEX (2 << 25) | ||
50 | #define LLED1S_COLLISION (3 << 25) | ||
51 | #define LLED1S_ACTIVITY (4 << 25) | ||
52 | #define LLED1S_FDX_COLLISION (5 << 25) | ||
53 | #define LLED1S_LINK_ACTIVITY (6 << 25) | ||
54 | #define SEC0_LLED0S (7 << 22) /* LED0 Select */ | ||
55 | #define LLED0S_SPEED (0 << 22) | ||
56 | #define LLED0S_LINK (1 << 22) | ||
57 | #define LLED0S_DUPLEX (2 << 22) | ||
58 | #define LLED0S_COLLISION (3 << 22) | ||
59 | #define LLED0S_ACTIVITY (4 << 22) | ||
60 | #define LLED0S_FDX_COLLISION (5 << 22) | ||
61 | #define LLED0S_LINK_ACTIVITY (6 << 22) | ||
62 | #define SEC0_ENABLE (1 << 0) /* Enable Switch */ | ||
63 | |||
64 | |||
65 | |||
66 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h deleted file mode 100644 index f3179815b8ee..000000000000 --- a/include/asm-arm/arch-ks8695/regs-sys.h +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-sys.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - System control registers and bit definitions | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_SYS_H | ||
15 | #define KS8695_SYS_H | ||
16 | |||
17 | #define KS8695_SYS_OFFSET (0xF0000 + 0x0000) | ||
18 | #define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) | ||
19 | #define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) | ||
20 | |||
21 | |||
22 | #define KS8695_SYSCFG (0x00) /* System Configuration Register */ | ||
23 | #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ | ||
24 | |||
25 | |||
26 | /* System Configuration Register */ | ||
27 | #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ | ||
28 | |||
29 | /* System Clock and Bus Control Register */ | ||
30 | #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ | ||
31 | #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ | ||
32 | |||
33 | |||
34 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h deleted file mode 100644 index 0a9f7f99ec52..000000000000 --- a/include/asm-arm/arch-ks8695/regs-timer.h +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-timer.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Timer registers and bit definitions. | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_TIMER_H | ||
15 | #define KS8695_TIMER_H | ||
16 | |||
17 | #define KS8695_TMR_OFFSET (0xF0000 + 0xE400) | ||
18 | #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) | ||
19 | #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * Timer registers | ||
24 | */ | ||
25 | #define KS8695_TMCON (0x00) /* Timer Control Register */ | ||
26 | #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ | ||
27 | #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ | ||
28 | #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ | ||
29 | #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ | ||
30 | |||
31 | |||
32 | /* Timer Control Register */ | ||
33 | #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ | ||
34 | #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ | ||
35 | |||
36 | /* Timer0 Timeout Counter Register */ | ||
37 | #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ | ||
38 | |||
39 | |||
40 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h deleted file mode 100644 index a27cb20502a3..000000000000 --- a/include/asm-arm/arch-ks8695/regs-uart.h +++ /dev/null | |||
@@ -1,92 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-ks8695/regs-uart.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - UART register and bit definitions. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef KS8695_UART_H | ||
15 | #define KS8695_UART_H | ||
16 | |||
17 | #define KS8695_UART_OFFSET (0xF0000 + 0xE000) | ||
18 | #define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) | ||
19 | #define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) | ||
20 | |||
21 | |||
22 | /* | ||
23 | * UART registers | ||
24 | */ | ||
25 | #define KS8695_URRB (0x00) /* Receive Buffer Register */ | ||
26 | #define KS8695_URTH (0x04) /* Transmit Holding Register */ | ||
27 | #define KS8695_URFC (0x08) /* FIFO Control Register */ | ||
28 | #define KS8695_URLC (0x0C) /* Line Control Register */ | ||
29 | #define KS8695_URMC (0x10) /* Modem Control Register */ | ||
30 | #define KS8695_URLS (0x14) /* Line Status Register */ | ||
31 | #define KS8695_URMS (0x18) /* Modem Status Register */ | ||
32 | #define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ | ||
33 | #define KS8695_USR (0x20) /* Status Register */ | ||
34 | |||
35 | |||
36 | /* FIFO Control Register */ | ||
37 | #define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ | ||
38 | #define URFC_URFRT_1 (0 << 6) | ||
39 | #define URFC_URFRT_4 (1 << 6) | ||
40 | #define URFC_URFRT_8 (2 << 6) | ||
41 | #define URFC_URFRT_14 (3 << 6) | ||
42 | #define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ | ||
43 | #define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ | ||
44 | #define URFC_URFE (1 << 0) /* FIFO Enable */ | ||
45 | |||
46 | /* Line Control Register */ | ||
47 | #define URLC_URSBC (1 << 6) /* Set Break Condition */ | ||
48 | #define URLC_PARITY (7 << 3) /* Parity */ | ||
49 | #define URPE_NONE (0 << 3) | ||
50 | #define URPE_ODD (1 << 3) | ||
51 | #define URPE_EVEN (3 << 3) | ||
52 | #define URPE_MARK (5 << 3) | ||
53 | #define URPE_SPACE (7 << 3) | ||
54 | #define URLC_URSB (1 << 2) /* Stop Bits */ | ||
55 | #define URLC_URCL (3 << 0) /* Character Length */ | ||
56 | #define URCL_5 (0 << 0) | ||
57 | #define URCL_6 (1 << 0) | ||
58 | #define URCL_7 (2 << 0) | ||
59 | #define URCL_8 (3 << 0) | ||
60 | |||
61 | /* Modem Control Register */ | ||
62 | #define URMC_URLB (1 << 4) /* Loop-back mode */ | ||
63 | #define URMC_UROUT2 (1 << 3) /* OUT2 signal */ | ||
64 | #define URMC_UROUT1 (1 << 2) /* OUT1 signal */ | ||
65 | #define URMC_URRTS (1 << 1) /* Request to Send */ | ||
66 | #define URMC_URDTR (1 << 0) /* Data Terminal Ready */ | ||
67 | |||
68 | /* Line Status Register */ | ||
69 | #define URLS_URRFE (1 << 7) /* Receive FIFO Error */ | ||
70 | #define URLS_URTE (1 << 6) /* Transmit Empty */ | ||
71 | #define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ | ||
72 | #define URLS_URBI (1 << 4) /* Break Interrupt */ | ||
73 | #define URLS_URFE (1 << 3) /* Framing Error */ | ||
74 | #define URLS_URPE (1 << 2) /* Parity Error */ | ||
75 | #define URLS_URROE (1 << 1) /* Receive Overrun Error */ | ||
76 | #define URLS_URDR (1 << 0) /* Receive Data Ready */ | ||
77 | |||
78 | /* Modem Status Register */ | ||
79 | #define URMS_URDCD (1 << 7) /* Data Carrier Detect */ | ||
80 | #define URMS_URRI (1 << 6) /* Ring Indicator */ | ||
81 | #define URMS_URDSR (1 << 5) /* Data Set Ready */ | ||
82 | #define URMS_URCTS (1 << 4) /* Clear to Send */ | ||
83 | #define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
84 | #define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
85 | #define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ | ||
86 | #define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ | ||
87 | |||
88 | /* Status Register */ | ||
89 | #define USR_UTI (1 << 0) /* Timeout Indication */ | ||
90 | |||
91 | |||
92 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h deleted file mode 100644 index 52e35b0d65e4..000000000000 --- a/include/asm-arm/arch-ks8695/regs-wan.h +++ /dev/null | |||
@@ -1,65 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - WAN Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_WAN_H | ||
14 | #define KS8695_WAN_H | ||
15 | |||
16 | #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) | ||
17 | #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) | ||
18 | #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * WAN registers | ||
23 | */ | ||
24 | #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ | ||
25 | #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ | ||
26 | #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ | ||
27 | #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ | ||
28 | #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
29 | #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
30 | #define KS8695_WMAL (0x18) /* MAC Station Address Low */ | ||
31 | #define KS8695_WMAH (0x1c) /* MAC Station Address High */ | ||
32 | #define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
33 | #define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
34 | |||
35 | |||
36 | /* DMA Transmit Control Register */ | ||
37 | #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ | ||
38 | #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
39 | #define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
40 | #define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
41 | #define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
42 | #define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
43 | #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ | ||
44 | #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ | ||
45 | #define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ | ||
46 | #define WMDTXC_WMTE (1 << 0) /* TX Enable */ | ||
47 | |||
48 | /* DMA Receive Control Register */ | ||
49 | #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ | ||
50 | #define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
51 | #define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
52 | #define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ | ||
53 | #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
54 | #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ | ||
55 | #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ | ||
56 | #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ | ||
57 | #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ | ||
58 | #define WMDRXC_WMRA (1 << 2) /* Receive All */ | ||
59 | #define WMDRXC_WMRE (1 << 0) /* RX Enable */ | ||
60 | |||
61 | /* Additional Station Address High */ | ||
62 | #define WMAAH_E (1 << 31) /* Address Enabled */ | ||
63 | |||
64 | |||
65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h deleted file mode 100644 index 3bc28106d937..000000000000 --- a/include/asm-arm/arch-ks8695/system.h +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-s3c2410/system.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 - System function defines and includes | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_SYSTEM_H | ||
15 | #define __ASM_ARCH_SYSTEM_H | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/arch/regs-timer.h> | ||
19 | |||
20 | static void arch_idle(void) | ||
21 | { | ||
22 | /* | ||
23 | * This should do all the clock switching | ||
24 | * and wait for interrupt tricks, | ||
25 | */ | ||
26 | cpu_do_idle(); | ||
27 | |||
28 | } | ||
29 | |||
30 | static void arch_reset(char mode) | ||
31 | { | ||
32 | unsigned int reg; | ||
33 | |||
34 | if (mode == 's') | ||
35 | cpu_reset(0); | ||
36 | |||
37 | /* disable timer0 */ | ||
38 | reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | ||
39 | __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
40 | |||
41 | /* enable watchdog mode */ | ||
42 | __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); | ||
43 | |||
44 | /* re-enable timer0 */ | ||
45 | __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
46 | } | ||
47 | |||
48 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h deleted file mode 100644 index 8320d528b903..000000000000 --- a/include/asm-arm/arch-ks8695/timex.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/timex.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 - Time Parameters | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_TIMEX_H | ||
15 | #define __ASM_ARCH_TIMEX_H | ||
16 | |||
17 | /* timers are derived from MCLK, which is 25MHz */ | ||
18 | #define CLOCK_TICK_RATE 25000000 | ||
19 | |||
20 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h deleted file mode 100644 index 733a50855b5d..000000000000 --- a/include/asm-arm/arch-ks8695/uncompress.h +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/uncompress.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
5 | * Copyright (C) 2006 Simtec Electronics | ||
6 | * | ||
7 | * KS8695 - Kernel uncompressor | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/arch/regs-uart.h> | ||
19 | |||
20 | static void putc(char c) | ||
21 | { | ||
22 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) | ||
23 | barrier(); | ||
24 | |||
25 | __raw_writel(c, KS8695_UART_PA + KS8695_URTH); | ||
26 | } | ||
27 | |||
28 | static inline void flush(void) | ||
29 | { | ||
30 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) | ||
31 | barrier(); | ||
32 | } | ||
33 | |||
34 | #define arch_decomp_setup() | ||
35 | #define arch_decomp_wdog() | ||
36 | |||
37 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h deleted file mode 100644 index d1d88e58117d..000000000000 --- a/include/asm-arm/arch-ks8695/vmalloc.h +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/vmalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Ben Dooks | ||
5 | * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk> | ||
6 | * | ||
7 | * KS8695 vmalloc definition | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_VMALLOC_H | ||
15 | #define __ASM_ARCH_VMALLOC_H | ||
16 | |||
17 | #define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) | ||
18 | |||
19 | #endif | ||