diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-08-08 14:38:42 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-08-08 14:38:42 -0400 |
| commit | 49b75b87ce2dfbd99e59a50c3681b154d07e3a22 (patch) | |
| tree | f14e1da19a13d87a512f9043c2f37fd75dd122b3 /include/asm-arm/arch-ks8695/regs-gpio.h | |
| parent | f1c7f79b6ab4f7ada002a0fae47f462ede6b6857 (diff) | |
| parent | 097d9eb537ff4d88b74c3fe67392e27c478ca3c5 (diff) | |
Merge branch 'for-linus-merged' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus-merged' of master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 5177/1: arm/mach-sa1100/Makefile: remove CONFIG_SA1100_USB
[ARM] 5166/1: magician: add MAINTAINERS entry
[ARM] fix pnx4008 build errors
[ARM] Fix SMP booting with non-zero PHYS_OFFSET
[ARM] 5185/1: Fix spi num_chipselect for lubbock
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[ARM] Add support for arch/arm/mach-*/include and arch/arm/plat-*/include
[ARM] Remove asm/hardware.h, use asm/arch/hardware.h instead
[ARM] Eliminate useless includes of asm/mach-types.h
[ARM] Fix circular include dependency with IRQ headers
avr32: Use <mach/foo.h> instead of <asm/arch/foo.h>
avr32: Introduce arch/avr32/mach-*/include/mach
avr32: Move include/asm-avr32 to arch/avr32/include/asm
[ARM] sa1100_wdt: use reset_status to remember watchdog reset status
[ARM] pxa: introduce reset_status and clear_reset_status for driver's usage
[ARM] pxa: introduce reset.h for reset specific header information
Diffstat (limited to 'include/asm-arm/arch-ks8695/regs-gpio.h')
| -rw-r--r-- | include/asm-arm/arch-ks8695/regs-gpio.h | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h deleted file mode 100644 index 6b95d77aea19..000000000000 --- a/include/asm-arm/arch-ks8695/regs-gpio.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - GPIO control registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_GPIO_H | ||
| 14 | #define KS8695_GPIO_H | ||
| 15 | |||
| 16 | #define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) | ||
| 17 | #define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) | ||
| 18 | #define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | #define KS8695_IOPM (0x00) /* I/O Port Mode Register */ | ||
| 22 | #define KS8695_IOPC (0x04) /* I/O Port Control Register */ | ||
| 23 | #define KS8695_IOPD (0x08) /* I/O Port Data Register */ | ||
| 24 | |||
| 25 | |||
| 26 | /* Port Mode Register */ | ||
| 27 | #define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ | ||
| 28 | |||
| 29 | /* Port Control Register */ | ||
| 30 | #define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ | ||
| 31 | #define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ | ||
| 32 | #define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ | ||
| 33 | #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ | ||
| 34 | #define IOPC_IOEINT3_MODE(x) ((x) << 12) | ||
| 35 | #define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ | ||
| 36 | #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ | ||
| 37 | #define IOPC_IOEINT2_MODE(x) ((x) << 8) | ||
| 38 | #define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ | ||
| 39 | #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ | ||
| 40 | #define IOPC_IOEINT1_MODE(x) ((x) << 4) | ||
| 41 | #define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ | ||
| 42 | #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ | ||
| 43 | #define IOPC_IOEINT0_MODE(x) ((x) << 0) | ||
| 44 | |||
| 45 | /* Trigger Modes */ | ||
| 46 | #define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ | ||
| 47 | #define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ | ||
| 48 | #define IOPC_TM_RISING (2) /* Rising Edge Detection */ | ||
| 49 | #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ | ||
| 50 | #define IOPC_TM_EDGE (6) /* Both Edge Detection */ | ||
| 51 | |||
| 52 | /* Port Data Register */ | ||
| 53 | #define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */ | ||
| 54 | |||
| 55 | #endif | ||