diff options
author | Deepak Saxena <dsaxena@plexity.net> | 2006-01-05 15:59:29 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-05 15:59:29 -0500 |
commit | 54e269ead6e672325866037b0617a72edd1396b9 (patch) | |
tree | 3076c2e0187657daed3054d511b62dc33a4c8f8b /include/asm-arm/arch-ixp4xx/nslu2.h | |
parent | 2b9ac7c15c0c5c9d6057b9e297dabaebd208ffe8 (diff) |
[ARM] 3226/1: IXP4xx runtime expansion bus window size configuration
Patch from Deepak Saxena
The expansion bus on the IXP46x NPU can be configured for either 32MiB or
16MiB windows and changing the configuration causes the base address for
each chip select for each region to change. Because of this, we cannot
hardcode the physical base as we currently do. This patch checks the
expansion bus configuration registers at runtime to determine the
appropriate window size. Note that this requires that the bootloader
already configured the device sizes appropriately, but I feel that is
valid assumption to make as the bootloader must configure and access
the flash window, the output display (LCD, LEDs, etc) window, and
other expansion bus devices.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ixp4xx/nslu2.h')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/nslu2.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h index b8b347a559c7..4281838873ef 100644 --- a/include/asm-arm/arch-ixp4xx/nslu2.h +++ b/include/asm-arm/arch-ixp4xx/nslu2.h | |||
@@ -18,9 +18,6 @@ | |||
18 | #error "Do not include this directly, instead #include <asm/hardware.h>" | 18 | #error "Do not include this directly, instead #include <asm/hardware.h>" |
19 | #endif | 19 | #endif |
20 | 20 | ||
21 | #define NSLU2_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS | ||
22 | #define NSLU2_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE | ||
23 | |||
24 | #define NSLU2_SDA_PIN 7 | 21 | #define NSLU2_SDA_PIN 7 |
25 | #define NSLU2_SCL_PIN 6 | 22 | #define NSLU2_SCL_PIN 6 |
26 | 23 | ||