diff options
author | Deepak Saxena <dsaxena@plexity.net> | 2006-01-05 15:59:29 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-05 15:59:29 -0500 |
commit | 54e269ead6e672325866037b0617a72edd1396b9 (patch) | |
tree | 3076c2e0187657daed3054d511b62dc33a4c8f8b /include/asm-arm/arch-ixp4xx/gtwx5715.h | |
parent | 2b9ac7c15c0c5c9d6057b9e297dabaebd208ffe8 (diff) |
[ARM] 3226/1: IXP4xx runtime expansion bus window size configuration
Patch from Deepak Saxena
The expansion bus on the IXP46x NPU can be configured for either 32MiB or
16MiB windows and changing the configuration causes the base address for
each chip select for each region to change. Because of this, we cannot
hardcode the physical base as we currently do. This patch checks the
expansion bus configuration registers at runtime to determine the
appropriate window size. Note that this requires that the bootloader
already configured the device sizes appropriately, but I feel that is
valid assumption to make as the bootloader must configure and access
the flash window, the output display (LCD, LEDs, etc) window, and
other expansion bus devices.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ixp4xx/gtwx5715.h')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/gtwx5715.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h index fc460af70627..c3069d67c00e 100644 --- a/include/asm-arm/arch-ixp4xx/gtwx5715.h +++ b/include/asm-arm/arch-ixp4xx/gtwx5715.h | |||
@@ -57,10 +57,6 @@ | |||
57 | #define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 | 57 | #define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 |
58 | #define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 | 58 | #define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 |
59 | 59 | ||
60 | |||
61 | #define GTWX5715_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS | ||
62 | #define GTWX5715_FLASH_SIZE (0x00800000) | ||
63 | |||
64 | /* PCI controller GPIO to IRQ pin mappings | 60 | /* PCI controller GPIO to IRQ pin mappings |
65 | 61 | ||
66 | INTA INTB | 62 | INTA INTB |