diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-04-01 18:07:39 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-04-01 18:07:39 -0500 |
commit | 23759dc6430428897a36c4d493f611eca55c9481 (patch) | |
tree | c62050927599b36ed223753c35fd737e3c0c6762 /include/asm-arm/arch-ixp23xx | |
parent | d3f4c571b6e596f9d39c596426269006a309d3b8 (diff) |
[ARM] 3439/2: xsc3: add I/O coherency support
Patch from Lennert Buytenhek
This patch adds support for the I/O coherent cache available on the
xsc3. The approach is to provide a simple API to determine whether the
chipset supports coherency by calling arch_is_coherent() and then
setting the appropriate system memory PTE and PMD bits. In addition,
we call this API on dma_alloc_coherent() and dma_map_single() calls.
A generic version exists that will compile out all the coherency-related
code that is not needed on the majority of ARM systems.
Note that we do not check for coherency in the dma_alloc_writecombine()
function as that still requires a special PTE setting. We also don't
touch dma_mmap_coherent() as that is a special ARM-only API that is by
definition only used on non-coherent system.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ixp23xx')
-rw-r--r-- | include/asm-arm/arch-ixp23xx/memory.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h index bebcf0aa0d72..6e19f46d54d1 100644 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ b/include/asm-arm/arch-ixp23xx/memory.h | |||
@@ -28,6 +28,7 @@ | |||
28 | * to an address that the kernel can use. | 28 | * to an address that the kernel can use. |
29 | */ | 29 | */ |
30 | #ifndef __ASSEMBLY__ | 30 | #ifndef __ASSEMBLY__ |
31 | #include <asm/mach-types.h> | ||
31 | 32 | ||
32 | #define __virt_to_bus(v) \ | 33 | #define __virt_to_bus(v) \ |
33 | ({ unsigned int ret; \ | 34 | ({ unsigned int ret; \ |
@@ -40,6 +41,22 @@ | |||
40 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ | 41 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ |
41 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) | 42 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) |
42 | 43 | ||
44 | /* | ||
45 | * Coherency support. Only supported on A2 CPUs or on A1 | ||
46 | * systems that have the cache coherency workaround. | ||
47 | */ | ||
48 | static inline int __ixp23xx_arch_is_coherent(void) | ||
49 | { | ||
50 | extern unsigned int processor_id; | ||
51 | |||
52 | if (((processor_id & 15) >= 2) || machine_is_roadrunner()) | ||
53 | return 1; | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | #define arch_is_coherent() __ixp23xx_arch_is_coherent() | ||
59 | |||
43 | #endif | 60 | #endif |
44 | 61 | ||
45 | 62 | ||