Merge master.kernel.org:/home/rmk/linux-2.6-arm

4 files changed, 89 insertions, 19 deletions

diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
index 31ae88674968..95128d9f5026 100644
--- a/include/asm-arm/arch-ixp2000/enp2611.h
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -21,8 +21,20 @@
 #ifndef __ENP2611_H
 #define __ENP2611_H
 
-#define ENP2611_GPIO_SCL        0x07
-#define ENP2611_GPIO_SDA        0x06
+#define ENP2611_CALEB_PHYS_BASE         0xc5000000
+#define ENP2611_CALEB_VIRT_BASE         0xfe000000
+#define ENP2611_CALEB_SIZE              0x00100000
+
+#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
+#define ENP2611_PM3386_0_SIZE           0x00100000
+
+#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
+#define ENP2611_PM3386_1_SIZE           0x00100000
+
+#define ENP2611_GPIO_SCL                7
+#define ENP2611_GPIO_SDA                6
 
 
 #endif
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index def089d693d2..fc5ac6aec4f2 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -59,14 +59,15 @@
 #define IXP2000_CAP_SIZE                0x00100000
 
 /*
- * Addresses for specific on-chip peripherals
+ * Addresses for specific on-chip peripherals.
  */
 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
 #define IXP2000_UART_PHYS_BASE          0xc0030000
 #define IXP2000_UART_VIRT_BASE          0xfef30000
 #define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_GPIO_VIRT_BASE          0Xfef10000
+#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define IXP2000_GPIO_VIRT_BASE          0xfef10000
 
 /*
  * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
@@ -252,7 +253,7 @@
 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 
 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
 
 /* These are from the IRQ register in the PCI ISR register */
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
index 4f489cc0dfa5..ddbbb34b5f95 100644
--- a/include/asm-arm/arch-ixp2000/system.h
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
          * RedBoot bank.
          */
         if (machine_is_ixdp2401()) {
-                *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                                                | IXDP2X01_CPLD_FLASH_INTERN);
-                *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
+                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                                                | IXDP2X01_CPLD_FLASH_INTERN));
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
         }
 
         /*
          * On IXDP2801 we need to write this magic sequence to the CPLD
          * to cause a complete reset of the CPU and all external devices
-         * and moves the flash bank register back to 0.
+         * and move the flash bank register back to 0.
          */
         if (machine_is_ixdp2801()) {
                 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
+
                 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                *IXDP2X01_CPLD_RESET_REG = reset_reg;
-                mb();
-                *IXDP2X01_CPLD_RESET_REG = 0x80000000;
+                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
+                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
         }
 
-        /*
-         * We do a reset all if we are PCI master. We could be a slave and we
-         * don't want to do anything funky on the PCI bus.
-         */
-        if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
-                *(IXP2000_RESET0) |= (RSTALL);
-        }
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
 }
diff --git a/include/asm-arm/arch-ixp2000/uengine.h b/include/asm-arm/arch-ixp2000/uengine.h
new file mode 100644
index 000000000000..b442d65c6593
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uengine.h
@@ -0,0 +1,62 @@
+/*
+ * Generic library functions for the microengines found on the Intel
+ * IXP2000 series of network processors.
+ *
+ * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Dedicated to Marija Kulikova.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as
+ * published by the Free Software Foundation; either version 2.1 of the
+ * License, or (at your option) any later version.
+ */
+
+#ifndef __IXP2000_UENGINE_H
+#define __IXP2000_UENGINE_H
+
+extern u32 ixp2000_uengine_mask;
+
+struct ixp2000_uengine_code
+{
+        u32     cpu_model_bitmask;
+        u8      cpu_min_revision;
+        u8      cpu_max_revision;
+
+        u32     uengine_parameters;
+
+        struct ixp2000_reg_value {
+                int     reg;
+                u32     value;
+        } *initial_reg_values;
+
+        int     num_insns;
+        u8      *insns;
+};
+
+u32 ixp2000_uengine_csr_read(int uengine, int offset);
+void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
+void ixp2000_uengine_reset(u32 uengine_mask);
+void ixp2000_uengine_set_mode(int uengine, u32 mode);
+void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
+void ixp2000_uengine_init_context(int uengine, int context, int pc);
+void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
+void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
+int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
+
+#define IXP2000_UENGINE_8_CONTEXTS              0x00000000
+#define IXP2000_UENGINE_4_CONTEXTS              0x80000000
+#define IXP2000_UENGINE_PRN_UPDATE_EVERY        0x40000000
+#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS    0x00000000
+#define IXP2000_UENGINE_NN_FROM_SELF            0x00100000
+#define IXP2000_UENGINE_NN_FROM_PREVIOUS        0x00000000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3       0x000c0000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2       0x00080000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1       0x00040000
+#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0       0x00000000
+#define IXP2000_UENGINE_LM_ADDR1_GLOBAL         0x00020000
+#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT    0x00000000
+#define IXP2000_UENGINE_LM_ADDR0_GLOBAL         0x00010000
+#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT    0x00000000
+
+
+#endif