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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-ixp2000
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-ixp2000')
-rw-r--r--include/asm-arm/arch-ixp2000/debug-macro.S40
-rw-r--r--include/asm-arm/arch-ixp2000/dma.h18
-rw-r--r--include/asm-arm/arch-ixp2000/enp2611.h28
-rw-r--r--include/asm-arm/arch-ixp2000/entry-macro.S53
-rw-r--r--include/asm-arm/arch-ixp2000/gpio.h55
-rw-r--r--include/asm-arm/arch-ixp2000/hardware.h44
-rw-r--r--include/asm-arm/arch-ixp2000/io.h150
-rw-r--r--include/asm-arm/arch-ixp2000/irq.h13
-rw-r--r--include/asm-arm/arch-ixp2000/irqs.h174
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x00.h93
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x01.h57
-rw-r--r--include/asm-arm/arch-ixp2000/ixp2000-regs.h377
-rw-r--r--include/asm-arm/arch-ixp2000/memory.h34
-rw-r--r--include/asm-arm/arch-ixp2000/param.h3
-rw-r--r--include/asm-arm/arch-ixp2000/platform.h166
-rw-r--r--include/asm-arm/arch-ixp2000/system.h54
-rw-r--r--include/asm-arm/arch-ixp2000/timex.h13
-rw-r--r--include/asm-arm/arch-ixp2000/uncompress.h52
-rw-r--r--include/asm-arm/arch-ixp2000/vmalloc.h23
19 files changed, 1447 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp2000/debug-macro.S b/include/asm-arm/arch-ixp2000/debug-macro.S
new file mode 100644
index 000000000000..5631e0889861
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/debug-macro.S
@@ -0,0 +1,40 @@
1/* linux/include/asm-arm/arch-ixp2000/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0xc0000000 @ Physical base
18 movne \rx, #0xfe000000 @ virtual base
19 orrne \rx, \rx, #0x00f00000
20 orr \rx, \rx, #0x00030000
21#ifdef __ARMEB__
22 orr \rx, \rx, #0x00000003
23#endif
24 .endm
25
26 .macro senduart,rd,rx
27 strb \rd, [\rx]
28 .endm
29
30 .macro busyuart,rd,rx
311002: ldrb \rd, [\rx, #0x14]
32 tst \rd, #0x20
33 beq 1002b
34 .endm
35
36 .macro waituart,rd,rx
37 nop
38 nop
39 nop
40 .endm
diff --git a/include/asm-arm/arch-ixp2000/dma.h b/include/asm-arm/arch-ixp2000/dma.h
new file mode 100644
index 000000000000..0fb3568a98dd
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/dma.h
@@ -0,0 +1,18 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/dma.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARCH_DMA_H
11#define __ASM_ARCH_DMA_H
12
13#define MAX_DMA_ADDRESS 0xffffffff
14
15/* No DMA */
16#define MAX_DMA_CHANNELS 0
17
18#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
new file mode 100644
index 000000000000..31ae88674968
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-ixp2000/enp2611.h
3 *
4 * Register and other defines for Radisys ENP-2611
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __ENP2611_H
22#define __ENP2611_H
23
24#define ENP2611_GPIO_SCL 0x07
25#define ENP2611_GPIO_SDA 0x06
26
27
28#endif
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
new file mode 100644
index 000000000000..e3a4e4121298
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/entry-macro.S
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-ixp2000/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP2000-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 .macro disable_fiq
12 .endm
13
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15
16 mov \irqnr, #0x0 @clear out irqnr as default
17 mov \base, #0xfe000000
18 orr \base, \base, #0x00e00000
19 orr \base, \base, #0x08
20 ldr \irqstat, [\base] @ get interrupts
21
22 cmp \irqstat, #0
23 beq 1001f
24
25 clz \irqnr, \irqstat
26 mov \base, #31
27 subs \irqnr, \base, \irqnr
28
29 /*
30 * We handle PCIA and PCIB here so we don't have an
31 * extra layer of code just to check these two bits.
32 */
33 cmp \irqnr, #IRQ_IXP2000_PCI
34 bne 1001f
35
36 mov \base, #0xfe000000
37 orr \base, \base, #0x00c00000
38 orr \base, \base, #0x00000100
39 orr \base, \base, #0x00000058
40 ldr \irqstat, [\base]
41
42 mov \tmp, #(1<<26)
43 tst \irqstat, \tmp
44 movne \irqnr, #IRQ_IXP2000_PCIA
45 bne 1001f
46
47 mov \tmp, #(1<<27)
48 tst \irqstat, \tmp
49 movne \irqnr, #IRQ_IXP2000_PCIB
50
511001:
52 .endm
53
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
new file mode 100644
index 000000000000..84634af5cc64
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/gpio.h
@@ -0,0 +1,55 @@
1/*
2 * include/asm-arm/arch-ixp2000/ixp2000-gpio.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software, you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * IXP2000 GPIO in/out, edge/level detection for IRQs:
13 * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
14 * or both Falling-edge and Rising-edge.
15 * This must be called *before* the corresponding IRQ is registerd.
16 * Use this instead of directly setting the GPIO registers.
17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
18 */
19#ifndef _ASM_ARCH_IXP2000_GPIO_H_
20#define _ASM_ARCH_IXP2000_GPIO_H_
21
22#ifndef __ASSEMBLY__
23#define GPIO_OUT 0x0
24#define GPIO_IN 0x80
25
26#define IXP2000_GPIO_LOW 0
27#define IXP2000_GPIO_HIGH 1
28
29#define GPIO_NO_EDGES 0
30#define GPIO_FALLING_EDGE 1
31#define GPIO_RISING_EDGE 2
32#define GPIO_BOTH_EDGES 3
33#define GPIO_LEVEL_LOW 4
34#define GPIO_LEVEL_HIGH 8
35
36extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
37extern void set_GPIO_IRQ_level(int gpio_nr, int level);
38extern void gpio_line_config(int line, int style);
39
40static inline int gpio_line_get(int line)
41{
42 return (((*IXP2000_GPIO_PLR) >> line) & 1);
43}
44
45static inline void gpio_line_set(int line, int value)
46{
47 if (value == IXP2000_GPIO_HIGH) {
48 ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
49 } else if (value == IXP2000_GPIO_LOW)
50 ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
51}
52
53#endif /* !__ASSEMBLY__ */
54#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
55
diff --git a/include/asm-arm/arch-ixp2000/hardware.h b/include/asm-arm/arch-ixp2000/hardware.h
new file mode 100644
index 000000000000..e7ea781c48aa
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/hardware.h
@@ -0,0 +1,44 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/hardware.h
3 *
4 * Hardware definitions for IXP2400/2800 based systems
5 *
6 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@mvista.com>
9 *
10 * Copyright (C) 2001-2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H__
20#define __ASM_ARCH_HARDWARE_H__
21
22/*
23 * This needs to be platform-specific?
24 */
25#define PCIBIOS_MIN_IO 0x00000000
26#define PCIBIOS_MIN_MEM 0x00000000
27
28#include "ixp2000-regs.h" /* Chipset Registers */
29
30#define pcibios_assign_all_busses() 0
31
32/*
33 * Platform helper functions
34 */
35#include "platform.h"
36
37/*
38 * Platform-specific bits
39 */
40#include "enp2611.h" /* ENP-2611 */
41#include "ixdp2x00.h" /* IXDP2400/2800 */
42#include "ixdp2x01.h" /* IXDP2401/2801 */
43
44#endif /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
new file mode 100644
index 000000000000..a8e3c2daefd6
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -0,0 +1,150 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19#define __mem_pci(a) (a)
20#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
21
22/*
23 * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
24 * transactions the other way round (MEM transactions don't have this
25 * issue), so we need to override the standard functions. B0 and later
26 * have a bit that can be set to 1 to get the 'proper' behavior, but
27 * since that isn't available on the A? revisions we just keep doing
28 * things manually.
29 */
30#define alignb(addr) (void __iomem *)((unsigned long)addr ^ 3)
31#define alignw(addr) (void __iomem *)((unsigned long)addr ^ 2)
32
33#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
34#define outw(v,p) __raw_writew((v),alignw(___io(p)))
35#define outl(v,p) __raw_writel((v),___io(p))
36
37#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
38#define inw(p) \
39 ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
40#define inl(p) \
41 ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
42
43#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
44#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
45#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
46
47#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
48#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
49#define insl(p,d,l) __raw_readsl(___io(p),d,l)
50
51
52#ifdef CONFIG_ARCH_IXDP2X01
53/*
54 * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
55 * of "I/O space" and is just direct mapped into a 32-bit-only addressable
56 * bus. The address space for this bus is such that we can't really easily
57 * make it contiguous to the PCI I/O address range, and it also does not
58 * need swapping like PCI addresses do (IXDP2x01 is a BE platform).
59 * B/C of this we can't use the standard in/out functions and need to
60 * runtime check if the incoming address is a PCI address or for
61 * the CS89x0.
62 */
63#undef inw
64#undef outw
65#undef insw
66#undef outsw
67
68#include <asm/mach-types.h>
69
70static inline void insw(u32 ptr, void *buf, int length)
71{
72 register volatile u32 *port = (volatile u32 *)ptr;
73
74 /*
75 * Is this cycle meant for the CS8900?
76 */
77 if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
78 ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
79 (port <= IXDP2X01_CS8900_VIRT_END))) {
80 u8 *buf8 = (u8*)buf;
81 register u32 tmp32;
82
83 do {
84 tmp32 = *port;
85 *buf8++ = (u8)tmp32;
86 *buf8++ = (u8)(tmp32 >> 8);
87 } while(--length);
88
89 return;
90 }
91
92 __raw_readsw(alignw(___io(ptr)),buf,length);
93}
94
95static inline void outsw(u32 ptr, void *buf, int length)
96{
97 register volatile u32 *port = (volatile u32 *)ptr;
98
99 /*
100 * Is this cycle meant for the CS8900?
101 */
102 if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
103 ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
104 (port <= IXDP2X01_CS8900_VIRT_END))) {
105 register u32 tmp32;
106 u8 *buf8 = (u8*)buf;
107 do {
108 tmp32 = *buf8++;
109 tmp32 |= (*buf8++) << 8;
110 *port = tmp32;
111 } while(--length);
112 return;
113 }
114
115 __raw_writesw(alignw(___io(ptr)),buf,length);
116}
117
118
119static inline u16 inw(u32 ptr)
120{
121 register volatile u32 *port = (volatile u32 *)ptr;
122
123 /*
124 * Is this cycle meant for the CS8900?
125 */
126 if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
127 ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
128 (port <= IXDP2X01_CS8900_VIRT_END))) {
129 return (u16)(*port);
130 }
131
132 return __raw_readw(alignw(___io(ptr)));
133}
134
135static inline void outw(u16 value, u32 ptr)
136{
137 register volatile u32 *port = (volatile u32 *)ptr;
138
139 if ((machine_is_ixdp2401() || machine_is_ixdp2801()) &&
140 ((port >= IXDP2X01_CS8900_VIRT_BASE) &&
141 (port <= IXDP2X01_CS8900_VIRT_END))) {
142 *port = value;
143 return;
144 }
145
146 __raw_writew((value),alignw(___io(ptr)));
147}
148#endif /* IXDP2x01 */
149
150#endif
diff --git a/include/asm-arm/arch-ixp2000/irq.h b/include/asm-arm/arch-ixp2000/irq.h
new file mode 100644
index 000000000000..ba00b23f9828
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/irq.h
@@ -0,0 +1,13 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/irq.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define fixup_irq(irq) (irq)
12
13
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
new file mode 100644
index 000000000000..0deb96c12adb
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/irqs.h
@@ -0,0 +1,174 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/irqs.h
3 *
4 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IRQS_H
16#define _IRQS_H
17
18/*
19 * Do NOT add #ifdef MACHINE_FOO in here.
20 * Simpy add your machine IRQs here and increase NR_IRQS if needed to
21 * hold your machine's IRQ table.
22 */
23
24/*
25 * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
26 * register has those bit reserved. We just mark those interrupts
27 * as invalid and this allows us to do mask/unmask with a single
28 * shift operation instead of having to map the IRQ number to
29 * a HW IRQ number.
30 */
31#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */
32#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
33#define IRQ_IXP2000_UART 2
34#define IRQ_IXP2000_GPIO 3
35#define IRQ_IXP2000_TIMER1 4
36#define IRQ_IXP2000_TIMER2 5
37#define IRQ_IXP2000_TIMER3 6
38#define IRQ_IXP2000_TIMER4 7
39#define IRQ_IXP2000_PMU 8
40#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
41#define IRQ_IXP2000_DMA1 10
42#define IRQ_IXP2000_DMA2 11
43#define IRQ_IXP2000_DMA3 12
44#define IRQ_IXP2000_PCI_DOORBELL 13
45#define IRQ_IXP2000_ME_ATTN 14
46#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
47#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
48#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */
49#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
50#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */
51#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */
52#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */
53#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
54#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */
55
56/* define generic GPIOs */
57#define IRQ_IXP2000_GPIO0 32
58#define IRQ_IXP2000_GPIO1 33
59#define IRQ_IXP2000_GPIO2 34
60#define IRQ_IXP2000_GPIO3 35
61#define IRQ_IXP2000_GPIO4 36
62#define IRQ_IXP2000_GPIO5 37
63#define IRQ_IXP2000_GPIO6 38
64#define IRQ_IXP2000_GPIO7 39
65
66/* split off the 2 PCI sources */
67#define IRQ_IXP2000_PCIA 40
68#define IRQ_IXP2000_PCIB 41
69
70#define NR_IXP2000_IRQS 42
71
72#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
73
74#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
75
76/*
77 * This allows for all the on-chip sources plus up to 32 CPLD based
78 * IRQs. Should be more than enough.
79 */
80#define IXP2000_BOARD_IRQS 32
81#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
82
83
84/*
85 * IXDP2400 specific IRQs
86 */
87#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
88#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
89#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
90#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
91#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
92#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
93#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
94#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
95
96#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
97#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
98
99/* IXDP2800 specific IRQs */
100#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
101#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
102#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
103#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
104#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
105#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
106
107#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
108#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
109
110/*
111 * IRQs on both IXDP2x01 boards
112 */
113#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
114#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
115#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
116#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
117#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
118#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
119#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
120#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
121#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
122#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
123#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
124#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
125#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
126#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
127#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
128#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
129
130#define IXDP2X01_VALID_IRQ_MASK ( \
131 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
132 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
133 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
134 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
135 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
136 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
137 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
138 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
139 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
140 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
141 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
142 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
143 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
144 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
145 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
146 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
147
148/*
149 * IXDP2401 specific IRQs
150 */
151#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
152#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
153
154#define IXDP2401_VALID_IRQ_MASK ( \
155 IXDP2X01_VALID_IRQ_MASK | \
156 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
157 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
158
159/*
160 * IXDP2801-specific IRQs
161 */
162#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
163#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
164#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
165
166#define IXDP2801_VALID_IRQ_MASK ( \
167 IXDP2X01_VALID_IRQ_MASK | \
168 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
169 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
170 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
171
172#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
173
174#endif /*_IRQS_H*/
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
new file mode 100644
index 000000000000..3a398dfbf125
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -0,0 +1,93 @@
1/*
2 * include/asm-arm/arch-ixp2000/ixdp2x00.h
3 *
4 * Register and other defines for IXDP2[48]00 platforms
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _IXDP2X00_H_
18#define _IXDP2X00_H_
19
20/*
21 * On board CPLD memory map
22 */
23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
24#define IXDP2X00_VIRT_CPLD_BASE 0xfafff000
25#define IXDP2X00_CPLD_SIZE 0x00001000
26
27
28#define IXDP2X00_CPLD_REG(x) \
29 (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
30
31/*
32 * IXDP2400 CPLD registers
33 */
34#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
35#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
36#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
37#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
38#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
39#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
40#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
41#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
42
43/*
44 * IXDP2800 CPLD registers
45 */
46#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
47#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
48
49
50#define IXDP2X00_GPIO_I2C_ENABLE 0x02
51#define IXDP2X00_GPIO_SCL 0x07
52#define IXDP2X00_GPIO_SDA 0x06
53
54/*
55 * PCI devfns for on-board devices. We need these to be able to
56 * properly translate IRQs and for device removal.
57 */
58#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
59#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
60#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
61#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
62
63#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
64#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
65#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
66
67#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
68#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
69#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
70#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
71#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
72
73#ifndef __ASSEMBLY__
74/*
75 * Master NPU will always have flash and be PCI master.
76 * Slave NPU may or may not have flash but will never be PCI master.
77 */
78static inline unsigned int ixdp2x00_master_npu(void)
79{
80 return ((ixp2000_has_flash()) && (ixp2000_is_pcimaster()));
81}
82
83/*
84 * Helper functions used by ixdp2400 and ixdp2800 specific code
85 */
86void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
87void ixdp2x00_slave_pci_postinit(void);
88void ixdp2x00_init_machine(void);
89void ixdp2x00_map_io(void);
90
91#endif
92
93#endif /*_IXDP2X00_H_ */
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
new file mode 100644
index 000000000000..b3a1bcda8d01
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -0,0 +1,57 @@
1/*
2 * include/asm-arm/arch-ixp2000/ixdp2x01.h
3 *
4 * Platform definitions for IXDP2X01 && IXDP2801 systems
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * Based on original code Copyright (c) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __IXDP2X01_H__
18#define __IXDP2X01_H__
19
20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
21#define IXDP2X01_VIRT_CPLD_BASE 0xfafff000
22#define IXDP2X01_CPLD_REGION_SIZE 0x00001000
23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
26
27#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
28#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
29
30#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
31#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
32
33#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
34#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
35
36#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
37#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
38#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
39#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
40#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
41#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
42
43#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
44
45#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
46#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
47#define IXDP2X01_FLASH_WINDOW_BITS 25
48#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
49#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
50
51#define IXDP2X01_UART_CLK 1843200
52
53#define IXDP2X01_GPIO_I2C_ENABLE 0x02
54#define IXDP2X01_GPIO_SCL 0x07
55#define IXDP2X01_GPIO_SDA 0x06
56
57#endif /* __IXDP2x01_H__ */
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
new file mode 100644
index 000000000000..6c56708d0ff0
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -0,0 +1,377 @@
1/*
2 * include/asm-arm/arch-ixp2000/ixp2000-regs.h
3 *
4 * Chipset register definitions for IXP2400/2800 based systems.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 *
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_
20
21/*
22 * Static I/O regions.
23 *
24 * Most of the registers are clumped in 4K regions spread throughout
25 * the 0xc0000000 -> 0xc0100000 address range, but we just map in
26 * the whole range using a single 1 MB section instead of small
27 * 4K pages. This has two advantages for us:
28 *
29 * 1) We use only one TLB entry for large number of on-chip I/O devices.
30 *
31 * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
32 * as required per erratum #66. We accomplish this by using a
33 * new MT_IXP2000_DEVICE memory type with the bits set as required.
34 *
35 * CAP stands for CSR Access Proxy.
36 *
37 * If you change the virtual address of this mapping, please propagate
38 * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
39 * address of the UART located in this region.
40 */
41
42#define IXP2000_CAP_PHYS_BASE 0xc0000000
43#define IXP2000_CAP_VIRT_BASE 0xfef00000
44#define IXP2000_CAP_SIZE 0x00100000
45
46/*
47 * Addresses for specific on-chip peripherals
48 */
49#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
50#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
51#define IXP2000_UART_PHYS_BASE 0xc0030000
52#define IXP2000_UART_VIRT_BASE 0xfef30000
53#define IXP2000_TIMER_VIRT_BASE 0xfef20000
54#define IXP2000_GPIO_VIRT_BASE 0Xfef10000
55
56/*
57 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
58 * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
59 * entry-macro.S, so if you ever change these please propagate
60 * the change.
61 */
62#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
63#define IXP2000_INTCTL_VIRT_BASE 0xfee00000
64#define IXP2000_INTCTL_SIZE 0x00100000
65
66#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
67#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000
68#define IXP2000_PCI_CREG_SIZE 0x00100000
69
70#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
71#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
72#define IXP2000_PCI_CSR_SIZE 0x00100000
73
74#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
75#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
76#define IXP2000_PCI_IO_SIZE 0x01000000
77
78#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
79#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
80#define IXP2000_PCI_CFG0_SIZE 0x01000000
81
82#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
83#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
84#define IXP2000_PCI_CFG1_SIZE 0x01000000
85
86/*
87 * Timers
88 */
89#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
90/* Timer control */
91#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
92#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
93#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
94#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
95/* Store initial value */
96#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
97#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
98#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
99#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
100/* Read current value */
101#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
102#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
103#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
104#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
105/* Clear associated timer interrupt */
106#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
107#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
108#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
109#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
110/* Timer watchdog enable for T4 */
111#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
112
113#define WDT_ENABLE 0x00000001
114#define TIMER_DIVIDER_256 0x00000008
115#define TIMER_ENABLE 0x00000080
116#define IRQ_MASK_TIMER1 (1 << 4)
117
118/*
119 * Interrupt controller registers
120 */
121#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
122#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
123#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
124#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
125#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
126#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
127#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
128#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
129#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
130#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
131#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60)
132#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64)
133#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68)
134#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c)
135#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80)
136#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
137#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
138#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
139#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
140#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
141#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
142#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c)
143#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180)
144#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184)
145#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188)
146#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c)
147#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0)
148#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4)
149#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8)
150#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec)
151#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200)
152#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204)
153#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208)
154#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c)
155
156/*
157 * Mask of valid IRQs in the 32-bit IRQ register. We use
158 * this to mark certain IRQs as being invalid.
159 */
160#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
161
162/*
163 * PCI config register access from core
164 */
165#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
166#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
167#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
168#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
169#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
170
171/*
172 * PCI CSRs
173 */
174#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
175
176/*
177 * PCI outbound interrupts
178 */
179#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
180#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
181/*
182 * PCI communications
183 */
184#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
185#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
186#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
187#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
188#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
189#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
190#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
191#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
192
193/*
194 * DMA engines
195 */
196#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
197#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
198#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
199#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
200#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
201#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
202#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
203#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
204#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
205#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
206#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
207#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
208#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
209#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
210#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
211#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
212#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
213#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
214#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
215/*
216 * Size masks for BARs
217 */
218#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
219#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
220/*
221 * Control and uEngine related
222 */
223#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
224#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
225#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
226#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
227#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
228#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
229/*
230 * Inbound PCI interrupt control
231 */
232#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
233#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
234
235#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
236#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */
237#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
238
239/* These are from the IRQ register in the PCI ISR register */
240#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
241#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
242#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
243#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
244#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */
245
246#define IXP2000_PCI_RST_REL (1 << 2)
247#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
248#define CFG_PCI_BOOT_HOST (1 << 2)
249#define CFG_BOOT_PROM (1 << 1)
250
251/*
252 * SlowPort CSRs
253 *
254 * The slowport is used to access things like flash, SONET framer control
255 * ports, slave microprocessors, CPLDs, and others of chip memory mapped
256 * peripherals.
257 */
258#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
259
260#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
261#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
262#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
263#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
264#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
265#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
266#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
267#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
268#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
269#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
270#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
271
272/*
273 * CCR values.
274 * The CCR configures the clock division for the slowport interface.
275 */
276#define SLOWPORT_CCR_DIV_1 0x00
277#define SLOWPORT_CCR_DIV_2 0x01
278#define SLOWPORT_CCR_DIV_4 0x02
279#define SLOWPORT_CCR_DIV_6 0x03
280#define SLOWPORT_CCR_DIV_8 0x04
281#define SLOWPORT_CCR_DIV_10 0x05
282#define SLOWPORT_CCR_DIV_12 0x06
283#define SLOWPORT_CCR_DIV_14 0x07
284#define SLOWPORT_CCR_DIV_16 0x08
285#define SLOWPORT_CCR_DIV_18 0x09
286#define SLOWPORT_CCR_DIV_20 0x0a
287#define SLOWPORT_CCR_DIV_22 0x0b
288#define SLOWPORT_CCR_DIV_24 0x0c
289#define SLOWPORT_CCR_DIV_26 0x0d
290#define SLOWPORT_CCR_DIV_28 0x0e
291#define SLOWPORT_CCR_DIV_30 0x0f
292
293/*
294 * PCR values. PCR configure the mode of the interface.
295 */
296#define SLOWPORT_MODE_FLASH 0x00
297#define SLOWPORT_MODE_LUCENT 0x01
298#define SLOWPORT_MODE_PMC_SIERRA 0x02
299#define SLOWPORT_MODE_INTEL_UP 0x03
300#define SLOWPORT_MODE_MOTOROLA_UP 0x04
301
302/*
303 * ADC values. Defines data and address bus widths.
304 */
305#define SLOWPORT_ADDR_WIDTH_8 0x00
306#define SLOWPORT_ADDR_WIDTH_16 0x01
307#define SLOWPORT_ADDR_WIDTH_24 0x02
308#define SLOWPORT_ADDR_WIDTH_32 0x03
309#define SLOWPORT_DATA_WIDTH_8 0x00
310#define SLOWPORT_DATA_WIDTH_16 0x10
311#define SLOWPORT_DATA_WIDTH_24 0x20
312#define SLOWPORT_DATA_WIDTH_32 0x30
313
314/*
315 * Masks and shifts for various fields in the WTC and RTC registers.
316 */
317#define SLOWPORT_WRTC_MASK_HD 0x0003
318#define SLOWPORT_WRTC_MASK_SU 0x003c
319#define SLOWPORT_WRTC_MASK_PW 0x03c0
320
321#define SLOWPORT_WRTC_SHIFT_HD 0x00
322#define SLOWPORT_WRTC_SHIFT_SU 0x02
323#define SLOWPORT_WRTC_SHFIT_PW 0x06
324
325
326/*
327 * GPIO registers & GPIO interface.
328 */
329#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
330#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
331#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
332#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
333#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
334#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
335#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
336#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
337#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
338#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
339#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
340#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
341#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
342#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
343#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
344#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
345#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
346#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
347
348/*
349 * "Global" registers...whatever that's supposed to mean.
350 */
351#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
352#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
353
354#define IXP2000_PROD_ID GLOBAL_REG(0x00)
355
356#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
357#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
358#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
359#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
360#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
361#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
362#define IXP2000_MAJ_REV_MASK 0x000000F0
363#define IXP2000_MIN_REV_MASK 0x0000000F
364#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
365
366#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
367#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
368#define IXP2000_RESET0 GLOBAL_REG(0x0c)
369#define IXP2000_RESET1 GLOBAL_REG(0x10)
370#define IXP2000_CCR GLOBAL_REG(0x14)
371#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
372
373#define RSTALL (1 << 16)
374#define WDT_RESET_ENABLE 0x01000000
375
376
377#endif /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
new file mode 100644
index 000000000000..d0f415c6dae9
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -0,0 +1,34 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/memory.h
3 *
4 * Copyright (c) 2002 Intel Corp.
5 * Copyright (c) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET (0x00000000UL)
17
18/*
19 * Virtual view <-> DMA view memory address translations
20 * virt_to_bus: Used to translate the virtual address to an
21 * address suitable to be passed to set_dma_addr
22 * bus_to_virt: Used to convert an address for DMA operations
23 * to an address that the kernel can use.
24 */
25#include <asm/arch/ixp2000-regs.h>
26
27#define __virt_to_bus(v) \
28 (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
29
30#define __bus_to_virt(b) \
31 __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
32
33#endif
34
diff --git a/include/asm-arm/arch-ixp2000/param.h b/include/asm-arm/arch-ixp2000/param.h
new file mode 100644
index 000000000000..2646d9e5919d
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/param.h
@@ -0,0 +1,3 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/param.h
3 */
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
new file mode 100644
index 000000000000..509e44d528d8
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -0,0 +1,166 @@
1/*
2 * include/asm-arm/arch-ixp2000/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15
16#ifndef __ASSEMBLY__
17
18/*
19 * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
20 * to on-chip I/O register to not complete fully. What this means is
21 * that if you have a write to on-chip I/O followed by a back-to-back
22 * read or write, the first write will happen twice. OR...if it's
23 * not a back-to-back transaction, the read or write will generate
24 * incorrect data.
25 *
26 * The official work around for this is to set the on-chip I/O regions
27 * as XCB=101 and then force a read-back from the register.
28 *
29 */
30#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
31
32#include <asm/system.h> /* Pickup local_irq_ functions */
33
34static inline void ixp2000_reg_write(volatile unsigned long *reg, unsigned long val)
35{
36 volatile unsigned long dummy;
37 unsigned long flags;
38
39 local_irq_save(flags);
40 *reg = val;
41 barrier();
42 dummy = *reg;
43 local_irq_restore(flags);
44}
45#else
46#define ixp2000_reg_write(reg, val) (*reg = val)
47#endif /* IXDP2400 || IXDP2401 */
48
49/*
50 * Boards may multiplex different devices on the 2nd channel of
51 * the slowport interface that each need different configuration
52 * settings. For example, the IXDP2400 uses channel 2 on the interface
53 * to access the CPLD, the switch fabric card, and the media card. Each
54 * one needs a different mode so drivers must save/restore the mode
55 * before and after each operation.
56 *
57 * acquire_slowport(&your_config);
58 * ...
59 * do slowport operations
60 * ...
61 * release_slowport();
62 *
63 * Note that while you have the slowport, you are holding a spinlock,
64 * so your code should be written as if you explicitly acquired a lock.
65 *
66 * The configuration only affects device 2 on the slowport, so the
67 * MTD map driver does not acquire/release the slowport.
68 */
69struct slowport_cfg {
70 unsigned long CCR; /* Clock divide */
71 unsigned long WTC; /* Write Timing Control */
72 unsigned long RTC; /* Read Timing Control */
73 unsigned long PCR; /* Protocol Control Register */
74 unsigned long ADC; /* Address/Data Width Control */
75};
76
77
78void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
79void ixp2000_release_slowport(struct slowport_cfg *);
80
81/*
82 * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
83 * tweaking of addresses in the MTD driver.
84 */
85static inline unsigned ixp2000_has_broken_slowport(void)
86{
87 unsigned long id = *IXP2000_PROD_ID;
88 unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
89 IXP2000_MIN_PROD_TYPE_MASK);
90 return (((id_prod ==
91 /* fixed in IXP2400-B0 */
92 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
93 IXP2000_MIN_PROD_TYPE_IXP2400)) &&
94 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
95 ((id_prod ==
96 /* fixed in IXP2800-B0 */
97 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
98 IXP2000_MIN_PROD_TYPE_IXP2800)) &&
99 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
100 ((id_prod ==
101 /* fixed in IXP2850-B0 */
102 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
103 IXP2000_MIN_PROD_TYPE_IXP2850)) &&
104 ((id & IXP2000_MAJ_REV_MASK) == 0)));
105}
106
107static inline unsigned int ixp2000_has_flash(void)
108{
109 return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
110}
111
112static inline unsigned int ixp2000_is_pcimaster(void)
113{
114 return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
115}
116
117void ixp2000_map_io(void);
118void ixp2000_init_irq(void);
119void ixp2000_init_time(unsigned long);
120unsigned long ixp2000_gettimeoffset(void);
121
122struct pci_sys_data;
123
124void ixp2000_pci_preinit(void);
125int ixp2000_pci_setup(int, struct pci_sys_data*);
126struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
127int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
128int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
129
130/*
131 * Several of the IXP2000 systems have banked flash so we need to extend the
132 * flash_platform_data structure with some private pointers
133 */
134struct ixp2000_flash_data {
135 struct flash_platform_data *platform_data;
136 int nr_banks;
137 unsigned long (*bank_setup)(unsigned long);
138};
139
140/*
141 * GPIO helper functions
142 */
143#define GPIO_IN 0
144#define GPIO_OUT 1
145
146extern void gpio_line_config(int line, int style);
147
148static inline int gpio_line_get(int line)
149{
150 return (((*IXP2000_GPIO_PLR) >> line) & 1);
151}
152
153static inline void gpio_line_set(int line, int value)
154{
155 if (value)
156 ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
157 else
158 ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
159}
160
161struct ixp2000_i2c_pins {
162 unsigned long sda_pin;
163 unsigned long scl_pin;
164};
165
166#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
new file mode 100644
index 000000000000..4f489cc0dfa5
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -0,0 +1,54 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/system.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 * Copyricht (C) 2003-2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <asm/hardware.h>
13#include <asm/mach-types.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 local_irq_disable();
23
24 /*
25 * Reset flash banking register so that we are pointing at
26 * RedBoot bank.
27 */
28 if (machine_is_ixdp2401()) {
29 *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
30 | IXDP2X01_CPLD_FLASH_INTERN);
31 *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
32 }
33
34 /*
35 * On IXDP2801 we need to write this magic sequence to the CPLD
36 * to cause a complete reset of the CPU and all external devices
37 * and moves the flash bank register back to 0.
38 */
39 if (machine_is_ixdp2801()) {
40 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
41 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
42 *IXDP2X01_CPLD_RESET_REG = reset_reg;
43 mb();
44 *IXDP2X01_CPLD_RESET_REG = 0x80000000;
45 }
46
47 /*
48 * We do a reset all if we are PCI master. We could be a slave and we
49 * don't want to do anything funky on the PCI bus.
50 */
51 if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
52 *(IXP2000_RESET0) |= (RSTALL);
53 }
54}
diff --git a/include/asm-arm/arch-ixp2000/timex.h b/include/asm-arm/arch-ixp2000/timex.h
new file mode 100644
index 000000000000..b78a183d4698
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/timex.h
@@ -0,0 +1,13 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/timex.h
3 *
4 * IXP2000 architecture timex specifications
5 */
6
7
8/*
9 * Default clock is 50MHz APB, but platform code can override this
10 */
11#define CLOCK_TICK_RATE 50000000
12
13
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h
new file mode 100644
index 000000000000..3d3d5b2ed6e9
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uncompress.h
@@ -0,0 +1,52 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/uncompress.h
3 *
4 *
5 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <linux/serial_reg.h>
18
19#define UART_BASE 0xc0030000
20
21#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
22
23#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
24#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
25#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
26#define UARTIER PHYS(0x04) /* Interrupt enable reg */
27#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
28#define UARTLCR PHYS(0x0c) /* Control reg */
29#define UARTSR PHYS(0x14) /* Status reg */
30
31
32static __inline__ void putc(char c)
33{
34 int j = 0x1000;
35
36 while (--j && !(*UARTSR & UART_LSR_THRE));
37 *UARTDR = c;
38}
39
40static void putstr(const char *s)
41{
42 while (*s)
43 {
44 putc(*s);
45 if (*s == '\n')
46 putc('\r');
47 s++;
48 }
49}
50
51#define arch_decomp_setup()
52#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
new file mode 100644
index 000000000000..2e4bcbcf31f0
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/vmalloc.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/vmalloc.h
3 *
4 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 *
6 * Copyright 2002 Intel Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Just any arbitrary offset to the start of the vmalloc VM area: the
14 * current 8MB value just means that there will be a 8MB "hole" after the
15 * physical memory until the kernel virtual memory starts. That means that
16 * any out-of-bounds memory accesses will hopefully be caught.
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;)
19 */
20#define VMALLOC_OFFSET (8*1024*1024)
21#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
22#define VMALLOC_VMADDR(x) ((unsigned long)(x))
23#define VMALLOC_END 0xfaffefff
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 16:48:17 -0500