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authorDan Williams <dan.j.williams@intel.com>2007-02-16 16:16:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-17 10:04:29 -0500
commitf80dff9da07d81da16e3b842118d47b9febf9c01 (patch)
treeea2da17c5af516c241b3ea3b4dd4fa47d9d86769 /include/asm-arm/arch-iop33x/entry-macro.S
parent588ef7693574cfbcb228f48d5478c2b39a9b0c9f (diff)
[ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user
get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-iop33x/entry-macro.S')
-rw-r--r--include/asm-arm/arch-iop33x/entry-macro.S35
1 files changed, 25 insertions, 10 deletions
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
index 92b791702e34..b8e3d449e882 100644
--- a/include/asm-arm/arch-iop33x/entry-macro.S
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -9,14 +9,29 @@
9 */ 9 */
10#include <asm/arch/iop33x.h> 10#include <asm/arch/iop33x.h>
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_preamble, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07C8) 16 mrc p15, 0, \tmp, c15, c1, 0
17 ldr \irqstat, [\base] @ Read IINTVEC 17 orr \tmp, \tmp, #(1 << 6)
18 cmp \irqstat, #0 18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 ldreq \irqstat, [\base] @ erratum 63 workaround 19 mrc p15, 0, \tmp, c15, c1, 0
20 adds \irqnr, \irqstat, #1 20 mov \tmp, \tmp
21 movne \irqnr, \irqstat, lsr #2 21 sub pc, pc, #4 @ cp_wait
22 .endm 22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
26 cmp \irqstat, #0
27 mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
28 adds \irqnr, \irqstat, #1
29 movne \irqnr, \irqstat, lsr #2
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 mrc p15, 0, \tmp1, c15, c1, 0
34 ands \tmp2, \tmp1, #(1 << 6)
35 bicne \tmp1, \tmp1, #(1 << 6)
36 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
37 .endm