[ARM] Merge remaining IOP code

Conflicts:
	include/asm-arm/arch-at91rm9200/entry-macro.S

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 28 insertions, 9 deletions

diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
index 1500cbbd2295..207db99dfbd2 100644
--- a/include/asm-arm/arch-iop32x/entry-macro.S
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -9,13 +9,28 @@
  */
 #include <asm/arch/iop32x.h>
 
-                .macro  disable_fiq
-                .endm
+        .macro  disable_fiq
+        .endm
 
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =IOP3XX_REG_ADDR(0x07D8)
-                ldr     \irqstat, [\base]               @ Read IINTSRC
-                cmp     \irqstat, #0
-                clzne   \irqnr, \irqstat
-                rsbne   \irqnr, \irqnr, #31
-                .endm
+        .macro get_irqnr_preamble, base, tmp
+        mrc     p15, 0, \tmp, c15, c1, 0
+        orr     \tmp, \tmp, #(1 << 6)
+        mcr     p15, 0, \tmp, c15, c1, 0        @ Enable cp6 access
+        mrc     p15, 0, \tmp, c15, c1, 0
+        mov     \tmp, \tmp
+        sub     pc, pc, #4                      @ cp_wait
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
+        cmp     \irqstat, #0
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
+
+        .macro arch_ret_to_user, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c15, c1, 0
+        ands    \tmp2, \tmp1, #(1 << 6)
+        bicne   \tmp1, \tmp1, #(1 << 6)
+        mcrne   p15, 0, \tmp1, c15, c1, 0       @ Disable cp6 access
+        .endm
diff --git a/include/asm-arm/arch-iop32x/time.h b/include/asm-arm/arch-iop32x/time.h
new file mode 100644
index 000000000000..0f28c9949623
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/time.h
@@ -0,0 +1,4 @@
+#ifndef _IOP32X_TIME_H_
+#define _IOP32X_TIME_H_
+#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
+#endif