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authorDan Williams <dan.j.williams@intel.com>2007-02-13 11:13:34 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-17 10:05:40 -0500
commit3668b45d46f777b0773ef5ff49531c1144efb6dd (patch)
treed9bb1a1ce8d0cce8bff99578fc0ba4bf8cdedd75 /include/asm-arm/arch-iop13xx/time.h
parent4434c5c7fd61c6713de882a2272b66f32fe7cac3 (diff)
[ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xx
* architecture specific details are handled in asm/arch/time.h * ARCH_IOP13XX now selects PLAT_IOP * as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on XSC3 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-iop13xx/time.h')
-rw-r--r--include/asm-arm/arch-iop13xx/time.h51
1 files changed, 51 insertions, 0 deletions
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
new file mode 100644
index 000000000000..77a837a02dec
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -0,0 +1,51 @@
1#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
10void iop_init_time(unsigned long tickrate);
11unsigned long iop_gettimeoffset(void);
12
13static inline void write_tmr0(u32 val)
14{
15 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
16}
17
18static inline void write_tmr1(u32 val)
19{
20 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
21}
22
23static inline u32 read_tcr0(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
27 return val;
28}
29
30static inline u32 read_tcr1(void)
31{
32 u32 val;
33 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
34 return val;
35}
36
37static inline void write_trr0(u32 val)
38{
39 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
40}
41
42static inline void write_trr1(u32 val)
43{
44 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
45}
46
47static inline void write_tisr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
50}
51#endif