[ARM] 4495/1: iop: combined watchdog timer driver for iop3xx and iop13xx

In order for this driver to be shared across the iop architectures the
iop3xx and iop13xx header files are modified to present a common interface
for the iop_wdt driver.

Details:
* iop13xx supports disabling the timer while iop3xx does not.  This requires
  a few 'compatibility' definitions in include/asm-arm/hardware/iop3xx.h to
  preclude adding #ifdef CONFIG_ARCH_IOP13XX blocks to the driver code.
* The heartbeat interval is derived from the internal bus clock rate, so this
  this patch also exports the tick rate to the iop_wdt driver.

Cc: Curt Bruns <curt.e.bruns@intel.com>
Cc: Peter Milne <peter.milne@d-tacq.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 32 deletions

diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1f..8575af8db78c 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
         cpu_do_idle();
 }
 
-/* WDTCR CP6 R7 Page 9 */
-static inline u32 read_wdtcr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtcr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
-}
-
-/* WDTSR CP6 R8 Page 9 */
-static inline u32 read_wdtsr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtsr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
-}
-
-#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
-#define IOP13XX_WDTCR_EN        0xe1e1e1e1
-#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
-#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
-#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
-#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
 static inline void arch_reset(char mode)
 {
         /*
          * Reset the internal bus (warning both cores are reset)
          */
-        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
-        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtcr(IOP_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN);
         write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
         write_wdtcr(0x1000);