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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-05 11:14:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:48 -0400
commita09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch)
tree69689f467179891b498bd7423fcf61925173db31 /include/asm-arm/arch-integrator
parenta1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff)
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-integrator')
-rw-r--r--include/asm-arm/arch-integrator/bits.h61
-rw-r--r--include/asm-arm/arch-integrator/cm.h36
-rw-r--r--include/asm-arm/arch-integrator/debug-macro.S22
-rw-r--r--include/asm-arm/arch-integrator/dma.h19
-rw-r--r--include/asm-arm/arch-integrator/entry-macro.S44
-rw-r--r--include/asm-arm/arch-integrator/hardware.h48
-rw-r--r--include/asm-arm/arch-integrator/impd1.h18
-rw-r--r--include/asm-arm/arch-integrator/io.h36
-rw-r--r--include/asm-arm/arch-integrator/irqs.h82
-rw-r--r--include/asm-arm/arch-integrator/lm.h23
-rw-r--r--include/asm-arm/arch-integrator/memory.h39
-rw-r--r--include/asm-arm/arch-integrator/platform.h469
-rw-r--r--include/asm-arm/arch-integrator/system.h44
-rw-r--r--include/asm-arm/arch-integrator/timex.h26
-rw-r--r--include/asm-arm/arch-integrator/uncompress.h50
-rw-r--r--include/asm-arm/arch-integrator/vmalloc.h20
16 files changed, 0 insertions, 1037 deletions
diff --git a/include/asm-arm/arch-integrator/bits.h b/include/asm-arm/arch-integrator/bits.h
deleted file mode 100644
index 09b024e0496a..000000000000
--- a/include/asm-arm/arch-integrator/bits.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16/* DO NOT EDIT!! - this file automatically generated
17 * from .s file by awk -f s2h.awk
18 */
19/* Bit field definitions
20 * Copyright (C) ARM Limited 1998. All rights reserved.
21 */
22
23#ifndef __bits_h
24#define __bits_h 1
25
26#define BIT0 0x00000001
27#define BIT1 0x00000002
28#define BIT2 0x00000004
29#define BIT3 0x00000008
30#define BIT4 0x00000010
31#define BIT5 0x00000020
32#define BIT6 0x00000040
33#define BIT7 0x00000080
34#define BIT8 0x00000100
35#define BIT9 0x00000200
36#define BIT10 0x00000400
37#define BIT11 0x00000800
38#define BIT12 0x00001000
39#define BIT13 0x00002000
40#define BIT14 0x00004000
41#define BIT15 0x00008000
42#define BIT16 0x00010000
43#define BIT17 0x00020000
44#define BIT18 0x00040000
45#define BIT19 0x00080000
46#define BIT20 0x00100000
47#define BIT21 0x00200000
48#define BIT22 0x00400000
49#define BIT23 0x00800000
50#define BIT24 0x01000000
51#define BIT25 0x02000000
52#define BIT26 0x04000000
53#define BIT27 0x08000000
54#define BIT28 0x10000000
55#define BIT29 0x20000000
56#define BIT30 0x40000000
57#define BIT31 0x80000000
58
59#endif
60
61/* END */
diff --git a/include/asm-arm/arch-integrator/cm.h b/include/asm-arm/arch-integrator/cm.h
deleted file mode 100644
index 1ab353e23595..000000000000
--- a/include/asm-arm/arch-integrator/cm.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * update the core module control register.
3 */
4void cm_control(u32, u32);
5
6#define CM_CTRL_LED (1 << 0)
7#define CM_CTRL_nMBDET (1 << 1)
8#define CM_CTRL_REMAP (1 << 2)
9#define CM_CTRL_RESET (1 << 3)
10
11/*
12 * Integrator/AP,PP2 specific
13 */
14#define CM_CTRL_HIGHVECTORS (1 << 4)
15#define CM_CTRL_BIGENDIAN (1 << 5)
16#define CM_CTRL_FASTBUS (1 << 6)
17#define CM_CTRL_SYNC (1 << 7)
18
19/*
20 * ARM926/946/966 Integrator/CP specific
21 */
22#define CM_CTRL_LCDBIASEN (1 << 8)
23#define CM_CTRL_LCDBIASUP (1 << 9)
24#define CM_CTRL_LCDBIASDN (1 << 10)
25#define CM_CTRL_LCDMUXSEL_MASK (7 << 11)
26#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11)
27#define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11)
28#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11)
29#define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11)
30#define CM_CTRL_LCDEN0 (1 << 14)
31#define CM_CTRL_LCDEN1 (1 << 15)
32#define CM_CTRL_STATIC1 (1 << 16)
33#define CM_CTRL_STATIC2 (1 << 17)
34#define CM_CTRL_STATIC (1 << 18)
35#define CM_CTRL_n24BITEN (1 << 19)
36#define CM_CTRL_EBIWP (1 << 20)
diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S
deleted file mode 100644
index 85b327c352df..000000000000
--- a/include/asm-arm/arch-integrator/debug-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/include/asm-arm/arch-integrator/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0x16000000 @ physical base address
18 movne \rx, #0xf0000000 @ virtual base
19 addne \rx, \rx, #0x16000000 >> 4
20 .endm
21
22#include <asm/hardware/debug-pl01x.S>
diff --git a/include/asm-arm/arch-integrator/dma.h b/include/asm-arm/arch-integrator/dma.h
deleted file mode 100644
index 83fd6bbaf9d3..000000000000
--- a/include/asm-arm/arch-integrator/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S
deleted file mode 100644
index ef535a68bdd3..000000000000
--- a/include/asm-arm/arch-integrator/entry-macro.S
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-arm/arch-integrator/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Integrator platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/hardware.h>
11#include <asm/arch/irqs.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23/* FIXME: should not be using soo many LDRs here */
24 ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
25 mov \irqnr, #IRQ_PIC_START
26 ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
27 ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
28 teq \irqstat, #0
29 ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
30 moveq \irqnr, #IRQ_CIC_START
31
321001: tst \irqstat, #15
33 bne 1002f
34 add \irqnr, \irqnr, #4
35 movs \irqstat, \irqstat, lsr #4
36 bne 1001b
371002: tst \irqstat, #1
38 bne 1003f
39 add \irqnr, \irqnr, #1
40 movs \irqstat, \irqstat, lsr #1
41 bne 1002b
421003: /* EQ will be set if no irqs pending */
43 .endm
44
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
deleted file mode 100644
index 6f0947bc500d..000000000000
--- a/include/asm-arm/arch-integrator/hardware.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/hardware.h
3 *
4 * This file contains the hardware definitions of the Integrator.
5 *
6 * Copyright (C) 1999 ARM Limited.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27
28/*
29 * Where in virtual memory the IO devices (timers, system controllers
30 * and so on)
31 */
32#define IO_BASE 0xF0000000 // VA of IO
33#define IO_SIZE 0x0B000000 // How much?
34#define IO_START INTEGRATOR_HDR_BASE // PA of IO
35
36#define PCIO_BASE PCI_IO_VADDR
37#define PCIMEM_BASE PCI_MEMORY_VADDR
38
39/* macro to get at IO space when running virtually */
40#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE)
41
42#define pcibios_assign_all_busses() 1
43
44#define PCIBIOS_MIN_IO 0x6000
45#define PCIBIOS_MIN_MEM 0x00100000
46
47#endif
48
diff --git a/include/asm-arm/arch-integrator/impd1.h b/include/asm-arm/arch-integrator/impd1.h
deleted file mode 100644
index d75de4b14237..000000000000
--- a/include/asm-arm/arch-integrator/impd1.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#define IMPD1_OSC1 0x00
2#define IMPD1_OSC2 0x04
3#define IMPD1_LOCK 0x08
4#define IMPD1_LEDS 0x0c
5#define IMPD1_INT 0x10
6#define IMPD1_SW 0x14
7#define IMPD1_CTRL 0x18
8
9#define IMPD1_CTRL_DISP_LCD (0 << 0)
10#define IMPD1_CTRL_DISP_VGA (1 << 0)
11#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
12#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
13#define IMPD1_CTRL_DISP_MASK (7 << 0)
14
15struct device;
16
17void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
18
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
deleted file mode 100644
index c8f2175948bd..000000000000
--- a/include/asm-arm/arch-integrator/io.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/io.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#define IO_SPACE_LIMIT 0xffff
24
25/*
26 * WARNING: this has to mirror definitions in platform.h
27 */
28#define PCI_MEMORY_VADDR 0xe8000000
29#define PCI_CONFIG_VADDR 0xec000000
30#define PCI_V3_VADDR 0xed000000
31#define PCI_IO_VADDR 0xee000000
32
33#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
34#define __mem_pci(a) (a)
35
36#endif
diff --git a/include/asm-arm/arch-integrator/irqs.h b/include/asm-arm/arch-integrator/irqs.h
deleted file mode 100644
index ba7b3afee445..000000000000
--- a/include/asm-arm/arch-integrator/irqs.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/irqs.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Interrupt numbers
24 */
25#define IRQ_PIC_START 0
26#define IRQ_SOFTINT 0
27#define IRQ_UARTINT0 1
28#define IRQ_UARTINT1 2
29#define IRQ_KMIINT0 3
30#define IRQ_KMIINT1 4
31#define IRQ_TIMERINT0 5
32#define IRQ_TIMERINT1 6
33#define IRQ_TIMERINT2 7
34#define IRQ_RTCINT 8
35#define IRQ_AP_EXPINT0 9
36#define IRQ_AP_EXPINT1 10
37#define IRQ_AP_EXPINT2 11
38#define IRQ_AP_EXPINT3 12
39#define IRQ_AP_PCIINT0 13
40#define IRQ_AP_PCIINT1 14
41#define IRQ_AP_PCIINT2 15
42#define IRQ_AP_PCIINT3 16
43#define IRQ_AP_V3INT 17
44#define IRQ_AP_CPINT0 18
45#define IRQ_AP_CPINT1 19
46#define IRQ_AP_LBUSTIMEOUT 20
47#define IRQ_AP_APCINT 21
48#define IRQ_CP_CLCDCINT 22
49#define IRQ_CP_MMCIINT0 23
50#define IRQ_CP_MMCIINT1 24
51#define IRQ_CP_AACIINT 25
52#define IRQ_CP_CPPLDINT 26
53#define IRQ_CP_ETHINT 27
54#define IRQ_CP_TSPENINT 28
55#define IRQ_PIC_END 31
56
57#define IRQ_CIC_START 32
58#define IRQ_CM_SOFTINT 32
59#define IRQ_CM_COMMRX 33
60#define IRQ_CM_COMMTX 34
61#define IRQ_CIC_END 34
62
63/*
64 * IntegratorCP only
65 */
66#define IRQ_SIC_START 35
67#define IRQ_SIC_CP_SOFTINT 35
68#define IRQ_SIC_CP_RI0 36
69#define IRQ_SIC_CP_RI1 37
70#define IRQ_SIC_CP_CARDIN 38
71#define IRQ_SIC_CP_LMINT0 39
72#define IRQ_SIC_CP_LMINT1 40
73#define IRQ_SIC_CP_LMINT2 41
74#define IRQ_SIC_CP_LMINT3 42
75#define IRQ_SIC_CP_LMINT4 43
76#define IRQ_SIC_CP_LMINT5 44
77#define IRQ_SIC_CP_LMINT6 45
78#define IRQ_SIC_CP_LMINT7 46
79#define IRQ_SIC_END 46
80
81#define NR_IRQS 47
82
diff --git a/include/asm-arm/arch-integrator/lm.h b/include/asm-arm/arch-integrator/lm.h
deleted file mode 100644
index 28186b6f2c09..000000000000
--- a/include/asm-arm/arch-integrator/lm.h
+++ /dev/null
@@ -1,23 +0,0 @@
1
2struct lm_device {
3 struct device dev;
4 struct resource resource;
5 unsigned int irq;
6 unsigned int id;
7};
8
9struct lm_driver {
10 struct device_driver drv;
11 int (*probe)(struct lm_device *);
12 void (*remove)(struct lm_device *);
13 int (*suspend)(struct lm_device *, pm_message_t);
14 int (*resume)(struct lm_device *);
15};
16
17int lm_driver_register(struct lm_driver *drv);
18void lm_driver_unregister(struct lm_driver *drv);
19
20int lm_device_register(struct lm_device *dev);
21
22#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
23#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
deleted file mode 100644
index 1ab56d783e7c..000000000000
--- a/include/asm-arm/arch-integrator/memory.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/memory.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PHYS_OFFSET UL(0x00000000)
27#define BUS_OFFSET UL(0x80000000)
28
29/*
30 * Virtual view <-> DMA view memory address translations
31 * virt_to_bus: Used to translate the virtual address to an
32 * address suitable to be passed to set_dma_addr
33 * bus_to_virt: Used to convert an address for DMA operations
34 * to an address that the kernel can use.
35 */
36#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET)
37#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET)
38
39#endif
diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h
deleted file mode 100644
index 83c4c1ceb411..000000000000
--- a/include/asm-arm/arch-integrator/platform.h
+++ /dev/null
@@ -1,469 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16/* DO NOT EDIT!! - this file automatically generated
17 * from .s file by awk -f s2h.awk
18 */
19/**************************************************************************
20 * * Copyright © ARM Limited 1998. All rights reserved.
21 * ***********************************************************************/
22/* ************************************************************************
23 *
24 * Integrator address map
25 *
26 * NOTE: This is a multi-hosted header file for use with uHAL and
27 * supported debuggers.
28 *
29 * $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
30 *
31 * ***********************************************************************/
32
33#ifndef __address_h
34#define __address_h 1
35
36/* ========================================================================
37 * Integrator definitions
38 * ========================================================================
39 * ------------------------------------------------------------------------
40 * Memory definitions
41 * ------------------------------------------------------------------------
42 * Integrator memory map
43 *
44 */
45#define INTEGRATOR_BOOT_ROM_LO 0x00000000
46#define INTEGRATOR_BOOT_ROM_HI 0x20000000
47#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
48#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
49
50/*
51 * New Core Modules have different amounts of SSRAM, the amount of SSRAM
52 * fitted can be found in HDR_STAT.
53 *
54 * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
55 * the minimum amount of SSRAM fitted on any core module.
56 *
57 * New Core Modules also alias the SSRAM.
58 *
59 */
60#define INTEGRATOR_SSRAM_BASE 0x00000000
61#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
62#define INTEGRATOR_SSRAM_SIZE SZ_256K
63
64#define INTEGRATOR_FLASH_BASE 0x24000000
65#define INTEGRATOR_FLASH_SIZE SZ_32M
66
67#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
68#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
69
70/*
71 * SDRAM is a SIMM therefore the size is not known.
72 *
73 */
74#define INTEGRATOR_SDRAM_BASE 0x00040000
75
76#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
77#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
78#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
79#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
80#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
81
82/*
83 * Logic expansion modules
84 *
85 */
86#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
87#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
88#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
89#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
90#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
91
92/* ------------------------------------------------------------------------
93 * Integrator header card registers
94 * ------------------------------------------------------------------------
95 *
96 */
97#define INTEGRATOR_HDR_ID_OFFSET 0x00
98#define INTEGRATOR_HDR_PROC_OFFSET 0x04
99#define INTEGRATOR_HDR_OSC_OFFSET 0x08
100#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
101#define INTEGRATOR_HDR_STAT_OFFSET 0x10
102#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
103#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
104#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
105#define INTEGRATOR_HDR_IC_OFFSET 0x40
106#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
107#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
108
109#define INTEGRATOR_HDR_BASE 0x10000000
110#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
111#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
112#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
113#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
114#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
115#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
116#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
117#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
118#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
119#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
120#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
121
122#define INTEGRATOR_HDR_CTRL_LED 0x01
123#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
124#define INTEGRATOR_HDR_CTRL_REMAP 0x04
125#define INTEGRATOR_HDR_CTRL_RESET 0x08
126#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
127#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
128#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
129#define INTEGRATOR_HDR_CTRL_SYNC 0x80
130
131#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
132#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
133#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
134#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
135#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
136#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
137#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
138#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
139#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
140#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
141#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
142#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
143#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
144#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
145#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
146#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
147#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
148#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
149#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
150#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
151#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
152#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
153#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
154#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
155#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
156#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
157#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
158#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
159#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
160#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
161#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
162#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
163
164#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
165#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
166#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
167#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
168#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
169#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
170#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
171#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
172#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
173#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
174#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
175
176#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
177#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
178#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
179#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
180#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
181
182#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
183
184
185/* ------------------------------------------------------------------------
186 * Integrator system registers
187 * ------------------------------------------------------------------------
188 *
189 */
190
191/*
192 * System Controller
193 *
194 */
195#define INTEGRATOR_SC_ID_OFFSET 0x00
196#define INTEGRATOR_SC_OSC_OFFSET 0x04
197#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
198#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
199#define INTEGRATOR_SC_DEC_OFFSET 0x10
200#define INTEGRATOR_SC_ARB_OFFSET 0x14
201#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
202#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
203
204#define INTEGRATOR_SC_BASE 0x11000000
205#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
206#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
207#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
208#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
209#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
210#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
211#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
212#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
213
214#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
215#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
216#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
217#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
218#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
219#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
220
221#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
222#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
223#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
224
225#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
226#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
227#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
228#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
229#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
230#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
231#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
232
233/*
234 * External Bus Interface
235 *
236 */
237#define INTEGRATOR_EBI_BASE 0x12000000
238
239#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
240#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
241#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
242#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
243#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
244
245#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
246#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
247#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
248#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
249#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
250
251#define INTEGRATOR_EBI_8_BIT 0x00
252#define INTEGRATOR_EBI_16_BIT 0x01
253#define INTEGRATOR_EBI_32_BIT 0x02
254#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
255#define INTEGRATOR_EBI_SYNC 0x08
256#define INTEGRATOR_EBI_WS_2 0x00
257#define INTEGRATOR_EBI_WS_3 0x10
258#define INTEGRATOR_EBI_WS_4 0x20
259#define INTEGRATOR_EBI_WS_5 0x30
260#define INTEGRATOR_EBI_WS_6 0x40
261#define INTEGRATOR_EBI_WS_7 0x50
262#define INTEGRATOR_EBI_WS_8 0x60
263#define INTEGRATOR_EBI_WS_9 0x70
264#define INTEGRATOR_EBI_WS_10 0x80
265#define INTEGRATOR_EBI_WS_11 0x90
266#define INTEGRATOR_EBI_WS_12 0xA0
267#define INTEGRATOR_EBI_WS_13 0xB0
268#define INTEGRATOR_EBI_WS_14 0xC0
269#define INTEGRATOR_EBI_WS_15 0xD0
270#define INTEGRATOR_EBI_WS_16 0xE0
271#define INTEGRATOR_EBI_WS_17 0xF0
272
273
274#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
275#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
276#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
277#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
278#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
279#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
280#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
281
282/*
283 * LED's & Switches
284 *
285 */
286#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
287#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
288#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
289
290#define INTEGRATOR_DBG_BASE 0x1A000000
291#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
292#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
293#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
294
295
296#if defined(CONFIG_ARCH_INTEGRATOR_AP)
297#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */
298#elif defined(CONFIG_ARCH_INTEGRATOR_CP)
299#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */
300#endif
301
302/* ------------------------------------------------------------------------
303 * KMI keyboard/mouse definitions
304 * ------------------------------------------------------------------------
305 */
306/* PS2 Keyboard interface */
307#define KMI0_BASE INTEGRATOR_KBD_BASE
308
309/* PS2 Mouse interface */
310#define KMI1_BASE INTEGRATOR_MOUSE_BASE
311
312/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
313
314/* ------------------------------------------------------------------------
315 * Where in the memory map does PCI live?
316 * ------------------------------------------------------------------------
317 * This represents a fairly liberal usage of address space. Even though
318 * the V3 only has two windows (therefore we need to map stuff on the fly),
319 * we maintain the same addresses, even if they're not mapped.
320 *
321 */
322#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
323/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
324 */
325#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
326/* unused (128-16)M from B1000000-B7FFFFFF
327 */
328#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
329/* unused ((128-16)M - 64K) from XXX
330 */
331#define PHYS_PCI_V3_BASE 0x62000000
332
333#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
334
335/* 'export' these to UHAL */
336#define UHAL_PCI_IO PCI_IO_BASE
337#define UHAL_PCI_MEM PCI_MEM_BASE
338#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
339#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
340#define UHAL_PCI_MAX_SLOT 20
341
342/* ========================================================================
343 * Start of uHAL definitions
344 * ========================================================================
345 */
346
347/* ------------------------------------------------------------------------
348 * Integrator Interrupt Controllers
349 * ------------------------------------------------------------------------
350 *
351 * Offsets from interrupt controller base
352 *
353 * System Controller interrupt controller base is
354 *
355 * INTEGRATOR_IC_BASE + (header_number << 6)
356 *
357 * Core Module interrupt controller base is
358 *
359 * INTEGRATOR_HDR_IC
360 *
361 */
362#define IRQ_STATUS 0
363#define IRQ_RAW_STATUS 0x04
364#define IRQ_ENABLE 0x08
365#define IRQ_ENABLE_SET 0x08
366#define IRQ_ENABLE_CLEAR 0x0C
367
368#define INT_SOFT_SET 0x10
369#define INT_SOFT_CLEAR 0x14
370
371#define FIQ_STATUS 0x20
372#define FIQ_RAW_STATUS 0x24
373#define FIQ_ENABLE 0x28
374#define FIQ_ENABLE_SET 0x28
375#define FIQ_ENABLE_CLEAR 0x2C
376
377
378/* ------------------------------------------------------------------------
379 * Interrupts
380 * ------------------------------------------------------------------------
381 *
382 *
383 * Each Core Module has two interrupts controllers, one on the core module
384 * itself and one in the system controller on the motherboard. The
385 * READ_INT macro in target.s reads both interrupt controllers and returns
386 * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
387 * and bits 24 to 31 are from the core module.
388 *
389 * The following definitions relate to the bitmask returned by READ_INT.
390 *
391 */
392
393/* ------------------------------------------------------------------------
394 * LED's - The header LED is not accessible via the uHAL API
395 * ------------------------------------------------------------------------
396 *
397 */
398#define GREEN_LED 0x01
399#define YELLOW_LED 0x02
400#define RED_LED 0x04
401#define GREEN_LED_2 0x08
402#define ALL_LEDS 0x0F
403
404#define LED_BANK INTEGRATOR_DBG_LEDS
405
406/*
407 * Memory definitions - run uHAL out of SSRAM.
408 *
409 */
410#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
411
412/*
413 * Application Flash
414 *
415 */
416#define FLASH_BASE INTEGRATOR_FLASH_BASE
417#define FLASH_SIZE INTEGRATOR_FLASH_SIZE
418#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
419#define FLASH_BLOCK_SIZE SZ_128K
420
421/*
422 * Boot Flash
423 *
424 */
425#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
426#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
427#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
428
429/*
430 * Clean base - dummy
431 *
432 */
433#define CLEAN_BASE EPROM_BASE
434
435/*
436 * Timer definitions
437 *
438 * Only use timer 1 & 2
439 * (both run at 24MHz and will need the clock divider set to 16).
440 *
441 * Timer 0 runs at bus frequency and therefore could vary and currently
442 * uHAL can't handle that.
443 *
444 */
445
446#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
447#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
448#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
449
450#define MAX_TIMER 2
451#define MAX_PERIOD 699050
452#define TICKS_PER_uSEC 24
453
454/*
455 * These are useconds NOT ticks.
456 *
457 */
458#define mSEC_1 1000
459#define mSEC_5 (mSEC_1 * 5)
460#define mSEC_10 (mSEC_1 * 10)
461#define mSEC_25 (mSEC_1 * 25)
462#define SEC_1 (mSEC_1 * 1000)
463
464#define INTEGRATOR_CSR_BASE 0x10000000
465#define INTEGRATOR_CSR_SIZE 0x10000000
466
467#endif
468
469/* END */
diff --git a/include/asm-arm/arch-integrator/system.h b/include/asm-arm/arch-integrator/system.h
deleted file mode 100644
index 8ea442237d20..000000000000
--- a/include/asm-arm/arch-integrator/system.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/system.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <asm/arch/cm.h>
25
26static inline void arch_idle(void)
27{
28 /*
29 * This should do all the clock switching
30 * and wait for interrupt tricks
31 */
32 cpu_do_idle();
33}
34
35static inline void arch_reset(char mode)
36{
37 /*
38 * To reset, we hit the on-board reset register
39 * in the system FPGA
40 */
41 cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
42}
43
44#endif
diff --git a/include/asm-arm/arch-integrator/timex.h b/include/asm-arm/arch-integrator/timex.h
deleted file mode 100644
index 87a762818ba2..000000000000
--- a/include/asm-arm/arch-integrator/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/timex.h
3 *
4 * Integrator architecture timex specifications
5 *
6 * Copyright (C) 1999 ARM Limited
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23/*
24 * ??
25 */
26#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h
deleted file mode 100644
index f61825c4d901..000000000000
--- a/include/asm-arm/arch-integrator/uncompress.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#define AMBA_UART_DR (*(volatile unsigned char *)0x16000000)
22#define AMBA_UART_LCRH (*(volatile unsigned char *)0x16000008)
23#define AMBA_UART_LCRM (*(volatile unsigned char *)0x1600000c)
24#define AMBA_UART_LCRL (*(volatile unsigned char *)0x16000010)
25#define AMBA_UART_CR (*(volatile unsigned char *)0x16000014)
26#define AMBA_UART_FR (*(volatile unsigned char *)0x16000018)
27
28/*
29 * This does not append a newline
30 */
31static void putc(int c)
32{
33 while (AMBA_UART_FR & (1 << 5))
34 barrier();
35
36 AMBA_UART_DR = c;
37}
38
39static inline void flush(void)
40{
41 while (AMBA_UART_FR & (1 << 3))
42 barrier();
43}
44
45/*
46 * nothing to do
47 */
48#define arch_decomp_setup()
49
50#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h
deleted file mode 100644
index 170cccece523..000000000000
--- a/include/asm-arm/arch-integrator/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 23:48:51 -0500