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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-imx
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-imx')
-rw-r--r--include/asm-arm/arch-imx/debug-macro.S34
-rw-r--r--include/asm-arm/arch-imx/dma.h71
-rw-r--r--include/asm-arm/arch-imx/entry-macro.S29
-rw-r--r--include/asm-arm/arch-imx/hardware.h99
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h548
-rw-r--r--include/asm-arm/arch-imx/io.h28
-rw-r--r--include/asm-arm/arch-imx/irq.h20
-rw-r--r--include/asm-arm/arch-imx/irqs.h116
-rw-r--r--include/asm-arm/arch-imx/memory.h38
-rw-r--r--include/asm-arm/arch-imx/mx1ads.h36
-rw-r--r--include/asm-arm/arch-imx/param.h19
-rw-r--r--include/asm-arm/arch-imx/system.h40
-rw-r--r--include/asm-arm/arch-imx/timex.h27
-rw-r--r--include/asm-arm/arch-imx/uncompress.h78
-rw-r--r--include/asm-arm/arch-imx/vmalloc.h32
15 files changed, 1215 insertions, 0 deletions
diff --git a/include/asm-arm/arch-imx/debug-macro.S b/include/asm-arm/arch-imx/debug-macro.S
new file mode 100644
index 000000000000..83f552f7bcc1
--- /dev/null
+++ b/include/asm-arm/arch-imx/debug-macro.S
@@ -0,0 +1,34 @@
1/* linux/include/asm-arm/arch-imx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0x00000000 @ physical
18 movne \rx, #0xe0000000 @ virtual
19 orr \rx, \rx, #0x00200000
20 orr \rx, \rx, #0x00006000 @ UART1 offset
21 .endm
22
23 .macro senduart,rd,rx
24 str \rd, [\rx, #0x40] @ TXDATA
25 .endm
26
27 .macro waituart,rd,rx
28 .endm
29
30 .macro busyuart,rd,rx
311002: ldr \rd, [\rx, #0x98] @ SR2
32 tst \rd, #1 << 3 @ TXDC
33 beq 1002b @ wait until transmit done
34 .endm
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h
new file mode 100644
index 000000000000..dbdc01780413
--- /dev/null
+++ b/include/asm-arm/arch-imx/dma.h
@@ -0,0 +1,71 @@
1/*
2 * linux/include/asm-arm/imxads/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_DMA_H
21#define __ASM_ARCH_DMA_H
22
23#define MAX_DMA_ADDRESS 0xffffffff
24
25#define MAX_DMA_CHANNELS 0
26
27/*
28 * DMA registration
29 */
30
31typedef enum {
32 DMA_PRIO_HIGH = 0,
33 DMA_PRIO_MEDIUM = 3,
34 DMA_PRIO_LOW = 6
35} imx_dma_prio;
36
37int imx_request_dma(char *name, imx_dma_prio prio,
38 void (*irq_handler) (int, void *, struct pt_regs *),
39 void (*err_handler) (int, void *, struct pt_regs *),
40 void *data);
41
42void imx_free_dma(int dma_ch);
43
44
45#define DMA_REQ_UART3_T 2
46#define DMA_REQ_UART3_R 3
47#define DMA_REQ_SSI2_T 4
48#define DMA_REQ_SSI2_R 5
49#define DMA_REQ_CSI_STAT 6
50#define DMA_REQ_CSI_R 7
51#define DMA_REQ_MSHC 8
52#define DMA_REQ_DSPA_DCT_DOUT 9
53#define DMA_REQ_DSPA_DCT_DIN 10
54#define DMA_REQ_DSPA_MAC 11
55#define DMA_REQ_EXT 12
56#define DMA_REQ_SDHC 13
57#define DMA_REQ_SPI1_R 14
58#define DMA_REQ_SPI1_T 15
59#define DMA_REQ_SSI_T 16
60#define DMA_REQ_SSI_R 17
61#define DMA_REQ_ASP_DAC 18
62#define DMA_REQ_ASP_ADC 19
63#define DMA_REQ_USP_EP(x) (20+(x))
64#define DMA_REQ_SPI2_R 26
65#define DMA_REQ_SPI2_T 27
66#define DMA_REQ_UART2_T 28
67#define DMA_REQ_UART2_R 29
68#define DMA_REQ_UART1_T 30
69#define DMA_REQ_UART1_R 31
70
71#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
new file mode 100644
index 000000000000..b40ea7cf88ec
--- /dev/null
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -0,0 +1,29 @@
1/*
2 * include/asm-arm/arch-imx/entry-macro.S
3 *
4 * Low-level IRQ helper macros for iMX-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10 .macro disable_fiq
11 .endm
12#define AITC_NIVECSR 0x40
13 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
14 ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
15 @ Load offset & priority of the highest priority
16 @ interrupt pending.
17 ldr \irqnr, [\irqstat, #AITC_NIVECSR]
18 @ Shift off the priority leaving the offset or
19 @ "interrupt number"
20 mov \irqnr, \irqnr, lsr #16
21 ldr \irqstat, =1 @ dummy compare
22 ldr \base, =0xFFFF // invalid interrupt
23 cmp \irqnr, \base
24 bne 1001f
25 ldr \irqstat, =0
261001:
27 tst \irqstat, #1 @ to make the condition code = TRUE
28 .endm
29
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
new file mode 100644
index 000000000000..adffb6acf42a
--- /dev/null
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -0,0 +1,99 @@
1/*
2 * linux/include/asm-arm/arch-imx/hardware.h
3 *
4 * Copyright (C) 1999 ARM Limited.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24#include "imx-regs.h"
25
26#ifndef __ASSEMBLY__
27# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
28
29# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
30#endif
31
32/*
33 * Memory map
34 */
35
36#define IMX_IO_PHYS 0x00200000
37#define IMX_IO_SIZE 0x00100000
38#define IMX_IO_BASE 0xe0000000
39
40#define IMX_CS0_PHYS 0x10000000
41#define IMX_CS0_SIZE 0x02000000
42#define IMX_CS0_VIRT 0xe8000000
43
44#define IMX_CS1_PHYS 0x12000000
45#define IMX_CS1_SIZE 0x01000000
46#define IMX_CS1_VIRT 0xea000000
47
48#define IMX_CS2_PHYS 0x13000000
49#define IMX_CS2_SIZE 0x01000000
50#define IMX_CS2_VIRT 0xeb000000
51
52#define IMX_CS3_PHYS 0x14000000
53#define IMX_CS3_SIZE 0x01000000
54#define IMX_CS3_VIRT 0xec000000
55
56#define IMX_CS4_PHYS 0x15000000
57#define IMX_CS4_SIZE 0x01000000
58#define IMX_CS4_VIRT 0xed000000
59
60#define IMX_CS5_PHYS 0x16000000
61#define IMX_CS5_SIZE 0x01000000
62#define IMX_CS5_VIRT 0xee000000
63
64#define IMX_FB_VIRT 0xF1000000
65#define IMX_FB_SIZE (256*1024)
66
67/* macro to get at IO space when running virtually */
68#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
69
70#ifndef __ASSEMBLY__
71/*
72 * Handy routine to set GPIO functions
73 */
74extern void imx_gpio_mode( int gpio_mode );
75
76/* get frequencies in Hz */
77extern unsigned int imx_get_system_clk(void);
78extern unsigned int imx_get_mcu_clk(void);
79extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
80extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
81extern unsigned int imx_get_perclk3(void); /* SSI */
82extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
83 /* I2C, DMA */
84#endif
85
86#define MAXIRQNUM 62
87#define MAXFIQNUM 62
88#define MAXSWINUM 62
89
90/*
91 * Use SDRAM for memory
92 */
93#define MEM_SIZE 0x01000000
94
95#ifdef CONFIG_ARCH_MX1ADS
96#include "mx1ads.h"
97#endif
98
99#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
new file mode 100644
index 000000000000..f32c203952cf
--- /dev/null
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -0,0 +1,548 @@
1#ifndef _IMX_REGS_H
2#define _IMX_REGS_H
3/* ------------------------------------------------------------------------
4 * Motorola IMX system registers
5 * ------------------------------------------------------------------------
6 *
7 */
8
9/*
10 * Register BASEs, based on OFFSETs
11 *
12 */
13#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
14#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
15#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
16#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
17#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
18#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
19#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
20#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
21#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
22#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
23#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
24#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
25#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
26#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
27#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
28#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
29#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
30#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
31#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
32#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
33#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
34#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
35#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
36#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
37#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
38#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
39#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
40#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
41
42/* PLL registers */
43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
44#define CSCR_SYSTEM_SEL (1<<16)
45
46#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
47#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
48#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
49#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
50#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
51
52#define CSCR_MPLL_RESTART (1<<21)
53
54/*
55 * GPIO Module and I/O Multiplexer
56 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
57 */
58#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
59#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
60#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
61#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
62#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
63#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
64#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
65#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
66#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
67#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
68#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
69#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
70#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
71#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
72#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
73#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
74#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
75
76#define GPIO_PIN_MASK 0x1f
77#define GPIO_PORT_MASK (0x3 << 5)
78
79#define GPIO_PORTA (0<<5)
80#define GPIO_PORTB (1<<5)
81#define GPIO_PORTC (2<<5)
82#define GPIO_PORTD (3<<5)
83
84#define GPIO_OUT (1<<7)
85#define GPIO_IN (0<<7)
86#define GPIO_PUEN (1<<8)
87
88#define GPIO_PF (0<<9)
89#define GPIO_AF (1<<9)
90
91#define GPIO_OCR_MASK (3<<10)
92#define GPIO_AIN (0<<10)
93#define GPIO_BIN (1<<10)
94#define GPIO_CIN (2<<10)
95#define GPIO_GPIO (3<<10)
96
97#define GPIO_AOUT (1<<12)
98#define GPIO_BOUT (1<<13)
99
100/* assignements for GPIO alternate/primary functions */
101
102/* FIXME: This list is not completed. The correct directions are
103 * missing on some (many) pins
104 */
105#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
106#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
107#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
108#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
109#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
110#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
111#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
112#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
113#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
114#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
115#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
116#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
117#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
118#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
119#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
120#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
121#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
122#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
123#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
124#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
125#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
126#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
127#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
128#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
129#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
130#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
131#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
132#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
133#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
134#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
135#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
136#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
137#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
138#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
139#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
140#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
141#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
142#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
143#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
144#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
145#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
146#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
147#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
148#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
149#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
150#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
151#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
152#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
153#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
154#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
155#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
156#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
157#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
158#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
159#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
160#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
161#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
162#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
163#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
164#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
165#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
166#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
167#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
168#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
169#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
170#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
171#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
172#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
173#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
174#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
175#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
176#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
177#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
178#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
179#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
180#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
181#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
182#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
183#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
184#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
185#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
186#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
187#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
188#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
189#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
190#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
191#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
192#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
193#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
194#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
195#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
196#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
197#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
198#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
199#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
200#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
201#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
202#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
203#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
204#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
205#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
206#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
207#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
208#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
209#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
210#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
211#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
212#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
213#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
214#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
215#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
216#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
217#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
218#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
219#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
220#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
221#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
222#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
223#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
224#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
225#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
226#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
227#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
228#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
229
230/*
231 * DMA Controller
232 */
233#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
234#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
235#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
236#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
237#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
238#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
239#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
240#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
241#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
242#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
243#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
244#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
245#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
246#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
247#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
248#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
249#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
250#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
251#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
252#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
253#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
254#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
255
256#define DCR_DRST (1<<1)
257#define DCR_DEN (1<<0)
258#define DBTOCR_EN (1<<15)
259#define DBTOCR_CNT(x) ((x) & 0x7fff )
260#define CNTR_CNT(x) ((x) & 0xffffff )
261#define CCR_DMOD_LINEAR ( 0x0 << 12 )
262#define CCR_DMOD_2D ( 0x1 << 12 )
263#define CCR_DMOD_FIFO ( 0x2 << 12 )
264#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
265#define CCR_SMOD_LINEAR ( 0x0 << 10 )
266#define CCR_SMOD_2D ( 0x1 << 10 )
267#define CCR_SMOD_FIFO ( 0x2 << 10 )
268#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
269#define CCR_MDIR_DEC (1<<9)
270#define CCR_MSEL_B (1<<8)
271#define CCR_DSIZ_32 ( 0x0 << 6 )
272#define CCR_DSIZ_8 ( 0x1 << 6 )
273#define CCR_DSIZ_16 ( 0x2 << 6 )
274#define CCR_SSIZ_32 ( 0x0 << 4 )
275#define CCR_SSIZ_8 ( 0x1 << 4 )
276#define CCR_SSIZ_16 ( 0x2 << 4 )
277#define CCR_REN (1<<3)
278#define CCR_RPT (1<<2)
279#define CCR_FRC (1<<1)
280#define CCR_CEN (1<<0)
281#define RTOR_EN (1<<15)
282#define RTOR_CLK (1<<14)
283#define RTOR_PSC (1<<13)
284
285/*
286 * Interrupt controller
287 */
288
289#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00)
290#define INTCNTL_FIAD (1<<19)
291#define INTCNTL_NIAD (1<<20)
292
293#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04)
294#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08)
295#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c)
296#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10)
297#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14)
298
299/*
300 * General purpose timers
301 */
302#define IMX_TCTL(x) __REG( 0x00 + (x))
303#define TCTL_SWR (1<<15)
304#define TCTL_FRR (1<<8)
305#define TCTL_CAP_RIS (1<<6)
306#define TCTL_CAP_FAL (2<<6)
307#define TCTL_CAP_RIS_FAL (3<<6)
308#define TCTL_OM (1<<5)
309#define TCTL_IRQEN (1<<4)
310#define TCTL_CLK_PCLK1 (1<<1)
311#define TCTL_CLK_PCLK1_16 (2<<1)
312#define TCTL_CLK_TIN (3<<1)
313#define TCTL_CLK_32 (4<<1)
314#define TCTL_TEN (1<<0)
315
316#define IMX_TPRER(x) __REG( 0x04 + (x))
317#define IMX_TCMP(x) __REG( 0x08 + (x))
318#define IMX_TCR(x) __REG( 0x0C + (x))
319#define IMX_TCN(x) __REG( 0x10 + (x))
320#define IMX_TSTAT(x) __REG( 0x14 + (x))
321#define TSTAT_CAPT (1<<1)
322#define TSTAT_COMP (1<<0)
323
324/*
325 * LCD Controller
326 */
327
328#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
329
330#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
331#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
332#define SIZE_YMAX(y) ( (y) & 0x1ff )
333
334#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
335#define VPW_VPW(x) ( (x) & 0x3ff )
336
337#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
338#define CPOS_CC1 (1<<31)
339#define CPOS_CC0 (1<<30)
340#define CPOS_OP (1<<28)
341#define CPOS_CXP(x) (((x) & 3ff) << 16)
342#define CPOS_CYP(y) ((y) & 0x1ff)
343
344#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
345#define LCWHB_BK_EN (1<<31)
346#define LCWHB_CW(w) (((w) & 0x1f) << 24)
347#define LCWHB_CH(h) (((h) & 0x1f) << 16)
348#define LCWHB_BD(x) ((x) & 0xff)
349
350#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
351#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
352#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
353#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
354
355#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
356#define PCR_TFT (1<<31)
357#define PCR_COLOR (1<<30)
358#define PCR_PBSIZ_1 (0<<28)
359#define PCR_PBSIZ_2 (1<<28)
360#define PCR_PBSIZ_4 (2<<28)
361#define PCR_PBSIZ_8 (3<<28)
362#define PCR_BPIX_1 (0<<25)
363#define PCR_BPIX_2 (1<<25)
364#define PCR_BPIX_4 (2<<25)
365#define PCR_BPIX_8 (3<<25)
366#define PCR_BPIX_12 (4<<25)
367#define PCR_BPIX_16 (4<<25)
368#define PCR_PIXPOL (1<<24)
369#define PCR_FLMPOL (1<<23)
370#define PCR_LPPOL (1<<22)
371#define PCR_CLKPOL (1<<21)
372#define PCR_OEPOL (1<<20)
373#define PCR_SCLKIDLE (1<<19)
374#define PCR_END_SEL (1<<18)
375#define PCR_END_BYTE_SWAP (1<<17)
376#define PCR_REV_VS (1<<16)
377#define PCR_ACD_SEL (1<<15)
378#define PCR_ACD(x) (((x) & 0x7f) << 8)
379#define PCR_SCLK_SEL (1<<7)
380#define PCR_SHARP (1<<6)
381#define PCR_PCD(x) ((x) & 0x3f)
382
383#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
384#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
385#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
386#define HCR_H_WAIT_2(x) ((x) & 0xff)
387
388#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
389#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
390#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
391#define VCR_V_WAIT_2(x) ((x) & 0xff)
392
393#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
394#define POS_POS(x) ((x) & 1f)
395
396#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
397#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
398#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
399#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
400#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
401#define LSCR1_GRAY1(x) (((x) & 0xf))
402
403#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
404#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
405#define PWMR_LDMSK (1<<15)
406#define PWMR_SCR1 (1<<10)
407#define PWMR_SCR0 (1<<9)
408#define PWMR_CC_EN (1<<8)
409#define PWMR_PW(x) ((x) & 0xff)
410
411#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
412#define DMACR_BURST (1<<31)
413#define DMACR_HM(x) (((x) & 0xf) << 16)
414#define DMACR_TM(x) ((x) &0xf)
415
416#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
417#define RMCR_LCDC_EN (1<<1)
418#define RMCR_SELF_REF (1<<0)
419
420#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
421#define LCDICR_INT_SYN (1<<2)
422#define LCDICR_INT_CON (1)
423
424#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
425#define LCDISR_UDR_ERR (1<<3)
426#define LCDISR_ERR_RES (1<<2)
427#define LCDISR_EOF (1<<1)
428#define LCDISR_BOF (1<<0)
429
430/*
431 * UART Module. Takes the UART base address as argument
432 */
433#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
434#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
435#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
436#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
437#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
438#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
439#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
440#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
441#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
442#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
443#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
444#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
445#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
446#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
447#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
448#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
449#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
450#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
451#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
452#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
453#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
454#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
455#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
456
457/* UART Control Register Bit Fields.*/
458#define URXD_CHARRDY (1<<15)
459#define URXD_ERR (1<<14)
460#define URXD_OVRRUN (1<<13)
461#define URXD_FRMERR (1<<12)
462#define URXD_BRK (1<<11)
463#define URXD_PRERR (1<<10)
464#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
465#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
466#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
467#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
468#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
469#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
470#define UCR1_IREN (1<<7) /* Infrared interface enable */
471#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
472#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
473#define UCR1_SNDBRK (1<<4) /* Send break */
474#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
475#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
476#define UCR1_DOZE (1<<1) /* Doze */
477#define UCR1_UARTEN (1<<0) /* UART enabled */
478#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
479#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
480#define UCR2_CTSC (1<<13) /* CTS pin control */
481#define UCR2_CTS (1<<12) /* Clear to send */
482#define UCR2_ESCEN (1<<11) /* Escape enable */
483#define UCR2_PREN (1<<8) /* Parity enable */
484#define UCR2_PROE (1<<7) /* Parity odd/even */
485#define UCR2_STPB (1<<6) /* Stop */
486#define UCR2_WS (1<<5) /* Word size */
487#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
488#define UCR2_TXEN (1<<2) /* Transmitter enabled */
489#define UCR2_RXEN (1<<1) /* Receiver enabled */
490#define UCR2_SRST (1<<0) /* SW reset */
491#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
492#define UCR3_PARERREN (1<<12) /* Parity enable */
493#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
494#define UCR3_DSR (1<<10) /* Data set ready */
495#define UCR3_DCD (1<<9) /* Data carrier detect */
496#define UCR3_RI (1<<8) /* Ring indicator */
497#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
498#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
499#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
500#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
501#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
502#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
503#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
504#define UCR3_BPEN (1<<0) /* Preset registers enable */
505#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
506#define UCR4_INVR (1<<9) /* Inverted infrared reception */
507#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
508#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
509#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
510#define UCR4_IRSC (1<<5) /* IR special case */
511#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
512#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
513#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
514#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
515#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
516#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
517#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
518#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
519#define USR1_RTSS (1<<14) /* RTS pin status */
520#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
521#define USR1_RTSD (1<<12) /* RTS delta */
522#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
523#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
524#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
525#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
526#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
527#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
528#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
529#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
530#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
531#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
532#define USR2_IDLE (1<<12) /* Idle condition */
533#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
534#define USR2_WAKE (1<<7) /* Wake */
535#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
536#define USR2_TXDC (1<<3) /* Transmitter complete */
537#define USR2_BRCD (1<<2) /* Break condition */
538#define USR2_ORE (1<<1) /* Overrun error */
539#define USR2_RDR (1<<0) /* Recv data ready */
540#define UTS_FRCPERR (1<<13) /* Force parity error */
541#define UTS_LOOP (1<<12) /* Loop tx and rx */
542#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
543#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
544#define UTS_TXFULL (1<<4) /* TxFIFO full */
545#define UTS_RXFULL (1<<3) /* RxFIFO full */
546#define UTS_SOFTRST (1<<0) /* Software reset */
547
548#endif // _IMX_REGS_H
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
new file mode 100644
index 000000000000..28a4cca6a4cb
--- /dev/null
+++ b/include/asm-arm/arch-imx/io.h
@@ -0,0 +1,28 @@
1/*
2 * linux/include/asm-arm/arch-imxads/io.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#define IO_SPACE_LIMIT 0xffffffff
24
25#define __io(a) ((void __iomem *)(a))
26#define __mem_pci(a) (a)
27
28#endif
diff --git a/include/asm-arm/arch-imx/irq.h b/include/asm-arm/arch-imx/irq.h
new file mode 100644
index 000000000000..545e065d2325
--- /dev/null
+++ b/include/asm-arm/arch-imx/irq.h
@@ -0,0 +1,20 @@
1/*
2 * linux/include/asm-arm/arch-imxads/irq.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define fixup_irq(i) (i)
diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h
new file mode 100644
index 000000000000..238197cfb9d9
--- /dev/null
+++ b/include/asm-arm/arch-imx/irqs.h
@@ -0,0 +1,116 @@
1/*
2 * linux/include/asm-arm/arch-imxads/irqs.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ARM_IRQS_H__
23#define __ARM_IRQS_H__
24
25/* Use the imx definitions */
26#include <asm/arch/hardware.h>
27
28/*
29 * IMX Interrupt numbers
30 *
31 */
32#define INT_SOFTINT 0
33#define CSI_INT 6
34#define DSPA_MAC_INT 7
35#define DSPA_INT 8
36#define COMP_INT 9
37#define MSHC_XINT 10
38#define GPIO_INT_PORTA 11
39#define GPIO_INT_PORTB 12
40#define GPIO_INT_PORTC 13
41#define LCDC_INT 14
42#define SIM_INT 15
43#define SIM_DATA_INT 16
44#define RTC_INT 17
45#define RTC_SAMINT 18
46#define UART2_MINT_PFERR 19
47#define UART2_MINT_RTS 20
48#define UART2_MINT_DTR 21
49#define UART2_MINT_UARTC 22
50#define UART2_MINT_TX 23
51#define UART2_MINT_RX 24
52#define UART1_MINT_PFERR 25
53#define UART1_MINT_RTS 26
54#define UART1_MINT_DTR 27
55#define UART1_MINT_UARTC 28
56#define UART1_MINT_TX 29
57#define UART1_MINT_RX 30
58#define VOICE_DAC_INT 31
59#define VOICE_ADC_INT 32
60#define PEN_DATA_INT 33
61#define PWM_INT 34
62#define SDHC_INT 35
63#define I2C_INT 39
64#define CSPI_INT 41
65#define SSI_TX_INT 42
66#define SSI_TX_ERR_INT 43
67#define SSI_RX_INT 44
68#define SSI_RX_ERR_INT 45
69#define TOUCH_INT 46
70#define USBD_INT0 47
71#define USBD_INT1 48
72#define USBD_INT2 49
73#define USBD_INT3 50
74#define USBD_INT4 51
75#define USBD_INT5 52
76#define USBD_INT6 53
77#define BTSYS_INT 55
78#define BTTIM_INT 56
79#define BTWUI_INT 57
80#define TIM2_INT 58
81#define TIM1_INT 59
82#define DMA_ERR 60
83#define DMA_INT 61
84#define GPIO_INT_PORTD 62
85
86#define IMX_IRQS (64)
87
88/* note: the IMX has four gpio ports (A-D), but only
89 * the following pins are connected to the outside
90 * world:
91 *
92 * PORT A: bits 0-31
93 * PORT B: bits 8-31
94 * PORT C: bits 3-17
95 * PORT D: bits 6-31
96 *
97 * We map these interrupts straight on. As a result we have
98 * several holes in the interrupt mapping. We do this for two
99 * reasons:
100 * - mapping the interrupts without holes would get
101 * far more complicated
102 * - Motorola could well decide to bring some processor
103 * with more pins connected
104 */
105
106#define IRQ_GPIOA(x) (IMX_IRQS + x)
107#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
108#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
109#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
110
111/* decode irq number to use with IMR(x), ISR(x) and friends */
112#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
113
114#define NR_IRQS (IRQ_GPIOD(32) + 1)
115#define IRQ_GPIO(x)
116#endif
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
new file mode 100644
index 000000000000..116a91fa14f1
--- /dev/null
+++ b/include/asm-arm/arch-imx/memory.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/arch-imx/memory.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_MMU_H
22#define __ASM_ARCH_MMU_H
23
24#define PHYS_OFFSET (0x08000000UL)
25
26/*
27 * Virtual view <-> DMA view memory address translations
28 * virt_to_bus: Used to translate the virtual address to an
29 * address suitable to be passed to set_dma_addr
30 * bus_to_virt: Used to convert an address for DMA operations
31 * to an address that the kernel can use.
32 */
33#define __virt_to_bus__is_a_macro
34#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET)
35#define __bus_to_virt__is_a_macro
36#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET)
37
38#endif
diff --git a/include/asm-arm/arch-imx/mx1ads.h b/include/asm-arm/arch-imx/mx1ads.h
new file mode 100644
index 000000000000..d90fa4b49ce1
--- /dev/null
+++ b/include/asm-arm/arch-imx/mx1ads.h
@@ -0,0 +1,36 @@
1/*
2 * linux/include/asm-arm/arch-imx/mx1ads.h
3 *
4 * Copyright (C) 2004 Robert Schwebel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#ifndef __ASM_ARCH_MX1ADS_H
23#define __ASM_ARCH_MX1ADS_H
24
25/* ------------------------------------------------------------------------ */
26/* Memory Map for the M9328MX1ADS (MX1ADS) Board */
27/* ------------------------------------------------------------------------ */
28
29#define MX1ADS_FLASH_PHYS 0x10000000
30#define MX1ADS_FLASH_SIZE (16*1024*1024)
31
32#define IMX_FB_PHYS (0x0C000000 - 0x40000)
33
34#define CLK32 32000
35
36#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/include/asm-arm/arch-imx/param.h b/include/asm-arm/arch-imx/param.h
new file mode 100644
index 000000000000..7c724f03333e
--- /dev/null
+++ b/include/asm-arm/arch-imx/param.h
@@ -0,0 +1,19 @@
1/*
2 * linux/include/asm-arm/arch-imx/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-imx/system.h b/include/asm-arm/arch-imx/system.h
new file mode 100644
index 000000000000..c645fe9afb9d
--- /dev/null
+++ b/include/asm-arm/arch-imx/system.h
@@ -0,0 +1,40 @@
1/*
2 * linux/include/asm-arm/arch-imxads/system.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static void
25arch_idle(void)
26{
27 /*
28 * This should do all the clock switching
29 * and wait for interrupt tricks
30 */
31 cpu_do_idle();
32}
33
34static inline void
35arch_reset(char mode)
36{
37 cpu_reset(0);
38}
39
40#endif
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
new file mode 100644
index 000000000000..d65ab3cd5d5d
--- /dev/null
+++ b/include/asm-arm/arch-imx/timex.h
@@ -0,0 +1,27 @@
1/*
2 * linux/include/asm-arm/imx/timex.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_TIMEX_H
22#define __ASM_ARCH_TIMEX_H
23
24#include <asm/arch/hardware.h>
25#define CLOCK_TICK_RATE (CLK32)
26
27#endif
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h
new file mode 100644
index 000000000000..096077f2750b
--- /dev/null
+++ b/include/asm-arm/arch-imx/uncompress.h
@@ -0,0 +1,78 @@
1/*
2 * linux/include/asm-arm/arch-imxads/uncompress.h
3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
25
26#define UART1_BASE 0x206000
27#define UART2_BASE 0x207000
28#define USR2 0x98
29#define USR2_TXFE (1<<14)
30#define TXR 0x40
31#define UCR1 0x80
32#define UCR1_UARTEN 1
33
34/*
35 * The following code assumes the serial port has already been
36 * initialized by the bootloader. We search for the first enabled
37 * port in the most probable order. If you didn't setup a port in
38 * your bootloader then nothing will appear (which might be desired).
39 *
40 * This does not append a newline
41 */
42static void
43putstr(const char *s)
44{
45 unsigned long serial_port;
46
47 do {
48 serial_port = UART1_BASE;
49 if ( UART(UCR1) & UCR1_UARTEN )
50 break;
51 serial_port = UART2_BASE;
52 if ( UART(UCR1) & UCR1_UARTEN )
53 break;
54 return;
55 } while(0);
56
57 while (*s) {
58 while ( !(UART(USR2) & USR2_TXFE) )
59 barrier();
60
61 UART(TXR) = *s;
62
63 if (*s == '\n') {
64 while ( !(UART(USR2) & USR2_TXFE) )
65 barrier();
66
67 UART(TXR) = '\r';
68 }
69 s++;
70 }
71}
72
73/*
74 * nothing to do
75 */
76#define arch_decomp_setup()
77
78#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h
new file mode 100644
index 000000000000..252038f48163
--- /dev/null
+++ b/include/asm-arm/arch-imx/vmalloc.h
@@ -0,0 +1,32 @@
1/*
2 * linux/include/asm-arm/arch-imx/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Just any arbitrary offset to the start of the vmalloc VM area: the
23 * current 8MB value just means that there will be a 8MB "hole" after the
24 * physical memory until the kernel virtual memory starts. That means that
25 * any out-of-bounds memory accesses will hopefully be caught.
26 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
27 * area for the same reason. ;)
28 */
29#define VMALLOC_OFFSET (8*1024*1024)
30#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
31#define VMALLOC_VMADDR(x) ((unsigned long)(x))
32#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 18:03:04 -0500