diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-imx/imx-regs.h | |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-arm/arch-imx/imx-regs.h')
| -rw-r--r-- | include/asm-arm/arch-imx/imx-regs.h | 548 |
1 files changed, 548 insertions, 0 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h new file mode 100644 index 000000000000..f32c203952cf --- /dev/null +++ b/include/asm-arm/arch-imx/imx-regs.h | |||
| @@ -0,0 +1,548 @@ | |||
| 1 | #ifndef _IMX_REGS_H | ||
| 2 | #define _IMX_REGS_H | ||
| 3 | /* ------------------------------------------------------------------------ | ||
| 4 | * Motorola IMX system registers | ||
| 5 | * ------------------------------------------------------------------------ | ||
| 6 | * | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Register BASEs, based on OFFSETs | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) | ||
| 14 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) | ||
| 15 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) | ||
| 16 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) | ||
| 17 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) | ||
| 18 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) | ||
| 19 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) | ||
| 20 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) | ||
| 21 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) | ||
| 22 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) | ||
| 23 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) | ||
| 24 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) | ||
| 25 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) | ||
| 26 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) | ||
| 27 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) | ||
| 28 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) | ||
| 29 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) | ||
| 30 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) | ||
| 31 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) | ||
| 32 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) | ||
| 33 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) | ||
| 34 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) | ||
| 35 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) | ||
| 36 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) | ||
| 37 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) | ||
| 38 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) | ||
| 39 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) | ||
| 40 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) | ||
| 41 | |||
| 42 | /* PLL registers */ | ||
| 43 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ | ||
| 44 | #define CSCR_SYSTEM_SEL (1<<16) | ||
| 45 | |||
| 46 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ | ||
| 47 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ | ||
| 48 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ | ||
| 49 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ | ||
| 50 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ | ||
| 51 | |||
| 52 | #define CSCR_MPLL_RESTART (1<<21) | ||
| 53 | |||
| 54 | /* | ||
| 55 | * GPIO Module and I/O Multiplexer | ||
| 56 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 57 | */ | ||
| 58 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) | ||
| 59 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) | ||
| 60 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) | ||
| 61 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) | ||
| 62 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) | ||
| 63 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) | ||
| 64 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) | ||
| 65 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) | ||
| 66 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) | ||
| 67 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) | ||
| 68 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) | ||
| 69 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) | ||
| 70 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) | ||
| 71 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) | ||
| 72 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) | ||
| 73 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) | ||
| 74 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) | ||
| 75 | |||
| 76 | #define GPIO_PIN_MASK 0x1f | ||
| 77 | #define GPIO_PORT_MASK (0x3 << 5) | ||
| 78 | |||
| 79 | #define GPIO_PORTA (0<<5) | ||
| 80 | #define GPIO_PORTB (1<<5) | ||
| 81 | #define GPIO_PORTC (2<<5) | ||
| 82 | #define GPIO_PORTD (3<<5) | ||
| 83 | |||
| 84 | #define GPIO_OUT (1<<7) | ||
| 85 | #define GPIO_IN (0<<7) | ||
| 86 | #define GPIO_PUEN (1<<8) | ||
| 87 | |||
| 88 | #define GPIO_PF (0<<9) | ||
| 89 | #define GPIO_AF (1<<9) | ||
| 90 | |||
| 91 | #define GPIO_OCR_MASK (3<<10) | ||
| 92 | #define GPIO_AIN (0<<10) | ||
| 93 | #define GPIO_BIN (1<<10) | ||
| 94 | #define GPIO_CIN (2<<10) | ||
| 95 | #define GPIO_GPIO (3<<10) | ||
| 96 | |||
| 97 | #define GPIO_AOUT (1<<12) | ||
| 98 | #define GPIO_BOUT (1<<13) | ||
| 99 | |||
| 100 | /* assignements for GPIO alternate/primary functions */ | ||
| 101 | |||
| 102 | /* FIXME: This list is not completed. The correct directions are | ||
| 103 | * missing on some (many) pins | ||
| 104 | */ | ||
| 105 | #define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) | ||
| 106 | #define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) | ||
| 107 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) | ||
| 108 | #define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) | ||
| 109 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) | ||
| 110 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) | ||
| 111 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) | ||
| 112 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) | ||
| 113 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) | ||
| 114 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) | ||
| 115 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) | ||
| 116 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) | ||
| 117 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) | ||
| 118 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) | ||
| 119 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) | ||
| 120 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) | ||
| 121 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) | ||
| 122 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) | ||
| 123 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) | ||
| 124 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) | ||
| 125 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) | ||
| 126 | #define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) | ||
| 127 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) | ||
| 128 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) | ||
| 129 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) | ||
| 130 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) | ||
| 131 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) | ||
| 132 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) | ||
| 133 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) | ||
| 134 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) | ||
| 135 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) | ||
| 136 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) | ||
| 137 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) | ||
| 138 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) | ||
| 139 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) | ||
| 140 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) | ||
| 141 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) | ||
| 142 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) | ||
| 143 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) | ||
| 144 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) | ||
| 145 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) | ||
| 146 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) | ||
| 147 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) | ||
| 148 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) | ||
| 149 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) | ||
| 150 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) | ||
| 151 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) | ||
| 152 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) | ||
| 153 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) | ||
| 154 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) | ||
| 155 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) | ||
| 156 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) | ||
| 157 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) | ||
| 158 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) | ||
| 159 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) | ||
| 160 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) | ||
| 161 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) | ||
| 162 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) | ||
| 163 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) | ||
| 164 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) | ||
| 165 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) | ||
| 166 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) | ||
| 167 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) | ||
| 168 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) | ||
| 169 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) | ||
| 170 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) | ||
| 171 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) | ||
| 172 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) | ||
| 173 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) | ||
| 174 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) | ||
| 175 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) | ||
| 176 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) | ||
| 177 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) | ||
| 178 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) | ||
| 179 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) | ||
| 180 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) | ||
| 181 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) | ||
| 182 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) | ||
| 183 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) | ||
| 184 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) | ||
| 185 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) | ||
| 186 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) | ||
| 187 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) | ||
| 188 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) | ||
| 189 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) | ||
| 190 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) | ||
| 191 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) | ||
| 192 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) | ||
| 193 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) | ||
| 194 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) | ||
| 195 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) | ||
| 196 | #define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) | ||
| 197 | #define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) | ||
| 198 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) | ||
| 199 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) | ||
| 200 | #define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) | ||
| 201 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) | ||
| 202 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) | ||
| 203 | #define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) | ||
| 204 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) | ||
| 205 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) | ||
| 206 | #define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) | ||
| 207 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) | ||
| 208 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) | ||
| 209 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) | ||
| 210 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) | ||
| 211 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) | ||
| 212 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) | ||
| 213 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) | ||
| 214 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) | ||
| 215 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) | ||
| 216 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) | ||
| 217 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) | ||
| 218 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) | ||
| 219 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) | ||
| 220 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) | ||
| 221 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) | ||
| 222 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) | ||
| 223 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) | ||
| 224 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) | ||
| 225 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) | ||
| 226 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) | ||
| 227 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) | ||
| 228 | #define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) | ||
| 229 | |||
| 230 | /* | ||
| 231 | * DMA Controller | ||
| 232 | */ | ||
| 233 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ | ||
| 234 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ | ||
| 235 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ | ||
| 236 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ | ||
| 237 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ | ||
| 238 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ | ||
| 239 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ | ||
| 240 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ | ||
| 241 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ | ||
| 242 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ | ||
| 243 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ | ||
| 244 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ | ||
| 245 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ | ||
| 246 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ | ||
| 247 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ | ||
| 248 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ | ||
| 249 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ | ||
| 250 | #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ | ||
| 251 | #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ | ||
| 252 | #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ | ||
| 253 | #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ | ||
| 254 | #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ | ||
| 255 | |||
| 256 | #define DCR_DRST (1<<1) | ||
| 257 | #define DCR_DEN (1<<0) | ||
| 258 | #define DBTOCR_EN (1<<15) | ||
| 259 | #define DBTOCR_CNT(x) ((x) & 0x7fff ) | ||
| 260 | #define CNTR_CNT(x) ((x) & 0xffffff ) | ||
| 261 | #define CCR_DMOD_LINEAR ( 0x0 << 12 ) | ||
| 262 | #define CCR_DMOD_2D ( 0x1 << 12 ) | ||
| 263 | #define CCR_DMOD_FIFO ( 0x2 << 12 ) | ||
| 264 | #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) | ||
| 265 | #define CCR_SMOD_LINEAR ( 0x0 << 10 ) | ||
| 266 | #define CCR_SMOD_2D ( 0x1 << 10 ) | ||
| 267 | #define CCR_SMOD_FIFO ( 0x2 << 10 ) | ||
| 268 | #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) | ||
| 269 | #define CCR_MDIR_DEC (1<<9) | ||
| 270 | #define CCR_MSEL_B (1<<8) | ||
| 271 | #define CCR_DSIZ_32 ( 0x0 << 6 ) | ||
| 272 | #define CCR_DSIZ_8 ( 0x1 << 6 ) | ||
| 273 | #define CCR_DSIZ_16 ( 0x2 << 6 ) | ||
| 274 | #define CCR_SSIZ_32 ( 0x0 << 4 ) | ||
| 275 | #define CCR_SSIZ_8 ( 0x1 << 4 ) | ||
| 276 | #define CCR_SSIZ_16 ( 0x2 << 4 ) | ||
| 277 | #define CCR_REN (1<<3) | ||
| 278 | #define CCR_RPT (1<<2) | ||
| 279 | #define CCR_FRC (1<<1) | ||
| 280 | #define CCR_CEN (1<<0) | ||
| 281 | #define RTOR_EN (1<<15) | ||
| 282 | #define RTOR_CLK (1<<14) | ||
| 283 | #define RTOR_PSC (1<<13) | ||
| 284 | |||
| 285 | /* | ||
| 286 | * Interrupt controller | ||
| 287 | */ | ||
| 288 | |||
| 289 | #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) | ||
| 290 | #define INTCNTL_FIAD (1<<19) | ||
| 291 | #define INTCNTL_NIAD (1<<20) | ||
| 292 | |||
| 293 | #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) | ||
| 294 | #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) | ||
| 295 | #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) | ||
| 296 | #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) | ||
| 297 | #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) | ||
| 298 | |||
| 299 | /* | ||
| 300 | * General purpose timers | ||
| 301 | */ | ||
| 302 | #define IMX_TCTL(x) __REG( 0x00 + (x)) | ||
| 303 | #define TCTL_SWR (1<<15) | ||
| 304 | #define TCTL_FRR (1<<8) | ||
| 305 | #define TCTL_CAP_RIS (1<<6) | ||
| 306 | #define TCTL_CAP_FAL (2<<6) | ||
| 307 | #define TCTL_CAP_RIS_FAL (3<<6) | ||
| 308 | #define TCTL_OM (1<<5) | ||
| 309 | #define TCTL_IRQEN (1<<4) | ||
| 310 | #define TCTL_CLK_PCLK1 (1<<1) | ||
| 311 | #define TCTL_CLK_PCLK1_16 (2<<1) | ||
| 312 | #define TCTL_CLK_TIN (3<<1) | ||
| 313 | #define TCTL_CLK_32 (4<<1) | ||
| 314 | #define TCTL_TEN (1<<0) | ||
| 315 | |||
| 316 | #define IMX_TPRER(x) __REG( 0x04 + (x)) | ||
| 317 | #define IMX_TCMP(x) __REG( 0x08 + (x)) | ||
| 318 | #define IMX_TCR(x) __REG( 0x0C + (x)) | ||
| 319 | #define IMX_TCN(x) __REG( 0x10 + (x)) | ||
| 320 | #define IMX_TSTAT(x) __REG( 0x14 + (x)) | ||
| 321 | #define TSTAT_CAPT (1<<1) | ||
| 322 | #define TSTAT_COMP (1<<0) | ||
| 323 | |||
| 324 | /* | ||
| 325 | * LCD Controller | ||
| 326 | */ | ||
| 327 | |||
| 328 | #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) | ||
| 329 | |||
| 330 | #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) | ||
| 331 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | ||
| 332 | #define SIZE_YMAX(y) ( (y) & 0x1ff ) | ||
| 333 | |||
| 334 | #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) | ||
| 335 | #define VPW_VPW(x) ( (x) & 0x3ff ) | ||
| 336 | |||
| 337 | #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) | ||
| 338 | #define CPOS_CC1 (1<<31) | ||
| 339 | #define CPOS_CC0 (1<<30) | ||
| 340 | #define CPOS_OP (1<<28) | ||
| 341 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | ||
| 342 | #define CPOS_CYP(y) ((y) & 0x1ff) | ||
| 343 | |||
| 344 | #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) | ||
| 345 | #define LCWHB_BK_EN (1<<31) | ||
| 346 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | ||
| 347 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | ||
| 348 | #define LCWHB_BD(x) ((x) & 0xff) | ||
| 349 | |||
| 350 | #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) | ||
| 351 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | ||
| 352 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | ||
| 353 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | ||
| 354 | |||
| 355 | #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) | ||
| 356 | #define PCR_TFT (1<<31) | ||
| 357 | #define PCR_COLOR (1<<30) | ||
| 358 | #define PCR_PBSIZ_1 (0<<28) | ||
| 359 | #define PCR_PBSIZ_2 (1<<28) | ||
| 360 | #define PCR_PBSIZ_4 (2<<28) | ||
| 361 | #define PCR_PBSIZ_8 (3<<28) | ||
| 362 | #define PCR_BPIX_1 (0<<25) | ||
| 363 | #define PCR_BPIX_2 (1<<25) | ||
| 364 | #define PCR_BPIX_4 (2<<25) | ||
| 365 | #define PCR_BPIX_8 (3<<25) | ||
| 366 | #define PCR_BPIX_12 (4<<25) | ||
| 367 | #define PCR_BPIX_16 (4<<25) | ||
| 368 | #define PCR_PIXPOL (1<<24) | ||
| 369 | #define PCR_FLMPOL (1<<23) | ||
| 370 | #define PCR_LPPOL (1<<22) | ||
| 371 | #define PCR_CLKPOL (1<<21) | ||
| 372 | #define PCR_OEPOL (1<<20) | ||
| 373 | #define PCR_SCLKIDLE (1<<19) | ||
| 374 | #define PCR_END_SEL (1<<18) | ||
| 375 | #define PCR_END_BYTE_SWAP (1<<17) | ||
| 376 | #define PCR_REV_VS (1<<16) | ||
| 377 | #define PCR_ACD_SEL (1<<15) | ||
| 378 | #define PCR_ACD(x) (((x) & 0x7f) << 8) | ||
| 379 | #define PCR_SCLK_SEL (1<<7) | ||
| 380 | #define PCR_SHARP (1<<6) | ||
| 381 | #define PCR_PCD(x) ((x) & 0x3f) | ||
| 382 | |||
| 383 | #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) | ||
| 384 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | ||
| 385 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | ||
| 386 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | ||
| 387 | |||
| 388 | #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) | ||
| 389 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | ||
| 390 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | ||
| 391 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | ||
| 392 | |||
| 393 | #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) | ||
| 394 | #define POS_POS(x) ((x) & 1f) | ||
| 395 | |||
| 396 | #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) | ||
| 397 | #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) | ||
| 398 | #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) | ||
| 399 | #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) | ||
| 400 | #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) | ||
| 401 | #define LSCR1_GRAY1(x) (((x) & 0xf)) | ||
| 402 | |||
| 403 | #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) | ||
| 404 | #define PWMR_CLS(x) (((x) & 0x1ff) << 16) | ||
| 405 | #define PWMR_LDMSK (1<<15) | ||
| 406 | #define PWMR_SCR1 (1<<10) | ||
| 407 | #define PWMR_SCR0 (1<<9) | ||
| 408 | #define PWMR_CC_EN (1<<8) | ||
| 409 | #define PWMR_PW(x) ((x) & 0xff) | ||
| 410 | |||
| 411 | #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) | ||
| 412 | #define DMACR_BURST (1<<31) | ||
| 413 | #define DMACR_HM(x) (((x) & 0xf) << 16) | ||
| 414 | #define DMACR_TM(x) ((x) &0xf) | ||
| 415 | |||
| 416 | #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) | ||
| 417 | #define RMCR_LCDC_EN (1<<1) | ||
| 418 | #define RMCR_SELF_REF (1<<0) | ||
| 419 | |||
| 420 | #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) | ||
| 421 | #define LCDICR_INT_SYN (1<<2) | ||
| 422 | #define LCDICR_INT_CON (1) | ||
| 423 | |||
| 424 | #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) | ||
| 425 | #define LCDISR_UDR_ERR (1<<3) | ||
| 426 | #define LCDISR_ERR_RES (1<<2) | ||
| 427 | #define LCDISR_EOF (1<<1) | ||
| 428 | #define LCDISR_BOF (1<<0) | ||
| 429 | |||
| 430 | /* | ||
| 431 | * UART Module. Takes the UART base address as argument | ||
| 432 | */ | ||
| 433 | #define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */ | ||
| 434 | #define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */ | ||
| 435 | #define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */ | ||
| 436 | #define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */ | ||
| 437 | #define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */ | ||
| 438 | #define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */ | ||
| 439 | #define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */ | ||
| 440 | #define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */ | ||
| 441 | #define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */ | ||
| 442 | #define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */ | ||
| 443 | #define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */ | ||
| 444 | #define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */ | ||
| 445 | #define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */ | ||
| 446 | #define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */ | ||
| 447 | #define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */ | ||
| 448 | #define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */ | ||
| 449 | #define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */ | ||
| 450 | #define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */ | ||
| 451 | #define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */ | ||
| 452 | #define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */ | ||
| 453 | #define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */ | ||
| 454 | #define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */ | ||
| 455 | #define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */ | ||
| 456 | |||
| 457 | /* UART Control Register Bit Fields.*/ | ||
| 458 | #define URXD_CHARRDY (1<<15) | ||
| 459 | #define URXD_ERR (1<<14) | ||
| 460 | #define URXD_OVRRUN (1<<13) | ||
| 461 | #define URXD_FRMERR (1<<12) | ||
| 462 | #define URXD_BRK (1<<11) | ||
| 463 | #define URXD_PRERR (1<<10) | ||
| 464 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ | ||
| 465 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | ||
| 466 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | ||
| 467 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | ||
| 468 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | ||
| 469 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | ||
| 470 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | ||
| 471 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | ||
| 472 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | ||
| 473 | #define UCR1_SNDBRK (1<<4) /* Send break */ | ||
| 474 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | ||
| 475 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | ||
| 476 | #define UCR1_DOZE (1<<1) /* Doze */ | ||
| 477 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | ||
| 478 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | ||
| 479 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | ||
| 480 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | ||
| 481 | #define UCR2_CTS (1<<12) /* Clear to send */ | ||
| 482 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | ||
| 483 | #define UCR2_PREN (1<<8) /* Parity enable */ | ||
| 484 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | ||
| 485 | #define UCR2_STPB (1<<6) /* Stop */ | ||
| 486 | #define UCR2_WS (1<<5) /* Word size */ | ||
| 487 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | ||
| 488 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | ||
| 489 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | ||
| 490 | #define UCR2_SRST (1<<0) /* SW reset */ | ||
| 491 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | ||
| 492 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | ||
| 493 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | ||
| 494 | #define UCR3_DSR (1<<10) /* Data set ready */ | ||
| 495 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | ||
| 496 | #define UCR3_RI (1<<8) /* Ring indicator */ | ||
| 497 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | ||
| 498 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | ||
| 499 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | ||
| 500 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | ||
| 501 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ | ||
| 502 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ | ||
| 503 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | ||
| 504 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | ||
| 505 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ | ||
| 506 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | ||
| 507 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | ||
| 508 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | ||
| 509 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | ||
| 510 | #define UCR4_IRSC (1<<5) /* IR special case */ | ||
| 511 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | ||
| 512 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | ||
| 513 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | ||
| 514 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | ||
| 515 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | ||
| 516 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | ||
| 517 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | ||
| 518 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | ||
| 519 | #define USR1_RTSS (1<<14) /* RTS pin status */ | ||
| 520 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | ||
| 521 | #define USR1_RTSD (1<<12) /* RTS delta */ | ||
| 522 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | ||
| 523 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | ||
| 524 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | ||
| 525 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | ||
| 526 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | ||
| 527 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | ||
| 528 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | ||
| 529 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | ||
| 530 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | ||
| 531 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | ||
| 532 | #define USR2_IDLE (1<<12) /* Idle condition */ | ||
| 533 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | ||
| 534 | #define USR2_WAKE (1<<7) /* Wake */ | ||
| 535 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | ||
| 536 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | ||
| 537 | #define USR2_BRCD (1<<2) /* Break condition */ | ||
| 538 | #define USR2_ORE (1<<1) /* Overrun error */ | ||
| 539 | #define USR2_RDR (1<<0) /* Recv data ready */ | ||
| 540 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | ||
| 541 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | ||
| 542 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | ||
| 543 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | ||
| 544 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | ||
| 545 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | ||
| 546 | #define UTS_SOFTRST (1<<0) /* Software reset */ | ||
| 547 | |||
| 548 | #endif // _IMX_REGS_H | ||