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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-clps711x/hardware.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-clps711x/hardware.h')
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diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
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1/*
2 * linux/include/asm-arm/arch-clps711x/hardware.h
3 *
4 * This file contains the hardware definitions of the Prospector P720T.
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __ASM_ARCH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H
24
25#include <linux/config.h>
26
27#define CLPS7111_VIRT_BASE 0xff000000
28#define CLPS7111_BASE CLPS7111_VIRT_BASE
29
30/*
31 * The physical addresses that the external chip select signals map to is
32 * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
33 * processors. CONFIG_EP72XX_BOOT_ROM is only available if these
34 * processors are in use.
35 */
36#ifndef CONFIG_EP72XX_ROM_BOOT
37#define CS0_PHYS_BASE (0x00000000)
38#define CS1_PHYS_BASE (0x10000000)
39#define CS2_PHYS_BASE (0x20000000)
40#define CS3_PHYS_BASE (0x30000000)
41#define CS4_PHYS_BASE (0x40000000)
42#define CS5_PHYS_BASE (0x50000000)
43#define CS6_PHYS_BASE (0x60000000)
44#define CS7_PHYS_BASE (0x70000000)
45#else
46#define CS0_PHYS_BASE (0x70000000)
47#define CS1_PHYS_BASE (0x60000000)
48#define CS2_PHYS_BASE (0x50000000)
49#define CS3_PHYS_BASE (0x40000000)
50#define CS4_PHYS_BASE (0x30000000)
51#define CS5_PHYS_BASE (0x20000000)
52#define CS6_PHYS_BASE (0x10000000)
53#define CS7_PHYS_BASE (0x00000000)
54#endif
55
56#if defined (CONFIG_ARCH_EP7211)
57
58#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
59#define EP7211_BASE CLPS7111_VIRT_BASE
60#include <asm/hardware/ep7211.h>
61
62#elif defined (CONFIG_ARCH_EP7212)
63
64#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
65#define EP7212_BASE CLPS7111_VIRT_BASE
66#include <asm/hardware/ep7212.h>
67
68#endif
69
70#define SYSPLD_VIRT_BASE 0xfe000000
71#define SYSPLD_BASE SYSPLD_VIRT_BASE
72
73#ifndef __ASSEMBLER__
74
75#define PCIO_BASE IO_BASE
76
77#endif
78
79
80#if defined (CONFIG_ARCH_AUTCPU12)
81
82#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
83#define CS89712_BASE CLPS7111_VIRT_BASE
84
85#include <asm/hardware/clps7111.h>
86#include <asm/hardware/ep7212.h>
87#include <asm/hardware/cs89712.h>
88
89#endif
90
91
92#if defined (CONFIG_ARCH_CDB89712)
93
94#include <asm/hardware/clps7111.h>
95#include <asm/hardware/ep7212.h>
96#include <asm/hardware/cs89712.h>
97
98/* dynamic ioremap() areas */
99#define FLASH_START 0x00000000
100#define FLASH_SIZE 0x800000
101#define FLASH_WIDTH 4
102
103#define SRAM_START 0x60000000
104#define SRAM_SIZE 0xc000
105#define SRAM_WIDTH 4
106
107#define BOOTROM_START 0x70000000
108#define BOOTROM_SIZE 0x80
109#define BOOTROM_WIDTH 4
110
111
112/* static cdb89712_map_io() areas */
113#define REGISTER_START 0x80000000
114#define REGISTER_SIZE 0x4000
115#define REGISTER_BASE 0xff000000
116
117#define ETHER_START 0x20000000
118#define ETHER_SIZE 0x1000
119#define ETHER_BASE 0xfe000000
120
121#endif
122
123
124#if defined (CONFIG_ARCH_EDB7211)
125
126/*
127 * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
128 * and repeat across it. This is the mapping for it.
129 *
130 * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
131 * was cause for much consternation and headscratching. This should probably
132 * be made a compile/run time kernel option.
133 */
134#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
135
136#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
137
138
139/*
140 * The CS8900A ethernet chip has its I/O registers wired to chip select 2
141 * (nCS2). This is the mapping for it.
142 *
143 * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
144 * was cause for much consternation and headscratching. This should probably
145 * be made a compile/run time kernel option.
146 */
147#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
148
149#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
150
151
152/*
153 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
154 * for them.
155 *
156 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
157 * in jumpered boot mode.
158 */
159#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
160#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
161
162#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
163#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
164
165#endif /* CONFIG_ARCH_EDB7211 */
166
167
168/*
169 * Relevant bits in port D, which controls power to the various parts of
170 * the LCD on the EDB7211.
171 */
172#define EDB_PD1_LCD_DC_DC_EN (1<<1)
173#define EDB_PD2_LCDEN (1<<2)
174#define EDB_PD3_LCDBL (1<<3)
175
176
177#if defined (CONFIG_ARCH_CEIVA)
178
179#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
180#define CEIVA_BASE CLPS7111_VIRT_BASE
181
182#include <asm/hardware/clps7111.h>
183#include <asm/hardware/ep7212.h>
184
185
186/*
187 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
188 * for them.
189 *
190 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
191 * in jumpered boot mode.
192 */
193#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
194#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
195
196#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
197#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
198
199#define CEIVA_FLASH_SIZE 0x100000
200#define CEIVA_FLASH_WIDTH 2
201
202#define SRAM_START 0x60000000
203#define SRAM_SIZE 0xc000
204#define SRAM_WIDTH 4
205
206#define BOOTROM_START 0x70000000
207#define BOOTROM_SIZE 0x80
208#define BOOTROM_WIDTH 4
209
210/*
211 * SED1355 LCD controller
212 */
213#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
214#define CEIVA_VIRT_SED1355 (0xfc000000)
215
216/*
217 * Relevant bits in port D, which controls power to the various parts of
218 * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
219 */
220
221// Reset line to SED1355 (must be high to operate)
222#define CEIVA_PD1_LCDRST (1<<1)
223// LCD panel enable (set to one, to enable LCD)
224#define CEIVA_PD4_LCDEN (1<<4)
225// Backlight (set to one, to turn on backlight
226#define CEIVA_PD5_LCDBL (1<<5)
227
228/*
229 * Relevant bits in port B, which report the status of the buttons.
230 */
231
232// White button
233#define CEIVA_PB4_WHT_BTN (1<<4)
234// Black button
235#define CEIVA_PB0_BLK_BTN (1<<0)
236#endif // #if defined (CONFIG_ARCH_CEIVA)
237
238#endif