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authorAndrew Victor <andrew@sanpeople.com>2006-11-30 10:08:49 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-11-30 17:51:39 -0500
commita5c474580b8b7cc8b7b2cca9a2bd27ff5c065e70 (patch)
tree974b871f006a7082ab50148b3d44a117bee32c1a /include/asm-arm/arch-at91rm9200
parent6171de8f57e80873436345a9c7ba8bae800e577b (diff)
[ARM] 3951/1: AT91: Rename user peripheral header files
Most of the AT91RM9200 user peripherals are also integrated into the Atmel SAM9 range of processors. This patch renames the headers from at91rm9200_xx.h to at91_xx.h to indicate they're not at91rm9200-specific. The new SAM9-specific registers and register bits have also been defined. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91rm9200')
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_mci.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_mci.h)24
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_spi.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_spi.h)8
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_ssc.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h)16
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_tc.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_tc.h)6
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_twi.h (renamed from include/asm-arm/arch-at91rm9200/at91rm9200_twi.h)10
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h36
6 files changed, 38 insertions, 62 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h
index f28636d61e39..9a552cb743c0 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
+++ b/include/asm-arm/arch-at91rm9200/at91_mci.h
@@ -1,11 +1,11 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h 2 * include/asm-arm/arch-at91rm9200/at91_mci.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
6 * 6 *
7 * MultiMedia Card Interface (MCI) registers. 7 * MultiMedia Card Interface (MCI) registers.
8 * Based on AT91RM9200 datasheet revision E. 8 * Based on AT91RM9200 datasheet revision F.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_MCI_H 16#ifndef AT91_MCI_H
17#define AT91RM9200_MCI_H 17#define AT91_MCI_H
18 18
19#define AT91_MCI_CR 0x00 /* Control Register */ 19#define AT91_MCI_CR 0x00 /* Control Register */
20#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ 20#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
@@ -25,10 +25,10 @@
25 25
26#define AT91_MCI_MR 0x04 /* Mode Register */ 26#define AT91_MCI_MR 0x04 /* Mode Register */
27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ 27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
28#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ 28#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
29#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ 29#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
30#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ 30#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
31#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ 31#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
32 32
33#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ 33#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
34#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ 34#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
@@ -43,8 +43,8 @@
43#define AT91_MCI_DTOMUL_1M (7 << 4) 43#define AT91_MCI_DTOMUL_1M (7 << 4)
44 44
45#define AT91_MCI_SDCR 0x0c /* SD Card Register */ 45#define AT91_MCI_SDCR 0x0c /* SD Card Register */
46#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ 46#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
47#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ 47#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
48 48
49#define AT91_MCI_ARGR 0x10 /* Argument Register */ 49#define AT91_MCI_ARGR 0x10 /* Argument Register */
50 50
@@ -78,18 +78,20 @@
78 78
79#define AT91_MCI_SR 0x40 /* Status Register */ 79#define AT91_MCI_SR 0x40 /* Status Register */
80#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ 80#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
81#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ 81#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
82#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ 82#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
83#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ 83#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
84#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ 84#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
85#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ 85#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
86#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ 86#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
87#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ 87#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
88#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
89#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
88#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ 90#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
89#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ 91#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
90#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ 92#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
91#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ 93#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
92#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ 94#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
93#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ 95#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
94#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ 96#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
95#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ 97#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h
index bff5ea45f604..bec48ca89bba 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_spi.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h 2 * include/asm-arm/arch-at91rm9200/at91_spi.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_SPI_H 16#ifndef AT91_SPI_H
17#define AT91RM9200_SPI_H 17#define AT91_SPI_H
18 18
19#define AT91_SPI_CR 0x00 /* Control Register */ 19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ 20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
@@ -28,7 +28,7 @@
28#define AT91_SPI_PS_FIXED (0 << 1) 28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1) 29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ 30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */ 31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ 32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ 33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h
index ac880227147f..694bcaa8f7c2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h 2 * include/asm-arm/arch-at91rm9200/at91_ssc.h
3 * 3 *
4 * Copyright (C) SAN People 4 * Copyright (C) SAN People
5 * 5 *
@@ -12,8 +12,8 @@
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15#ifndef AT91RM9200_SSC_H 15#ifndef AT91_SSC_H
16#define AT91RM9200_SSC_H 16#define AT91_SSC_H
17 17
18#define AT91_SSC_CR 0x00 /* Control Register */ 18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ 19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
@@ -36,6 +36,10 @@
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ 36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5) 37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5) 38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
40#define AT91_SSC_CKG_NONE (0 << 6)
41#define AT91_SSC_CKG_RFLOW (1 << 6)
42#define AT91_SSC_CKG_RFHIGH (2 << 6)
39#define AT91_SSC_START (0xf << 8) /* Start Selection */ 43#define AT91_SSC_START (0xf << 8) /* Start Selection */
40#define AT91_SSC_START_CONTINUOUS (0 << 8) 44#define AT91_SSC_START_CONTINUOUS (0 << 8)
41#define AT91_SSC_START_TX_RX (1 << 8) 45#define AT91_SSC_START_TX_RX (1 << 8)
@@ -45,6 +49,7 @@
45#define AT91_SSC_START_RISING_RF (5 << 8) 49#define AT91_SSC_START_RISING_RF (5 << 8)
46#define AT91_SSC_START_LEVEL_RF (6 << 8) 50#define AT91_SSC_START_LEVEL_RF (6 << 8)
47#define AT91_SSC_START_EDGE_RF (7 << 8) 51#define AT91_SSC_START_EDGE_RF (7 << 8)
52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
48#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ 53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
49#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ 54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
50 55
@@ -75,6 +80,9 @@
75#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ 80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
76#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ 81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
77 82
83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
85
78#define AT91_SSC_SR 0x40 /* Status Register */ 86#define AT91_SSC_SR 0x40 /* Status Register */
79#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ 87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
80#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ 88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
@@ -84,6 +92,8 @@
84#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ 92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
85#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ 93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
86#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ 94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
87#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ 97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
88#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ 98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
89#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ 99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h
index f4da752bb0c8..8d06eb078e1d 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_tc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h 2 * include/asm-arm/arch-at91rm9200/at91_tc.h
3 * 3 *
4 * Copyright (C) SAN People 4 * Copyright (C) SAN People
5 * 5 *
@@ -12,8 +12,8 @@
12 * (at your option) any later version. 12 * (at your option) any later version.
13 */ 13 */
14 14
15#ifndef AT91RM9200_TC_H 15#ifndef AT91_TC_H
16#define AT91RM9200_TC_H 16#define AT91_TC_H
17 17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ 18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ 19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h
index 93547d7482bd..cda914f1e740 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+++ b/include/asm-arm/arch-at91rm9200/at91_twi.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h 2 * include/asm-arm/arch-at91rm9200/at91_twi.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -13,8 +13,8 @@
13 * (at your option) any later version. 13 * (at your option) any later version.
14 */ 14 */
15 15
16#ifndef AT91RM9200_TWI_H 16#ifndef AT91_TWI_H
17#define AT91RM9200_TWI_H 17#define AT91_TWI_H
18 18
19#define AT91_TWI_CR 0x00 /* Control Register */ 19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ 20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
@@ -43,8 +43,8 @@
43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ 43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ 44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ 45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ 46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ 47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ 48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
49 49
50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ 50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
deleted file mode 100644
index ce1150d4438d..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Peripheral Data Controller (PDC) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_PDC_H
17#define AT91RM9200_PDC_H
18
19#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
20#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
21#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
22#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
23#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
24#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
25#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
26#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
27
28#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
29#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
30#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
31#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
32#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
33
34#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
35
36#endif