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authorLinus Torvalds <torvalds@g5.osdl.org>2006-03-25 23:29:54 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-25 23:29:54 -0500
commita41622eaa97e40c811fb7756f403c0d4caa65654 (patch)
tree43dc2d74f80fc18d0467dcd2fe2168b2fccb845d /include/asm-arm/arch-at91rm9200
parent0b5c59a1e41636afa77b90d34e8c394d8d929733 (diff)
parent2ce9804fbd9d4da75fb5bb53331b46b614a7d5c3 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall [ARM] nommu: rename compressed/head.S symbols to a new style [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h [ARM] Move read of processor ID out of lookup_processor_type() [ARM] Fix typo in tlbflush.h [ARM] noMMU: removes TLB codes in nommu mode [ARM] noMMU: block sys_fork in nommu mode [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled [ARM] 3398/1: Fix the VFP registers loading/storing base address [ARM] 3397/1: AT91RM9200 Header update [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie) [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu include/linux/clk.h is betraying its ARM origins [ARM] Move enable_irq and disable_irq to assembler.h [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1
Diffstat (limited to 'include/asm-arm/arch-at91rm9200')
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h100
1 files changed, 99 insertions, 1 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 9bfffdbf1e0b..2910d359f919 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -172,6 +172,7 @@
172#define AT91_PMC_MDIV_4 (3 << 8) 172#define AT91_PMC_MDIV_4 (3 << 8)
173 173
174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ 174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
175
175#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 176#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
176#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 177#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
177#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 178#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
@@ -286,8 +287,32 @@
286#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 287#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
287 288
288#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 289#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
290#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
291#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
292#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
293#define AT91_MC_ABTSZ_BYTE (0 << 8)
294#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
295#define AT91_MC_ABTSZ_WORD (2 << 8)
296#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
297#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
298#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
299#define AT91_MC_ABTTYP_FETCH (2 << 10)
300#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
301#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
302#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
303#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
304#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
305#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
306#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
307#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
308
289#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 309#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
310
290#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 311#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
312#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
313#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
314#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
315#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
291 316
292/* External Bus Interface (EBI) registers */ 317/* External Bus Interface (EBI) registers */
293#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 318#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
@@ -309,8 +334,10 @@
309/* Static Memory Controller (SMC) registers */ 334/* Static Memory Controller (SMC) registers */
310#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 335#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
311#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 336#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
337#define AT91_SMC_NWS_(x) ((x) << 0)
312#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 338#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
313#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ 339#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
340#define AT91_SMC_TDF_(x) ((x) << 8)
314#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ 341#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
315#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ 342#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
316#define AT91_SMC_DBW_16 (1 << 13) 343#define AT91_SMC_DBW_16 (1 << 13)
@@ -322,7 +349,78 @@
322#define AT91_SMC_ACSS_2 (2 << 16) 349#define AT91_SMC_ACSS_2 (2 << 16)
323#define AT91_SMC_ACSS_3 (3 << 16) 350#define AT91_SMC_ACSS_3 (3 << 16)
324#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ 351#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
352#define AT91_SMC_RWSETUP_(x) ((x) << 24)
325#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 353#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
326 354#define AT91_SMC_RWHOLD_(x) ((x) << 28)
355
356/* SDRAM Controller registers */
357#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
358#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
359#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
360#define AT91_SDRAMC_MODE_NOP (1 << 0)
361#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
362#define AT91_SDRAMC_MODE_LMR (3 << 0)
363#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
364#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
365#define AT91_SDRAMC_DBW_32 (0 << 4)
366#define AT91_SDRAMC_DBW_16 (1 << 4)
367
368#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
369#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
370
371#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
372#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
373#define AT91_SDRAMC_NC_8 (0 << 0)
374#define AT91_SDRAMC_NC_9 (1 << 0)
375#define AT91_SDRAMC_NC_10 (2 << 0)
376#define AT91_SDRAMC_NC_11 (3 << 0)
377#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
378#define AT91_SDRAMC_NR_11 (0 << 2)
379#define AT91_SDRAMC_NR_12 (1 << 2)
380#define AT91_SDRAMC_NR_13 (2 << 2)
381#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
382#define AT91_SDRAMC_NB_2 (0 << 4)
383#define AT91_SDRAMC_NB_4 (1 << 4)
384#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
385#define AT91_SDRAMC_CAS_2 (2 << 5)
386#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
387#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
388#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
389#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
390#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
391#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
392
393#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
394#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
395#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
396#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
397#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
398#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
399
400/* Burst Flash Controller register */
401#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
402#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
403#define AT91_BFC_BFCOM_DISABLED (0 << 0)
404#define AT91_BFC_BFCOM_ASYNC (1 << 0)
405#define AT91_BFC_BFCOM_BURST (2 << 0)
406#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
407#define AT91_BFC_BFCC_MCK (1 << 2)
408#define AT91_BFC_BFCC_DIV2 (2 << 2)
409#define AT91_BFC_BFCC_DIV4 (3 << 2)
410#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
411#define AT91_BFC_PAGES (7 << 8) /* Page Size */
412#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
413#define AT91_BFC_PAGES_16 (1 << 8)
414#define AT91_BFC_PAGES_32 (2 << 8)
415#define AT91_BFC_PAGES_64 (3 << 8)
416#define AT91_BFC_PAGES_128 (4 << 8)
417#define AT91_BFC_PAGES_256 (5 << 8)
418#define AT91_BFC_PAGES_512 (6 << 8)
419#define AT91_BFC_PAGES_1024 (7 << 8)
420#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
421#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
422#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
423#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
424#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
327 425
328#endif 426#endif