Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
  [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
  [ARM] 3855/1: Add generic time support
  [ARM] 3873/1: S3C24XX: Add irq_chip names
  [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
  [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
  [ARM] nommu: confirms the CR_V bit in nommu mode
  [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
  [ARM] 3870/1: AT91: Start removing static memory mappings
  [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
  [ARM] 3868/1: AT91 hardware header update
  [ARM] 3867/1: AT91 GPIO update
  [ARM] 3866/1: AT91 clock update
  [ARM] 3865/1: AT91RM9200 header updates
  [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
  [ARM] kthread: switch arch/arm/kernel/apm.c
  [ARM] Off-by-one in arch/arm/common/icst*
  [ARM] 3864/1: Refactore sharpsl_pm
  [ARM] 3863/1: Add Locomo SPI Device
  [ARM] 3847/2:  Convert LOMOMO to use struct device for GPIOs
  [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
  ...

6 files changed, 142 insertions, 84 deletions

diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 58f40931a5c1..a5a86b1ff886 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -19,67 +19,80 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ     0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS     1       /* System Peripheral */
-#define AT91_ID_PIOA    2       /* Parallel IO Controller A */
-#define AT91_ID_PIOB    3       /* Parallel IO Controller B */
-#define AT91_ID_PIOC    4       /* Parallel IO Controller C */
-#define AT91_ID_PIOD    5       /* Parallel IO Controller D */
-#define AT91_ID_US0     6       /* USART 0 */
-#define AT91_ID_US1     7       /* USART 1 */
-#define AT91_ID_US2     8       /* USART 2 */
-#define AT91_ID_US3     9       /* USART 3 */
-#define AT91_ID_MCI     10      /* Multimedia Card Interface */
-#define AT91_ID_UDP     11      /* USB Device Port */
-#define AT91_ID_TWI     12      /* Two-Wire Interface */
-#define AT91_ID_SPI     13      /* Serial Peripheral Interface */
-#define AT91_ID_SSC0    14      /* Serial Synchronous Controller 0 */
-#define AT91_ID_SSC1    15      /* Serial Synchronous Controller 1 */
-#define AT91_ID_SSC2    16      /* Serial Synchronous Controller 2 */
-#define AT91_ID_TC0     17      /* Timer Counter 0 */
-#define AT91_ID_TC1     18      /* Timer Counter 1 */
-#define AT91_ID_TC2     19      /* Timer Counter 2 */
-#define AT91_ID_TC3     20      /* Timer Counter 3 */
-#define AT91_ID_TC4     21      /* Timer Counter 4 */
-#define AT91_ID_TC5     22      /* Timer Counter 5 */
-#define AT91_ID_UHP     23      /* USB Host port */
-#define AT91_ID_EMAC    24      /* Ethernet MAC */
-#define AT91_ID_IRQ0    25      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91_ID_IRQ1    26      /* Advanced Interrupt Controller (IRQ1) */
-#define AT91_ID_IRQ2    27      /* Advanced Interrupt Controller (IRQ2) */
-#define AT91_ID_IRQ3    28      /* Advanced Interrupt Controller (IRQ3) */
-#define AT91_ID_IRQ4    29      /* Advanced Interrupt Controller (IRQ4) */
-#define AT91_ID_IRQ5    30      /* Advanced Interrupt Controller (IRQ5) */
-#define AT91_ID_IRQ6    31      /* Advanced Interrupt Controller (IRQ6) */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripheral */
+#define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
+#define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
+#define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
+#define AT91RM9200_ID_PIOD      5       /* Parallel IO Controller D */
+#define AT91RM9200_ID_US0       6       /* USART 0 */
+#define AT91RM9200_ID_US1       7       /* USART 1 */
+#define AT91RM9200_ID_US2       8       /* USART 2 */
+#define AT91RM9200_ID_US3       9       /* USART 3 */
+#define AT91RM9200_ID_MCI       10      /* Multimedia Card Interface */
+#define AT91RM9200_ID_UDP       11      /* USB Device Port */
+#define AT91RM9200_ID_TWI       12      /* Two-Wire Interface */
+#define AT91RM9200_ID_SPI       13      /* Serial Peripheral Interface */
+#define AT91RM9200_ID_SSC0      14      /* Serial Synchronous Controller 0 */
+#define AT91RM9200_ID_SSC1      15      /* Serial Synchronous Controller 1 */
+#define AT91RM9200_ID_SSC2      16      /* Serial Synchronous Controller 2 */
+#define AT91RM9200_ID_TC0       17      /* Timer Counter 0 */
+#define AT91RM9200_ID_TC1       18      /* Timer Counter 1 */
+#define AT91RM9200_ID_TC2       19      /* Timer Counter 2 */
+#define AT91RM9200_ID_TC3       20      /* Timer Counter 3 */
+#define AT91RM9200_ID_TC4       21      /* Timer Counter 4 */
+#define AT91RM9200_ID_TC5       22      /* Timer Counter 5 */
+#define AT91RM9200_ID_UHP       23      /* USB Host port */
+#define AT91RM9200_ID_EMAC      24      /* Ethernet MAC */
+#define AT91RM9200_ID_IRQ0      25      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91RM9200_ID_IRQ1      26      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91RM9200_ID_IRQ2      27      /* Advanced Interrupt Controller (IRQ2) */
+#define AT91RM9200_ID_IRQ3      28      /* Advanced Interrupt Controller (IRQ3) */
+#define AT91RM9200_ID_IRQ4      29      /* Advanced Interrupt Controller (IRQ4) */
+#define AT91RM9200_ID_IRQ5      30      /* Advanced Interrupt Controller (IRQ5) */
+#define AT91RM9200_ID_IRQ6      31      /* Advanced Interrupt Controller (IRQ6) */
 
 
 /*
  * Peripheral physical base addresses.
  */
-#define AT91_BASE_TCB0          0xfffa0000
-#define AT91_BASE_TC0           0xfffa0000
-#define AT91_BASE_TC1           0xfffa0040
-#define AT91_BASE_TC2           0xfffa0080
-#define AT91_BASE_TCB1          0xfffa4000
-#define AT91_BASE_TC3           0xfffa4000
-#define AT91_BASE_TC4           0xfffa4040
-#define AT91_BASE_TC5           0xfffa4080
-#define AT91_BASE_UDP           0xfffb0000
-#define AT91_BASE_MCI           0xfffb4000
-#define AT91_BASE_TWI           0xfffb8000
-#define AT91_BASE_EMAC          0xfffbc000
-#define AT91_BASE_US0           0xfffc0000
-#define AT91_BASE_US1           0xfffc4000
-#define AT91_BASE_US2           0xfffc8000
-#define AT91_BASE_US3           0xfffcc000
-#define AT91_BASE_SSC0          0xfffd0000
-#define AT91_BASE_SSC1          0xfffd4000
-#define AT91_BASE_SSC2          0xfffd8000
-#define AT91_BASE_SPI           0xfffe0000
+#define AT91RM9200_BASE_TCB0    0xfffa0000
+#define AT91RM9200_BASE_TC0     0xfffa0000
+#define AT91RM9200_BASE_TC1     0xfffa0040
+#define AT91RM9200_BASE_TC2     0xfffa0080
+#define AT91RM9200_BASE_TCB1    0xfffa4000
+#define AT91RM9200_BASE_TC3     0xfffa4000
+#define AT91RM9200_BASE_TC4     0xfffa4040
+#define AT91RM9200_BASE_TC5     0xfffa4080
+#define AT91RM9200_BASE_UDP     0xfffb0000
+#define AT91RM9200_BASE_MCI     0xfffb4000
+#define AT91RM9200_BASE_TWI     0xfffb8000
+#define AT91RM9200_BASE_EMAC    0xfffbc000
+#define AT91RM9200_BASE_US0     0xfffc0000
+#define AT91RM9200_BASE_US1     0xfffc4000
+#define AT91RM9200_BASE_US2     0xfffc8000
+#define AT91RM9200_BASE_US3     0xfffcc000
+#define AT91RM9200_BASE_SSC0    0xfffd0000
+#define AT91RM9200_BASE_SSC1    0xfffd4000
+#define AT91RM9200_BASE_SSC2    0xfffd8000
+#define AT91RM9200_BASE_SPI     0xfffe0000
 #define AT91_BASE_SYS           0xfffff000
 
 
 /*
+ * Internal Memory.
+ */
+#define AT91RM9200_ROM_BASE     0x00100000      /* Internal ROM base address */
+#define AT91RM9200_ROM_SIZE     SZ_128K         /* Internal ROM size (128Kb) */
+
+#define AT91RM9200_SRAM_BASE    0x00200000      /* Internal SRAM base address */
+#define AT91RM9200_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
+
+#define AT91RM9200_UHP_BASE     0x00300000      /* USB Host controller */
+
+
+#if 0
+/*
  * PIO pin definitions (peripheral A/B multiplexing).
  */
 #define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
@@ -257,5 +270,6 @@
 #define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
 #define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
 #define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
+#endif
 
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 0f4c12d5f0cd..73693fea76a2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -80,6 +80,9 @@
 #define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
 #define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
 
+#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
 
 /*
  * PIO Controllers.
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
new file mode 100644
index 000000000000..93547d7482bd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
@@ -0,0 +1,57 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Two-wire Interface (TWI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_TWI_H
+#define AT91RM9200_TWI_H
+
+#define AT91_TWI_CR             0x00            /* Control Register */
+#define         AT91_TWI_START          (1 <<  0)       /* Send a Start Condition */
+#define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
+#define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
+#define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
+
+#define AT91_TWI_MMR            0x04            /* Master Mode Register */
+#define         AT91_TWI_IADRSZ         (3    <<  8)    /* Internal Device Address Size */
+#define                 AT91_TWI_IADRSZ_NO              (0 << 8)
+#define                 AT91_TWI_IADRSZ_1               (1 << 8)
+#define                 AT91_TWI_IADRSZ_2               (2 << 8)
+#define                 AT91_TWI_IADRSZ_3               (3 << 8)
+#define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
+#define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
+
+#define AT91_TWI_IADR           0x0c            /* Internal Address Register */
+
+#define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
+#define         AT91_TWI_CLDIV          (0xff <<  0)    /* Clock Low Divisor */
+#define         AT91_TWI_CHDIV          (0xff <<  8)    /* Clock High Divisor */
+#define         AT91_TWI_CKDIV          (7    << 16)    /* Clock Divider */
+
+#define AT91_TWI_SR             0x20            /* Status Register */
+#define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
+#define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
+#define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error */
+#define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error */
+#define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+
+#define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
+#define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
+#define AT91_TWI_IMR            0x2c            /* Interrupt Mask Register */
+#define AT91_TWI_RHR            0x30            /* Receive Holding Register */
+#define AT91_TWI_THR            0x34            /* Transmit Holding Register */
+
+#endif
+
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index dbde1baaf251..a011d27876a2 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -17,10 +17,9 @@
 
 #define PIN_BASE                NR_AIC_IRQS
 
-#define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
-#define BGA_GPIO_BANKS          4       /* BGA package has 4 banks */
+#define MAX_GPIO_BANKS          4
 
-/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
 #define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
 #define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
@@ -180,17 +179,18 @@
 
 #ifndef __ASSEMBLY__
 /* setup setup routines, called from board init or driver probe() */
-extern int at91_set_A_periph(unsigned pin, int use_pullup);
-extern int at91_set_B_periph(unsigned pin, int use_pullup);
-extern int at91_set_gpio_input(unsigned pin, int use_pullup);
-extern int at91_set_gpio_output(unsigned pin, int value);
-extern int at91_set_deglitch(unsigned pin, int is_on);
-extern int at91_set_multi_drive(unsigned pin, int is_on);
+extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
+extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
 
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
 extern int at91_get_gpio_value(unsigned pin);
 
+/* callable only from core power-management code */
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..6551b4d1ff7b 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,27 +34,14 @@
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91_BASE_SPI)
-#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91_BASE_SSC2)
-#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91_BASE_SSC1)
-#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91_BASE_SSC0)
-#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91_BASE_US3)
-#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91_BASE_US2)
-#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91_BASE_US1)
-#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91_BASE_US0)
-#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91_BASE_EMAC)
-#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91_BASE_TWI)
-#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91_BASE_MCI)
-#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91_BASE_UDP)
-#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91_BASE_TCB1)
-#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
-
-/* Internal SRAM */
-#define AT91_SRAM_BASE          0x00200000      /* Internal SRAM base address */
-#define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
+#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91RM9200_BASE_SPI)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
+#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91RM9200_BASE_TWI)
+#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91RM9200_BASE_MCI)
+#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91RM9200_BASE_UDP)
 
  /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
+#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
 
 /* Serial ports */
 #define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
@@ -71,9 +58,6 @@
 /* Compact Flash */
 #define AT91_CF_BASE            0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
 
-/* Multi-Master Memory controller */
-#define AT91_UHP_BASE           0x00300000      /* USB Host controller */
-
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
 
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index f63842c2c093..763cb96c418b 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -32,7 +32,7 @@
 
 
 /*
- * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
+ * IRQ interrupt symbols are the AT91xxx_ID_* symbols
  * for IRQs handled directly through the AIC, or else the AT91_PIN_*
  * symbols in gpio.h for ones handled indirectly as GPIOs.
  * We make provision for 4 banks of GPIO.