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authorAndrew Victor <andrew@sanpeople.com>2006-09-27 11:18:18 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-28 06:53:54 -0400
commit97f0fb68f142b477773c05140da27c1dbd31a2ab (patch)
treeb44ae4dda6b66f408be6b1af3db87d6df93f2d6e /include/asm-arm/arch-at91rm9200
parentf21738341ca330ec83ef978ee63ffa5ecf13f082 (diff)
[ARM] 3868/1: AT91 hardware header update
This patch adds the hardware register definitions for the TWI (I2C) controller found on the AT91RM9200 and AT91SAM9xx processors. It also defines the AIC Fast-Forcing registers added to the AT91SAM9's. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91rm9200')
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h3
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_twi.h57
2 files changed, 60 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 0f4c12d5f0cd..73693fea76a2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -80,6 +80,9 @@
80#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ 80#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
81#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ 81#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
82 82
83#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
84#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
85#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
83 86
84/* 87/*
85 * PIO Controllers. 88 * PIO Controllers.
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
new file mode 100644
index 000000000000..93547d7482bd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
@@ -0,0 +1,57 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Two-wire Interface (TWI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_TWI_H
17#define AT91RM9200_TWI_H
18
19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
25
26#define AT91_TWI_MMR 0x04 /* Master Mode Register */
27#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
28#define AT91_TWI_IADRSZ_NO (0 << 8)
29#define AT91_TWI_IADRSZ_1 (1 << 8)
30#define AT91_TWI_IADRSZ_2 (2 << 8)
31#define AT91_TWI_IADRSZ_3 (3 << 8)
32#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
33#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
34
35#define AT91_TWI_IADR 0x0c /* Internal Address Register */
36
37#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
38#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
39#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
40#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
41
42#define AT91_TWI_SR 0x20 /* Status Register */
43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
49
50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
51#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
52#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
53#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
54#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
55
56#endif
57