diff options
| author | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-07 18:40:39 -0500 |
| commit | ea14fad0d416354a4e9bb1a04f32acba706f9548 (patch) | |
| tree | 2c8acc5331f189aef1d40ddce3f40d6be9314e77 /include/asm-arm/arch-at91rm9200 | |
| parent | 6ee7e78e7c78d871409ad4df30551c9355be7d0e (diff) | |
| parent | 6705cda24fad1cb0ac82ac4f312df8ec735b39b0 (diff) | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
[ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
[ARM] 4001/1: S3C24XX: shorten reboot time
[ARM] 3983/2: remove unused argument to __bug()
[ARM] 4000/1: Osiris: add third serial port in
[ARM] 3999/1: RX3715: suspend to RAM support
[ARM] 3998/1: VR1000: LED platform devices
[ARM] 3995/1: iop13xx: add iop13xx support
[ARM] 3968/1: iop13xx: add iop13xx_defconfig
[ARM] Update mach-types
[ARM] Allow gcc to optimise arm_add_memory a little more
[ARM] 3991/1: i.MX/MX1 high resolution time source
[ARM] 3990/1: i.MX/MX1 more precise PLL decode
[ARM] 3986/1: H1940: suspend to RAM support
[ARM] 3985/1: ixp4xx clocksource cleanup
[ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
[ARM] 3994/1: ixp23xx: fix handling of pci master aborts
[ARM] 3981/1: sched_clock for PXA2xx
[ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
[ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
[ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
...
Diffstat (limited to 'include/asm-arm/arch-at91rm9200')
38 files changed, 1723 insertions, 579 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_aic.h b/include/asm-arm/arch-at91rm9200/at91_aic.h new file mode 100644 index 000000000000..267e69812e26 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_aic.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_aic.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_AIC_H | ||
| 17 | #define AT91_AIC_H | ||
| 18 | |||
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 26 | |||
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 32 | |||
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 38 | |||
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 48 | |||
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h new file mode 100644 index 000000000000..e4b8b27acfca --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_dbgu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Debug Unit (DBGU) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_DBGU_H | ||
| 17 | #define AT91_DBGU_H | ||
| 18 | |||
| 19 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 20 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 21 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 22 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 23 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 24 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 25 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 26 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 27 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 28 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 29 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 30 | |||
| 31 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 32 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 33 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 34 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 35 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 36 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 37 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 38 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 39 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 40 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 41 | |||
| 42 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
| 43 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h new file mode 100644 index 000000000000..fddf256a98d3 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_ecc.h | ||
| 3 | * | ||
| 4 | * Error Corrected Code Controller (ECC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_ECC_H | ||
| 14 | #define AT91_ECC_H | ||
| 15 | |||
| 16 | #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ | ||
| 17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ | ||
| 18 | |||
| 19 | #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ | ||
| 20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ | ||
| 21 | #define AT91_ECC_PAGESIZE_528 (0) | ||
| 22 | #define AT91_ECC_PAGESIZE_1056 (1) | ||
| 23 | #define AT91_ECC_PAGESIZE_2112 (2) | ||
| 24 | #define AT91_ECC_PAGESIZE_4224 (3) | ||
| 25 | |||
| 26 | #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ | ||
| 27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ | ||
| 28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ | ||
| 29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ | ||
| 30 | |||
| 31 | #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ | ||
| 32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ | ||
| 33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ | ||
| 34 | |||
| 35 | #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ | ||
| 36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h new file mode 100644 index 000000000000..9cbfcdd3c471 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h | |||
| @@ -0,0 +1,148 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_lcdc.h | ||
| 3 | * | ||
| 4 | * LCD Controller (LCDC). | ||
| 5 | * Based on AT91SAM9261 datasheet revision E. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_LCDC_H | ||
| 14 | #define AT91_LCDC_H | ||
| 15 | |||
| 16 | #define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ | ||
| 17 | #define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ | ||
| 18 | #define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ | ||
| 19 | #define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ | ||
| 20 | #define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ | ||
| 21 | #define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ | ||
| 22 | |||
| 23 | #define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ | ||
| 24 | #define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ | ||
| 25 | #define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ | ||
| 26 | |||
| 27 | #define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ | ||
| 28 | #define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ | ||
| 29 | #define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ | ||
| 30 | #define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ | ||
| 31 | |||
| 32 | #define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ | ||
| 33 | #define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ | ||
| 34 | #define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ | ||
| 35 | #define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ | ||
| 36 | |||
| 37 | #define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ | ||
| 38 | #define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ | ||
| 39 | #define AT91_LCDC_DISTYPE_STNMONO (0 << 0) | ||
| 40 | #define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) | ||
| 41 | #define AT91_LCDC_DISTYPE_TFT (2 << 0) | ||
| 42 | #define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ | ||
| 43 | #define AT91_LCDC_SCANMOD_SINGLE (0 << 2) | ||
| 44 | #define AT91_LCDC_SCANMOD_DUAL (1 << 2) | ||
| 45 | #define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ | ||
| 46 | #define AT91_LCDC_IFWIDTH_4 (0 << 3) | ||
| 47 | #define AT91_LCDC_IFWIDTH_8 (1 << 3) | ||
| 48 | #define AT91_LCDC_IFWIDTH_16 (2 << 3) | ||
| 49 | #define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ | ||
| 50 | #define AT91_LCDC_PIXELSIZE_1 (0 << 5) | ||
| 51 | #define AT91_LCDC_PIXELSIZE_2 (1 << 5) | ||
| 52 | #define AT91_LCDC_PIXELSIZE_4 (2 << 5) | ||
| 53 | #define AT91_LCDC_PIXELSIZE_8 (3 << 5) | ||
| 54 | #define AT91_LCDC_PIXELSIZE_16 (4 << 5) | ||
| 55 | #define AT91_LCDC_PIXELSIZE_24 (5 << 5) | ||
| 56 | #define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ | ||
| 57 | #define AT91_LCDC_INVVD_NORMAL (0 << 8) | ||
| 58 | #define AT91_LCDC_INVVD_INVERTED (1 << 8) | ||
| 59 | #define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ | ||
| 60 | #define AT91_LCDC_INVFRAME_NORMAL (0 << 9) | ||
| 61 | #define AT91_LCDC_INVFRAME_INVERTED (1 << 9) | ||
| 62 | #define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ | ||
| 63 | #define AT91_LCDC_INVLINE_NORMAL (0 << 10) | ||
| 64 | #define AT91_LCDC_INVLINE_INVERTED (1 << 10) | ||
| 65 | #define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ | ||
| 66 | #define AT91_LCDC_INVCLK_NORMAL (0 << 11) | ||
| 67 | #define AT91_LCDC_INVCLK_INVERTED (1 << 11) | ||
| 68 | #define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ | ||
| 69 | #define AT91_LCDC_INVDVAL_NORMAL (0 << 12) | ||
| 70 | #define AT91_LCDC_INVDVAL_INVERTED (1 << 12) | ||
| 71 | #define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ | ||
| 72 | #define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) | ||
| 73 | #define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) | ||
| 74 | #define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ | ||
| 75 | #define AT91_LCDC_MEMOR_BIG (0 << 31) | ||
| 76 | #define AT91_LCDC_MEMOR_LITTLE (1 << 31) | ||
| 77 | |||
| 78 | #define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ | ||
| 79 | #define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ | ||
| 80 | #define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ | ||
| 81 | #define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ | ||
| 82 | #define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ | ||
| 83 | |||
| 84 | #define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ | ||
| 85 | #define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ | ||
| 86 | #define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ | ||
| 87 | #define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ | ||
| 88 | |||
| 89 | #define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ | ||
| 90 | #define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ | ||
| 91 | #define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ | ||
| 92 | |||
| 93 | #define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ | ||
| 94 | #define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ | ||
| 95 | |||
| 96 | #define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ | ||
| 97 | #define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ | ||
| 98 | #define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ | ||
| 99 | #define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ | ||
| 100 | #define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ | ||
| 101 | #define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ | ||
| 102 | #define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ | ||
| 103 | #define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ | ||
| 104 | #define AT91_LCDC_DP1_2_VAL (0xff) | ||
| 105 | #define AT91_LCDC_DP4_7_VAL (0xfffffff) | ||
| 106 | #define AT91_LCDC_DP3_5_VAL (0xfffff) | ||
| 107 | #define AT91_LCDC_DP2_3_VAL (0xfff) | ||
| 108 | #define AT91_LCDC_DP5_7_VAL (0xfffffff) | ||
| 109 | #define AT91_LCDC_DP3_4_VAL (0xffff) | ||
| 110 | #define AT91_LCDC_DP4_5_VAL (0xfffff) | ||
| 111 | #define AT91_LCDC_DP6_7_VAL (0xfffffff) | ||
| 112 | |||
| 113 | #define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ | ||
| 114 | #define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ | ||
| 115 | #define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ | ||
| 116 | #define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ | ||
| 117 | |||
| 118 | #define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ | ||
| 119 | #define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ | ||
| 120 | #define AT91_LCDC_PS_DIV1 (0 << 0) | ||
| 121 | #define AT91_LCDC_PS_DIV2 (1 << 0) | ||
| 122 | #define AT91_LCDC_PS_DIV4 (2 << 0) | ||
| 123 | #define AT91_LCDC_PS_DIV8 (3 << 0) | ||
| 124 | #define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ | ||
| 125 | #define AT91_LCDC_POL_NEGATIVE (0 << 2) | ||
| 126 | #define AT91_LCDC_POL_POSITIVE (1 << 2) | ||
| 127 | #define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ | ||
| 128 | #define AT91_LCDC_ENA_PWMDISABLE (0 << 3) | ||
| 129 | #define AT91_LCDC_ENA_PWMENABLE (1 << 3) | ||
| 130 | |||
| 131 | #define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ | ||
| 132 | #define AT91_LCDC_CVAL (0xff) /* PWM compare value */ | ||
| 133 | |||
| 134 | #define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ | ||
| 135 | #define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ | ||
| 136 | #define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ | ||
| 137 | #define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ | ||
| 138 | #define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ | ||
| 139 | #define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ | ||
| 140 | #define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ | ||
| 141 | #define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ | ||
| 142 | #define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ | ||
| 143 | #define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ | ||
| 144 | #define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ | ||
| 145 | |||
| 146 | #define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ | ||
| 147 | |||
| 148 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h b/include/asm-arm/arch-at91rm9200/at91_mci.h index f28636d61e39..9a552cb743c0 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_mci.h +++ b/include/asm-arm/arch-at91rm9200/at91_mci.h | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_mci.h | 2 | * include/asm-arm/arch-at91rm9200/at91_mci.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| 6 | * | 6 | * |
| 7 | * MultiMedia Card Interface (MCI) registers. | 7 | * MultiMedia Card Interface (MCI) registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. | 8 | * Based on AT91RM9200 datasheet revision F. |
| 9 | * | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by | 11 | * it under the terms of the GNU General Public License as published by |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_MCI_H | 16 | #ifndef AT91_MCI_H |
| 17 | #define AT91RM9200_MCI_H | 17 | #define AT91_MCI_H |
| 18 | 18 | ||
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ | 19 | #define AT91_MCI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ | 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ |
| @@ -25,10 +25,10 @@ | |||
| 25 | 25 | ||
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ | 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ |
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ | 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ |
| 28 | #define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ | 28 | #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ |
| 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ | 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ |
| 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ | 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ |
| 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ | 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ |
| 32 | 32 | ||
| 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ | 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ |
| 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ | 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ |
| @@ -43,8 +43,8 @@ | |||
| 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) | 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) |
| 44 | 44 | ||
| 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ | 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ |
| 46 | #define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ | 46 | #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ |
| 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ | 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ |
| 48 | 48 | ||
| 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ | 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ |
| 50 | 50 | ||
| @@ -78,18 +78,20 @@ | |||
| 78 | 78 | ||
| 79 | #define AT91_MCI_SR 0x40 /* Status Register */ | 79 | #define AT91_MCI_SR 0x40 /* Status Register */ |
| 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ | 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ |
| 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ | 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ |
| 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ | 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ |
| 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ | 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ |
| 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ | 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ |
| 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ | 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ |
| 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ | 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ |
| 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ | 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ |
| 88 | #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ | ||
| 89 | #define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ | ||
| 88 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ | 90 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ |
| 89 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ | 91 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ |
| 90 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ | 92 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ |
| 91 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ | 93 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ |
| 92 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ | 94 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ |
| 93 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ | 95 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ |
| 94 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ | 96 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ |
| 95 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ | 97 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91_pdc.h index ce1150d4438d..79d6e02fa45e 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h +++ b/include/asm-arm/arch-at91rm9200/at91_pdc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_pdc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_PDC_H | 16 | #ifndef AT91_PDC_H |
| 17 | #define AT91RM9200_PDC_H | 17 | #define AT91_PDC_H |
| 18 | 18 | ||
| 19 | #define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ | 19 | #define AT91_PDC_RPR 0x100 /* Receive Pointer Register */ |
| 20 | #define AT91_PDC_RCR 0x104 /* Receive Counter Register */ | 20 | #define AT91_PDC_RCR 0x104 /* Receive Counter Register */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_pio.h b/include/asm-arm/arch-at91rm9200/at91_pio.h new file mode 100644 index 000000000000..680eaa1f5915 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pio.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Parallel I/O Controller (PIO) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PIO_H | ||
| 17 | #define AT91_PIO_H | ||
| 18 | |||
| 19 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 20 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 21 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 22 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 23 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 24 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 25 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 26 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 27 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 28 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 29 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 30 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 31 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 32 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 33 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 34 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 35 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 36 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 37 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 38 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 39 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 40 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 41 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 42 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 43 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 44 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 45 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 46 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 47 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_pit.h b/include/asm-arm/arch-at91rm9200/at91_pit.h new file mode 100644 index 000000000000..4a30d009c588 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pit.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pit.h | ||
| 3 | * | ||
| 4 | * Periodic Interval Timer (PIT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_PIT_H | ||
| 14 | #define AT91_PIT_H | ||
| 15 | |||
| 16 | #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | ||
| 18 | #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | ||
| 19 | #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | ||
| 20 | |||
| 21 | #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | ||
| 22 | #define AT91_PIT_PITS (1 << 0) /* Timer Status */ | ||
| 23 | |||
| 24 | #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | ||
| 25 | #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | ||
| 26 | #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | ||
| 27 | #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h new file mode 100644 index 000000000000..de8c3da74a01 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Power Management Controller (PMC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PMC_H | ||
| 17 | #define AT91_PMC_H | ||
| 18 | |||
| 19 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 20 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 21 | |||
| 22 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
| 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
| 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
| 28 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
| 29 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 30 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 31 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 32 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 33 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
| 34 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
| 35 | |||
| 36 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 37 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 38 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 39 | |||
| 40 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | ||
| 41 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 42 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | ||
| 43 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 44 | |||
| 45 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 46 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 47 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 48 | |||
| 49 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 50 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 51 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 52 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 53 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 54 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 55 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 56 | |||
| 57 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 58 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 59 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 60 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 61 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 62 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 63 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 64 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 65 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 66 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 67 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 68 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 69 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 70 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 71 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 72 | #define AT91_PMC_MDIV_1 (0 << 8) | ||
| 73 | #define AT91_PMC_MDIV_2 (1 << 8) | ||
| 74 | #define AT91_PMC_MDIV_3 (2 << 8) | ||
| 75 | #define AT91_PMC_MDIV_4 (3 << 8) | ||
| 76 | |||
| 77 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 78 | |||
| 79 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 80 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 81 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 82 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 83 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 84 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 85 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 86 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 87 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 88 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 89 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 90 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h new file mode 100644 index 000000000000..ccdc52da973d --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rstc.h | ||
| 3 | * | ||
| 4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RSTC_H | ||
| 14 | #define AT91_RSTC_H | ||
| 15 | |||
| 16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
| 20 | #define AT01_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
| 21 | |||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
| 24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
| 25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
| 26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
| 27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
| 28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
| 29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
| 30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
| 31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
| 32 | |||
| 33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
| 34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
| 35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
| 36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
| 37 | #define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h new file mode 100644 index 000000000000..6e5065d56260 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rtc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Real Time Clock (RTC) - System peripheral registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_RTC_H | ||
| 17 | #define AT91_RTC_H | ||
| 18 | |||
| 19 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 20 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 21 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 22 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 23 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 24 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 25 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 26 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 27 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 28 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 29 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 30 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 31 | |||
| 32 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 33 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 34 | |||
| 35 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 36 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 37 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 38 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 39 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 40 | |||
| 41 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 42 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 43 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 44 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 45 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 46 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 47 | |||
| 48 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 49 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 50 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 51 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 52 | |||
| 53 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 54 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 55 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 56 | |||
| 57 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 58 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 59 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 60 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 61 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 62 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 63 | |||
| 64 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 65 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 66 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 67 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 68 | |||
| 69 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 70 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 71 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 72 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 73 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h new file mode 100644 index 000000000000..c6751ba3cccc --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_rtt.h | ||
| 3 | * | ||
| 4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RTT_H | ||
| 14 | #define AT91_RTT_H | ||
| 15 | |||
| 16 | #define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ | ||
| 17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
| 18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
| 19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
| 20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ | ||
| 23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
| 24 | |||
| 25 | #define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ | ||
| 26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
| 27 | |||
| 28 | #define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ | ||
| 29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
| 30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h new file mode 100644 index 000000000000..0439250553c9 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_shdwc.h | ||
| 3 | * | ||
| 4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_SHDWC_H | ||
| 14 | #define AT91_SHDWC_H | ||
| 15 | |||
| 16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
| 17 | #define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
| 21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
| 22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
| 23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
| 24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
| 25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
| 26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
| 27 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
| 28 | |||
| 29 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
| 30 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
| 31 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h b/include/asm-arm/arch-at91rm9200/at91_spi.h index bff5ea45f604..bec48ca89bba 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_spi.h +++ b/include/asm-arm/arch-at91rm9200/at91_spi.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_spi.h | 2 | * include/asm-arm/arch-at91rm9200/at91_spi.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_SPI_H | 16 | #ifndef AT91_SPI_H |
| 17 | #define AT91RM9200_SPI_H | 17 | #define AT91_SPI_H |
| 18 | 18 | ||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | 19 | #define AT91_SPI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ |
| @@ -28,7 +28,7 @@ | |||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | 28 | #define AT91_SPI_PS_FIXED (0 << 1) |
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) |
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ |
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */ | 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ |
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ |
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ |
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h b/include/asm-arm/arch-at91rm9200/at91_ssc.h index ac880227147f..694bcaa8f7c2 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h +++ b/include/asm-arm/arch-at91rm9200/at91_ssc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_ssc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) SAN People | 4 | * Copyright (C) SAN People |
| 5 | * | 5 | * |
| @@ -12,8 +12,8 @@ | |||
| 12 | * (at your option) any later version. | 12 | * (at your option) any later version. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #ifndef AT91RM9200_SSC_H | 15 | #ifndef AT91_SSC_H |
| 16 | #define AT91RM9200_SSC_H | 16 | #define AT91_SSC_H |
| 17 | 17 | ||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | 18 | #define AT91_SSC_CR 0x00 /* Control Register */ |
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ |
| @@ -36,6 +36,10 @@ | |||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ |
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | 37 | #define AT91_SSC_CKI_FALLING (0 << 5) |
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | 38 | #define AT91_SSC_CK_RISING (1 << 5) |
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 39 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ |
| 40 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) |
| 41 | #define AT91_SSC_START_TX_RX (1 << 8) | 45 | #define AT91_SSC_START_TX_RX (1 << 8) |
| @@ -45,6 +49,7 @@ | |||
| 45 | #define AT91_SSC_START_RISING_RF (5 << 8) | 49 | #define AT91_SSC_START_RISING_RF (5 << 8) |
| 46 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) |
| 47 | #define AT91_SSC_START_EDGE_RF (7 << 8) | 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) |
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 48 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ |
| 49 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ |
| 50 | 55 | ||
| @@ -75,6 +80,9 @@ | |||
| 75 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ |
| 76 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ |
| 77 | 82 | ||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 78 | #define AT91_SSC_SR 0x40 /* Status Register */ | 86 | #define AT91_SSC_SR 0x40 /* Status Register */ |
| 79 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ |
| 80 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ |
| @@ -84,6 +92,8 @@ | |||
| 84 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ |
| 85 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ |
| 86 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ |
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 87 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ |
| 88 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ |
| 89 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_st.h b/include/asm-arm/arch-at91rm9200/at91_st.h new file mode 100644 index 000000000000..2432ddfc6c47 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_st.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_st.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System Timer (ST) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_ST_H | ||
| 17 | #define AT91_ST_H | ||
| 18 | |||
| 19 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 20 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 23 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 24 | |||
| 25 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 26 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 27 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 28 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 29 | |||
| 30 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 31 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 32 | |||
| 33 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 34 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 35 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 36 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 37 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 38 | |||
| 39 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 40 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 41 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 42 | |||
| 43 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 44 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 45 | |||
| 46 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 47 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h b/include/asm-arm/arch-at91rm9200/at91_tc.h index f4da752bb0c8..8d06eb078e1d 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_tc.h +++ b/include/asm-arm/arch-at91rm9200/at91_tc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_tc.h | 2 | * include/asm-arm/arch-at91rm9200/at91_tc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) SAN People | 4 | * Copyright (C) SAN People |
| 5 | * | 5 | * |
| @@ -12,8 +12,8 @@ | |||
| 12 | * (at your option) any later version. | 12 | * (at your option) any later version. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #ifndef AT91RM9200_TC_H | 15 | #ifndef AT91_TC_H |
| 16 | #define AT91RM9200_TC_H | 16 | #define AT91_TC_H |
| 17 | 17 | ||
| 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ | 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ |
| 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ | 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91_twi.h index 93547d7482bd..cda914f1e740 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h +++ b/include/asm-arm/arch-at91rm9200/at91_twi.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h | 2 | * include/asm-arm/arch-at91rm9200/at91_twi.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -13,8 +13,8 @@ | |||
| 13 | * (at your option) any later version. | 13 | * (at your option) any later version. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef AT91RM9200_TWI_H | 16 | #ifndef AT91_TWI_H |
| 17 | #define AT91RM9200_TWI_H | 17 | #define AT91_TWI_H |
| 18 | 18 | ||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | 19 | #define AT91_TWI_CR 0x00 /* Control Register */ |
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ |
| @@ -43,8 +43,8 @@ | |||
| 43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | 43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ |
| 44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | 44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ |
| 45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | 45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ |
| 46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ | 46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ |
| 47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ | 47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ |
| 48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | 48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ |
| 49 | 49 | ||
| 50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | 50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h new file mode 100644 index 000000000000..ac63e775772c --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91_wdt.h | ||
| 3 | * | ||
| 4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_WDT_H | ||
| 14 | #define AT91_WDT_H | ||
| 15 | |||
| 16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
| 17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
| 18 | #define AT91_WDT_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
| 21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
| 22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
| 23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
| 24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
| 25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
| 26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
| 27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
| 28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
| 29 | |||
| 30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
| 31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
| 32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h index a5a86b1ff886..4d51177efddd 100644 --- a/include/asm-arm/arch-at91rm9200/at91rm9200.h +++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h | |||
| @@ -80,6 +80,22 @@ | |||
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ | ||
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ | ||
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ | ||
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ | ||
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | ||
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ | ||
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ | ||
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 95 | |||
| 96 | #define AT91_MATRIX 0 /* not supported */ | ||
| 97 | |||
| 98 | /* | ||
| 83 | * Internal Memory. | 99 | * Internal Memory. |
| 84 | */ | 100 | */ |
| 85 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ | 101 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h new file mode 100644 index 000000000000..0c0d81480b3a --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91rm9200_mc.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_mc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_MC_H | ||
| 17 | #define AT91RM9200_MC_H | ||
| 18 | |||
| 19 | /* Memory Controller */ | ||
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 22 | |||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 27 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 28 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 29 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 30 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 31 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 32 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 33 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 34 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 35 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 36 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 37 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 38 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 39 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 42 | |||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 44 | |||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 50 | |||
| 51 | /* External Bus Interface (EBI) registers */ | ||
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 56 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 57 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 58 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 59 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 60 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 61 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 62 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 63 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 64 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 65 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 67 | |||
| 68 | /* Static Memory Controller (SMC) registers */ | ||
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 73 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 74 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 75 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 76 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 77 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 78 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 79 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 80 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 81 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 82 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 83 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 84 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 85 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 86 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 87 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 89 | |||
| 90 | /* SDRAM Controller registers */ | ||
| 91 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 92 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 93 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 94 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 95 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 96 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 97 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 98 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 99 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 100 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 101 | |||
| 102 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 103 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 104 | |||
| 105 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 106 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 107 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 108 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 109 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 110 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 111 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 112 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 113 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 114 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 115 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 116 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 117 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 118 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 119 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 120 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 121 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 122 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 123 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 124 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 125 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 126 | |||
| 127 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 128 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 129 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 130 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 131 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 132 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 133 | |||
| 134 | /* Burst Flash Controller register */ | ||
| 135 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 136 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 137 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 138 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 139 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 140 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 141 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 142 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 143 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 144 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 145 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 146 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 147 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 148 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 149 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 150 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 151 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 152 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 153 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 154 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 155 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 156 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 157 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 158 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h deleted file mode 100644 index 73693fea76a2..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h +++ /dev/null | |||
| @@ -1,438 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_SYS_H | ||
| 17 | #define AT91RM9200_SYS_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Advanced Interrupt Controller. | ||
| 21 | */ | ||
| 22 | #define AT91_AIC 0x000 | ||
| 23 | |||
| 24 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 25 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 26 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 27 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 28 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 29 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 30 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 31 | |||
| 32 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 33 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 34 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 35 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 37 | |||
| 38 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 39 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 40 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 41 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 42 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 43 | |||
| 44 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 45 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 46 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 47 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 48 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 49 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 50 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 51 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 52 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * Debug Unit. | ||
| 57 | */ | ||
| 58 | #define AT91_DBGU 0x200 | ||
| 59 | |||
| 60 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 61 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 62 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 63 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 64 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 65 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 66 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 67 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 68 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 69 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 70 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 71 | |||
| 72 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 73 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 74 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 75 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 76 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 77 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 78 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 79 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 80 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 81 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 82 | |||
| 83 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 84 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 85 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 86 | |||
| 87 | /* | ||
| 88 | * PIO Controllers. | ||
| 89 | */ | ||
| 90 | #define AT91_PIOA 0x400 | ||
| 91 | #define AT91_PIOB 0x600 | ||
| 92 | #define AT91_PIOC 0x800 | ||
| 93 | #define AT91_PIOD 0xa00 | ||
| 94 | |||
| 95 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 96 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 97 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 98 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 99 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 100 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 101 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 102 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 103 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 104 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 105 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 106 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 107 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 108 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 109 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 110 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 111 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 112 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 113 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 114 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 115 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 116 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 117 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 118 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 119 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 120 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 121 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 122 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 123 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 124 | |||
| 125 | #define AT91_PIO_P(n) (1 << (n)) | ||
| 126 | |||
| 127 | |||
| 128 | /* | ||
| 129 | * Power Management Controller. | ||
| 130 | */ | ||
| 131 | #define AT91_PMC 0xc00 | ||
| 132 | |||
| 133 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 134 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 135 | |||
| 136 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 137 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 138 | #define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */ | ||
| 139 | #define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */ | ||
| 140 | #define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */ | ||
| 141 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 142 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 143 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 144 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 145 | |||
| 146 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 147 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 148 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 149 | |||
| 150 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | ||
| 151 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 152 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 153 | |||
| 154 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 155 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 156 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 157 | |||
| 158 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 159 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 160 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 161 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 162 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 163 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 164 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 165 | |||
| 166 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 167 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 168 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 169 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 170 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 171 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 172 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 173 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 174 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 175 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 176 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 177 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 178 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 179 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 180 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 181 | #define AT91_PMC_MDIV_1 (0 << 8) | ||
| 182 | #define AT91_PMC_MDIV_2 (1 << 8) | ||
| 183 | #define AT91_PMC_MDIV_3 (2 << 8) | ||
| 184 | #define AT91_PMC_MDIV_4 (3 << 8) | ||
| 185 | |||
| 186 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 187 | |||
| 188 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 189 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 190 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 191 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 192 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 193 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 194 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 195 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 196 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 197 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 198 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 199 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 200 | |||
| 201 | |||
| 202 | /* | ||
| 203 | * System Timer. | ||
| 204 | */ | ||
| 205 | #define AT91_ST 0xd00 | ||
| 206 | |||
| 207 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 208 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 209 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 210 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 211 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 212 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 213 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 214 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 215 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 216 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 217 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 218 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 219 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 220 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 221 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 222 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 223 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 224 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 225 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 226 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 227 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 228 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 229 | |||
| 230 | |||
| 231 | /* | ||
| 232 | * Real-time Clock. | ||
| 233 | */ | ||
| 234 | #define AT91_RTC 0xe00 | ||
| 235 | |||
| 236 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 237 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 238 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 239 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 240 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 241 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 242 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 243 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 244 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 245 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 246 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 247 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 248 | |||
| 249 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 250 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 251 | |||
| 252 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 253 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 254 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 255 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 256 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 257 | |||
| 258 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 259 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 260 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 261 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 262 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 263 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 264 | |||
| 265 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 266 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 267 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 268 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 269 | |||
| 270 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 271 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 272 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 273 | |||
| 274 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 275 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 276 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 277 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 278 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 279 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 280 | |||
| 281 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 282 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 283 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 284 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 285 | |||
| 286 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 287 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 288 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 289 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 290 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 291 | |||
| 292 | |||
| 293 | /* | ||
| 294 | * Memory Controller. | ||
| 295 | */ | ||
| 296 | #define AT91_MC 0xf00 | ||
| 297 | |||
| 298 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 299 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 300 | |||
| 301 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 302 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 303 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 304 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 305 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 306 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 307 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 308 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 309 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 310 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 311 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 312 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 313 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 314 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 315 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 316 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 317 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 318 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 319 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 320 | |||
| 321 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 322 | |||
| 323 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 324 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 325 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 326 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 327 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 328 | |||
| 329 | /* External Bus Interface (EBI) registers */ | ||
| 330 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 331 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 332 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 333 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 334 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 335 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 336 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 337 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 338 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 339 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 340 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 341 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 342 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 343 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 344 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 345 | |||
| 346 | /* Static Memory Controller (SMC) registers */ | ||
| 347 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 348 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 349 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 350 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 351 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 352 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 353 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 354 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 355 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 356 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 357 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 358 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 359 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 360 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 361 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 362 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 363 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 364 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 365 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 366 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 367 | |||
| 368 | /* SDRAM Controller registers */ | ||
| 369 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 370 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 371 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 372 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 373 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 374 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 375 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 376 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 377 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 378 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 379 | |||
| 380 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 381 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 382 | |||
| 383 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 384 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 385 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 386 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 387 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 388 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 389 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 390 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 391 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 392 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 393 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 394 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 395 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 396 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 397 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 398 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 399 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 400 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 401 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 402 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 403 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 404 | |||
| 405 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 406 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 407 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 408 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 409 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 410 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 411 | |||
| 412 | /* Burst Flash Controller register */ | ||
| 413 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 414 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 415 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 416 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 417 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 418 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 419 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 420 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 421 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 422 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 423 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 424 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 425 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 426 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 427 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 428 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 429 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 430 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 431 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 432 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 433 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 434 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 435 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 436 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 437 | |||
| 438 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h b/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h deleted file mode 100644 index 951e3f61cef4..000000000000 --- a/include/asm-arm/arch-at91rm9200/at91rm9200_udp.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91rm9200_udp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * USB Device Port (UDP) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_UDP_H | ||
| 17 | #define AT91RM9200_UDP_H | ||
| 18 | |||
| 19 | #define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */ | ||
| 20 | #define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */ | ||
| 21 | #define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */ | ||
| 22 | #define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */ | ||
| 23 | |||
| 24 | #define AT91_UDP_GLB_STAT 0x04 /* Global State Register */ | ||
| 25 | #define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */ | ||
| 26 | #define AT91_UDP_CONFG (1 << 1) /* Configured */ | ||
| 27 | #define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */ | ||
| 28 | #define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */ | ||
| 29 | #define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */ | ||
| 30 | |||
| 31 | #define AT91_UDP_FADDR 0x08 /* Function Address Register */ | ||
| 32 | #define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */ | ||
| 33 | #define AT91_UDP_FEN (1 << 8) /* Function Enable */ | ||
| 34 | |||
| 35 | #define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ | ||
| 36 | #define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ | ||
| 37 | #define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ | ||
| 38 | |||
| 39 | #define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ | ||
| 40 | #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ | ||
| 41 | #define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ | ||
| 42 | #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ | ||
| 43 | #define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */ | ||
| 44 | #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ | ||
| 45 | #define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */ | ||
| 46 | #define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */ | ||
| 47 | |||
| 48 | #define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ | ||
| 49 | #define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */ | ||
| 50 | |||
| 51 | #define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */ | ||
| 52 | #define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */ | ||
| 53 | #define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */ | ||
| 54 | #define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */ | ||
| 55 | #define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */ | ||
| 56 | #define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */ | ||
| 57 | #define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */ | ||
| 58 | #define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */ | ||
| 59 | #define AT91_UDP_DIR (1 << 7) /* Transfer Direction */ | ||
| 60 | #define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */ | ||
| 61 | #define AT91_UDP_EPTYPE_CTRL (0 << 8) | ||
| 62 | #define AT91_UDP_EPTYPE_ISO_OUT (1 << 8) | ||
| 63 | #define AT91_UDP_EPTYPE_BULK_OUT (2 << 8) | ||
| 64 | #define AT91_UDP_EPTYPE_INT_OUT (3 << 8) | ||
| 65 | #define AT91_UDP_EPTYPE_ISO_IN (5 << 8) | ||
| 66 | #define AT91_UDP_EPTYPE_BULK_IN (6 << 8) | ||
| 67 | #define AT91_UDP_EPTYPE_INT_IN (7 << 8) | ||
| 68 | #define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */ | ||
| 69 | #define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */ | ||
| 70 | #define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */ | ||
| 71 | |||
| 72 | #define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */ | ||
| 73 | |||
| 74 | #define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ | ||
| 75 | #define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */ | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h new file mode 100644 index 000000000000..46f4dd65c035 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h | |||
| @@ -0,0 +1,125 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9260.h | ||
| 3 | * | ||
| 4 | * (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9260 datasheet revision A (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9260_H | ||
| 16 | #define AT91SAM9260_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ | ||
| 27 | #define AT91SAM9260_ID_US0 6 /* USART 0 */ | ||
| 28 | #define AT91SAM9260_ID_US1 7 /* USART 1 */ | ||
| 29 | #define AT91SAM9260_ID_US2 8 /* USART 2 */ | ||
| 30 | #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 31 | #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ | ||
| 32 | #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ | ||
| 36 | #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ | ||
| 37 | #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ | ||
| 38 | #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ | ||
| 39 | #define AT91SAM9260_ID_UHP 20 /* USB Host port */ | ||
| 40 | #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ | ||
| 42 | #define AT91SAM9260_ID_US3 23 /* USART 3 */ | ||
| 43 | #define AT91SAM9260_ID_US4 24 /* USART 4 */ | ||
| 44 | #define AT91SAM9260_ID_US5 25 /* USART 5 */ | ||
| 45 | #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ | ||
| 46 | #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ | ||
| 47 | #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ | ||
| 48 | #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 49 | #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 50 | #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 51 | |||
| 52 | |||
| 53 | /* | ||
| 54 | * User Peripheral physical base addresses. | ||
| 55 | */ | ||
| 56 | #define AT91SAM9260_BASE_TCB0 0xfffa0000 | ||
| 57 | #define AT91SAM9260_BASE_TC0 0xfffa0000 | ||
| 58 | #define AT91SAM9260_BASE_TC1 0xfffa0040 | ||
| 59 | #define AT91SAM9260_BASE_TC2 0xfffa0080 | ||
| 60 | #define AT91SAM9260_BASE_UDP 0xfffa4000 | ||
| 61 | #define AT91SAM9260_BASE_MCI 0xfffa8000 | ||
| 62 | #define AT91SAM9260_BASE_TWI 0xfffac000 | ||
| 63 | #define AT91SAM9260_BASE_US0 0xfffb0000 | ||
| 64 | #define AT91SAM9260_BASE_US1 0xfffb4000 | ||
| 65 | #define AT91SAM9260_BASE_US2 0xfffb8000 | ||
| 66 | #define AT91SAM9260_BASE_SSC 0xfffbc000 | ||
| 67 | #define AT91SAM9260_BASE_ISI 0xfffc0000 | ||
| 68 | #define AT91SAM9260_BASE_EMAC 0xfffc4000 | ||
| 69 | #define AT91SAM9260_BASE_SPI0 0xfffc8000 | ||
| 70 | #define AT91SAM9260_BASE_SPI1 0xfffcc000 | ||
| 71 | #define AT91SAM9260_BASE_US3 0xfffd0000 | ||
| 72 | #define AT91SAM9260_BASE_US4 0xfffd4000 | ||
| 73 | #define AT91SAM9260_BASE_US5 0xfffd8000 | ||
| 74 | #define AT91SAM9260_BASE_TCB1 0xfffdc000 | ||
| 75 | #define AT91SAM9260_BASE_TC3 0xfffdc000 | ||
| 76 | #define AT91SAM9260_BASE_TC4 0xfffdc040 | ||
| 77 | #define AT91SAM9260_BASE_TC5 0xfffdc080 | ||
| 78 | #define AT91SAM9260_BASE_ADC 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xffffe800 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 83 | */ | ||
| 84 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 97 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 98 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 99 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 100 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 107 | #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 108 | |||
| 109 | #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 110 | #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ | ||
| 111 | #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 112 | #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ | ||
| 113 | |||
| 114 | #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 115 | |||
| 116 | #if 0 | ||
| 117 | /* | ||
| 118 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 119 | */ | ||
| 120 | |||
| 121 | // TODO: Add | ||
| 122 | |||
| 123 | #endif | ||
| 124 | |||
| 125 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h new file mode 100644 index 000000000000..746d973705bf --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9260_MATRIX_H | ||
| 14 | #define AT91SAM9260_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */ | ||
| 22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 28 | |||
| 29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 55 | |||
| 56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 59 | |||
| 60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
| 61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 70 | #define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ | ||
| 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h new file mode 100644 index 000000000000..8d39672d5b82 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h | |||
| @@ -0,0 +1,292 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9261.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9261_H | ||
| 16 | #define AT91SAM9261_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | ||
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | ||
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | ||
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | ||
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | ||
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | ||
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | ||
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * User Peripheral physical base addresses. | ||
| 49 | */ | ||
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | ||
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | ||
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | ||
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | ||
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | ||
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | ||
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 | ||
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 | ||
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 | ||
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 | ||
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | ||
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | ||
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | ||
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | ||
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | ||
| 65 | #define AT91_BASE_SYS 0xffffea00 | ||
| 66 | |||
| 67 | |||
| 68 | /* | ||
| 69 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 70 | */ | ||
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 86 | |||
| 87 | |||
| 88 | /* | ||
| 89 | * Internal Memory. | ||
| 90 | */ | ||
| 91 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 92 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | ||
| 93 | |||
| 94 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 95 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 96 | |||
| 97 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 98 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | ||
| 99 | |||
| 100 | |||
| 101 | #if 0 | ||
| 102 | /* | ||
| 103 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 104 | */ | ||
| 105 | #define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ | ||
| 106 | #define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ | ||
| 107 | #define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ | ||
| 108 | #define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ | ||
| 109 | #define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ | ||
| 110 | #define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ | ||
| 111 | #define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ | ||
| 112 | #define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ | ||
| 113 | #define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ | ||
| 114 | #define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ | ||
| 115 | #define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ | ||
| 116 | #define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ | ||
| 117 | #define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ | ||
| 118 | #define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ | ||
| 119 | #define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ | ||
| 120 | #define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ | ||
| 121 | #define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ | ||
| 122 | #define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ | ||
| 123 | #define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ | ||
| 124 | #define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ | ||
| 125 | #define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ | ||
| 126 | #define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ | ||
| 127 | #define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ | ||
| 128 | #define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ | ||
| 129 | #define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ | ||
| 130 | #define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ | ||
| 131 | #define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ | ||
| 132 | #define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ | ||
| 133 | #define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ | ||
| 134 | #define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ | ||
| 135 | #define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ | ||
| 136 | #define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ | ||
| 137 | #define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ | ||
| 138 | #define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ | ||
| 139 | #define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ | ||
| 140 | #define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ | ||
| 141 | #define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ | ||
| 142 | #define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ | ||
| 143 | #define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ | ||
| 144 | #define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ | ||
| 145 | #define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ | ||
| 146 | #define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ | ||
| 147 | #define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ | ||
| 148 | #define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ | ||
| 149 | #define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ | ||
| 150 | #define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ | ||
| 151 | #define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ | ||
| 152 | #define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ | ||
| 153 | #define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ | ||
| 154 | #define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ | ||
| 155 | #define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 156 | #define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ | ||
| 157 | #define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 158 | #define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ | ||
| 159 | #define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ | ||
| 160 | #define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ | ||
| 161 | #define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ | ||
| 162 | #define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ | ||
| 163 | #define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ | ||
| 164 | #define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ | ||
| 165 | #define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ | ||
| 166 | #define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ | ||
| 167 | #define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ | ||
| 168 | |||
| 169 | #define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ | ||
| 170 | #define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ | ||
| 171 | #define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ | ||
| 172 | #define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ | ||
| 173 | #define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ | ||
| 174 | #define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ | ||
| 175 | #define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ | ||
| 176 | #define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ | ||
| 177 | #define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ | ||
| 178 | #define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ | ||
| 179 | #define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ | ||
| 180 | #define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ | ||
| 181 | #define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ | ||
| 182 | #define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ | ||
| 183 | #define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ | ||
| 184 | #define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ | ||
| 185 | #define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ | ||
| 186 | #define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ | ||
| 187 | #define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ | ||
| 188 | #define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ | ||
| 189 | #define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ | ||
| 190 | #define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ | ||
| 191 | #define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ | ||
| 192 | #define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ | ||
| 193 | #define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ | ||
| 194 | #define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ | ||
| 195 | #define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ | ||
| 196 | #define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ | ||
| 197 | #define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ | ||
| 198 | #define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ | ||
| 199 | #define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ | ||
| 200 | #define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ | ||
| 201 | #define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ | ||
| 202 | #define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ | ||
| 203 | #define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ | ||
| 204 | #define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ | ||
| 205 | #define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ | ||
| 206 | #define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ | ||
| 207 | #define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ | ||
| 208 | #define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ | ||
| 209 | #define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ | ||
| 210 | #define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ | ||
| 211 | #define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ | ||
| 212 | #define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ | ||
| 213 | #define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ | ||
| 214 | #define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ | ||
| 215 | #define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ | ||
| 216 | #define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ | ||
| 217 | #define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ | ||
| 218 | #define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ | ||
| 219 | #define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ | ||
| 220 | #define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ | ||
| 221 | #define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ | ||
| 222 | #define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ | ||
| 223 | #define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ | ||
| 224 | #define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ | ||
| 225 | #define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ | ||
| 226 | #define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ | ||
| 227 | #define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ | ||
| 228 | #define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ | ||
| 229 | #define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ | ||
| 230 | |||
| 231 | #define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ | ||
| 232 | #define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ | ||
| 233 | #define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ | ||
| 234 | #define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ | ||
| 235 | #define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ | ||
| 236 | #define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ | ||
| 237 | #define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ | ||
| 238 | #define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ | ||
| 239 | #define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ | ||
| 240 | #define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ | ||
| 241 | #define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ | ||
| 242 | #define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ | ||
| 243 | #define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ | ||
| 244 | #define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ | ||
| 245 | #define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ | ||
| 246 | #define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ | ||
| 247 | #define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ | ||
| 248 | #define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ | ||
| 249 | #define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ | ||
| 250 | #define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ | ||
| 251 | #define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ | ||
| 252 | #define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ | ||
| 253 | #define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ | ||
| 254 | #define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ | ||
| 255 | #define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 256 | #define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ | ||
| 257 | #define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 258 | #define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ | ||
| 259 | #define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ | ||
| 260 | #define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ | ||
| 261 | #define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ | ||
| 262 | #define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ | ||
| 263 | #define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ | ||
| 264 | #define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ | ||
| 265 | #define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ | ||
| 266 | #define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ | ||
| 267 | #define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ | ||
| 268 | #define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ | ||
| 269 | #define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ | ||
| 270 | #define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ | ||
| 271 | #define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ | ||
| 272 | #define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ | ||
| 273 | #define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ | ||
| 274 | #define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ | ||
| 275 | #define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ | ||
| 276 | #define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ | ||
| 277 | #define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ | ||
| 278 | #define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ | ||
| 279 | #define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ | ||
| 280 | #define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ | ||
| 281 | #define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ | ||
| 282 | #define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ | ||
| 283 | #define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ | ||
| 284 | #define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ | ||
| 285 | #define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ | ||
| 286 | #define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ | ||
| 287 | #define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ | ||
| 288 | #define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ | ||
| 289 | #define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ | ||
| 290 | #endif | ||
| 291 | |||
| 292 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h new file mode 100644 index 000000000000..270a5dcdf1cd --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9261_MATRIX_H | ||
| 14 | #define AT91SAM9261_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 18 | #define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 19 | |||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 31 | |||
| 32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
| 33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
| 38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
| 45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
| 60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h new file mode 100644 index 000000000000..7d94968b5d57 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | |||
| @@ -0,0 +1,134 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (SMC, SDRAMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM926x_MC_H | ||
| 14 | #define AT91SAM926x_MC_H | ||
| 15 | |||
| 16 | /* SDRAM Controller (SDRAMC) registers */ | ||
| 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
| 18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
| 20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
| 21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
| 22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
| 23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
| 24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
| 25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
| 26 | |||
| 27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
| 28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 29 | |||
| 30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
| 31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
| 47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
| 48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
| 49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
| 50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
| 51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
| 52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
| 53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
| 54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
| 55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
| 56 | |||
| 57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
| 58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
| 60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
| 61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
| 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
| 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ | ||
| 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 70 | |||
| 71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
| 72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
| 73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
| 74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
| 75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
| 76 | |||
| 77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
| 78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
| 79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
| 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
| 81 | |||
| 82 | |||
| 83 | /* Static Memory Controller (SMC) registers */ | ||
| 84 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 85 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| 86 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| 87 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| 88 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| 89 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| 90 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| 91 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| 92 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
| 93 | |||
| 94 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 95 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| 96 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| 97 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| 98 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| 99 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| 100 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| 101 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| 102 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
| 103 | |||
| 104 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 105 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| 106 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| 107 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| 108 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
| 109 | |||
| 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| 113 | #define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ | ||
| 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 5) | ||
| 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 5) | ||
| 116 | #define AT91_SMC_EXNWMODE_READY (3 << 5) | ||
| 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| 118 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 119 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 120 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| 121 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 122 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 123 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 124 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| 125 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| 126 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| 127 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| 128 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| 129 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 130 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 131 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 132 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 133 | |||
| 134 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h index 3cc9aec80f9d..768e0fc6aa2f 100644 --- a/include/asm-arm/arch-at91rm9200/board.h +++ b/include/asm-arm/arch-at91rm9200/board.h | |||
| @@ -48,13 +48,14 @@ struct at91_cf_data { | |||
| 48 | u8 det_pin; /* Card detect */ | 48 | u8 det_pin; /* Card detect */ |
| 49 | u8 vcc_pin; /* power switching */ | 49 | u8 vcc_pin; /* power switching */ |
| 50 | u8 rst_pin; /* card reset */ | 50 | u8 rst_pin; /* card reset */ |
| 51 | u8 chipselect; /* EBI Chip Select number */ | ||
| 51 | }; | 52 | }; |
| 52 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | 53 | extern void __init at91_add_device_cf(struct at91_cf_data *data); |
| 53 | 54 | ||
| 54 | /* MMC / SD */ | 55 | /* MMC / SD */ |
| 55 | struct at91_mmc_data { | 56 | struct at91_mmc_data { |
| 56 | u8 det_pin; /* card detect IRQ */ | 57 | u8 det_pin; /* card detect IRQ */ |
| 57 | unsigned is_b:1; /* uses B side (vs A) */ | 58 | unsigned slot_b:1; /* uses Slot B */ |
| 58 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ | 59 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ |
| 59 | u8 wp_pin; /* (SD) writeprotect detect */ | 60 | u8 wp_pin; /* (SD) writeprotect detect */ |
| 60 | u8 vcc_pin; /* power switching (high == on) */ | 61 | u8 vcc_pin; /* power switching (high == on) */ |
| @@ -81,7 +82,8 @@ struct at91_nand_data { | |||
| 81 | u8 rdy_pin; /* ready/busy */ | 82 | u8 rdy_pin; /* ready/busy */ |
| 82 | u8 ale; /* address line number connected to ALE */ | 83 | u8 ale; /* address line number connected to ALE */ |
| 83 | u8 cle; /* address line number connected to CLE */ | 84 | u8 cle; /* address line number connected to CLE */ |
| 84 | struct mtd_partition* (*partition_info)(int, int*); | 85 | u8 bus_width_16; /* buswidth is 16 bit */ |
| 86 | struct mtd_partition* (*partition_info)(int, int*); | ||
| 85 | }; | 87 | }; |
| 86 | extern void __init at91_add_device_nand(struct at91_nand_data *data); | 88 | extern void __init at91_add_device_nand(struct at91_nand_data *data); |
| 87 | 89 | ||
diff --git a/include/asm-arm/arch-at91rm9200/cpu.h b/include/asm-arm/arch-at91rm9200/cpu.h new file mode 100644 index 000000000000..6f8d09b08692 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/cpu.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91rm9200/cpu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_CPU_H | ||
| 14 | #define __ASM_ARCH_CPU_H | ||
| 15 | |||
| 16 | #include <asm/hardware.h> | ||
| 17 | #include <asm/arch/at91_dbgu.h> | ||
| 18 | |||
| 19 | |||
| 20 | #define ARCH_ID_AT91RM9200 0x09290780 | ||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | ||
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | ||
| 23 | |||
| 24 | |||
| 25 | static inline unsigned long at91_cpu_identify(void) | ||
| 26 | { | ||
| 27 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | ||
| 28 | } | ||
| 29 | |||
| 30 | |||
| 31 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 32 | #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) | ||
| 33 | #else | ||
| 34 | #define cpu_is_at91rm9200() (0) | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef CONFIG_ARCH_AT91SAM9260 | ||
| 38 | #define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260) | ||
| 39 | #else | ||
| 40 | #define cpu_is_at91sam9260() (0) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifdef CONFIG_ARCH_AT91SAM9261 | ||
| 44 | #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) | ||
| 45 | #else | ||
| 46 | #define cpu_is_at91sam9261() (0) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S index f496b54c4c3e..85cdadf26634 100644 --- a/include/asm-arm/arch-at91rm9200/debug-macro.S +++ b/include/asm-arm/arch-at91rm9200/debug-macro.S | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <asm/hardware.h> | 14 | #include <asm/hardware.h> |
| 15 | #include <asm/arch/at91_dbgu.h> | ||
| 15 | 16 | ||
| 16 | .macro addruart,rx | 17 | .macro addruart,rx |
| 17 | mrc p15, 0, \rx, c1, c0 | 18 | mrc p15, 0, \rx, c1, c0 |
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S index 61a326e94909..57248a796472 100644 --- a/include/asm-arm/arch-at91rm9200/entry-macro.S +++ b/include/asm-arm/arch-at91rm9200/entry-macro.S | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <asm/hardware.h> | 13 | #include <asm/hardware.h> |
| 14 | #include <asm/arch/at91_aic.h> | ||
| 14 | 15 | ||
| 15 | .macro disable_fiq | 16 | .macro disable_fiq |
| 16 | .endm | 17 | .endm |
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 9ca4cc9c0b2e..9ea5bfe06320 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h | |||
| @@ -16,8 +16,16 @@ | |||
| 16 | 16 | ||
| 17 | #include <asm/sizes.h> | 17 | #include <asm/sizes.h> |
| 18 | 18 | ||
| 19 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 19 | #include <asm/arch/at91rm9200.h> | 20 | #include <asm/arch/at91rm9200.h> |
| 20 | #include <asm/arch/at91rm9200_sys.h> | 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) |
| 22 | #include <asm/arch/at91sam9260.h> | ||
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 24 | #include <asm/arch/at91sam9261.h> | ||
| 25 | #else | ||
| 26 | #error "Unsupported AT91 processor" | ||
| 27 | #endif | ||
| 28 | |||
| 21 | 29 | ||
| 22 | /* | 30 | /* |
| 23 | * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF | 31 | * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF |
| @@ -34,29 +42,27 @@ | |||
| 34 | * Virtual to Physical Address mapping for IO devices. | 42 | * Virtual to Physical Address mapping for IO devices. |
| 35 | */ | 43 | */ |
| 36 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) | 44 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) |
| 37 | #define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI) | ||
| 38 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) | 45 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) |
| 39 | #define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI) | ||
| 40 | #define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI) | ||
| 41 | #define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP) | ||
| 42 | 46 | ||
| 43 | /* Internal SRAM is mapped below the IO devices */ | 47 | /* Internal SRAM is mapped below the IO devices */ |
| 44 | #define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE) | 48 | #define AT91_SRAM_MAX SZ_1M |
| 49 | #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) | ||
| 45 | 50 | ||
| 46 | /* Serial ports */ | 51 | /* Serial ports */ |
| 47 | #define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */ | 52 | #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ |
| 48 | 53 | ||
| 49 | /* FLASH */ | 54 | /* External Memory Map */ |
| 50 | #define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */ | 55 | #define AT91_CHIPSELECT_0 0x10000000 |
| 56 | #define AT91_CHIPSELECT_1 0x20000000 | ||
| 57 | #define AT91_CHIPSELECT_2 0x30000000 | ||
| 58 | #define AT91_CHIPSELECT_3 0x40000000 | ||
| 59 | #define AT91_CHIPSELECT_4 0x50000000 | ||
| 60 | #define AT91_CHIPSELECT_5 0x60000000 | ||
| 61 | #define AT91_CHIPSELECT_6 0x70000000 | ||
| 62 | #define AT91_CHIPSELECT_7 0x80000000 | ||
| 51 | 63 | ||
| 52 | /* SDRAM */ | 64 | /* SDRAM */ |
| 53 | #define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */ | 65 | #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 |
| 54 | |||
| 55 | /* SmartMedia */ | ||
| 56 | #define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */ | ||
| 57 | |||
| 58 | /* Compact Flash */ | ||
| 59 | #define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ | ||
| 60 | 66 | ||
| 61 | /* Clocks */ | 67 | /* Clocks */ |
| 62 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | 68 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ |
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h index 763cb96c418b..c0679eaefaf2 100644 --- a/include/asm-arm/arch-at91rm9200/irqs.h +++ b/include/asm-arm/arch-at91rm9200/irqs.h | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | 21 | #ifndef __ASM_ARCH_IRQS_H |
| 22 | #define __ASM_ARCH_IRQS_H | 22 | #define __ASM_ARCH_IRQS_H |
| 23 | 23 | ||
| 24 | #include <asm/arch/at91_aic.h> | ||
| 25 | |||
| 24 | #define NR_AIC_IRQS 32 | 26 | #define NR_AIC_IRQS 32 |
| 25 | 27 | ||
| 26 | 28 | ||
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h index 8a2ff472e4cf..9c67130603b2 100644 --- a/include/asm-arm/arch-at91rm9200/system.h +++ b/include/asm-arm/arch-at91rm9200/system.h | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #define __ASM_ARCH_SYSTEM_H | 22 | #define __ASM_ARCH_SYSTEM_H |
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/arch/at91_st.h> | ||
| 26 | #include <asm/arch/at91_dbgu.h> | ||
| 25 | 27 | ||
| 26 | static inline void arch_idle(void) | 28 | static inline void arch_idle(void) |
| 27 | { | 29 | { |
| @@ -39,21 +41,13 @@ static inline void arch_idle(void) | |||
| 39 | cpu_do_idle(); | 41 | cpu_do_idle(); |
| 40 | } | 42 | } |
| 41 | 43 | ||
| 42 | static inline void arch_reset(char mode) | 44 | void (*at91_arch_reset)(void); |
| 43 | { | ||
| 44 | /* | ||
| 45 | * Perform a hardware reset with the use of the Watchdog timer. | ||
| 46 | */ | ||
| 47 | at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); | ||
| 48 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); | ||
| 49 | } | ||
| 50 | |||
| 51 | #define ARCH_ID_AT91RM9200 0x09200080 | ||
| 52 | #define ARCH_ID_AT91SAM9261 0x019000a0 | ||
| 53 | 45 | ||
| 54 | static inline unsigned long arch_identify(void) | 46 | static inline void arch_reset(char mode) |
| 55 | { | 47 | { |
| 56 | return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH); | 48 | /* call the CPU-specific reset function */ |
| 49 | if (at91_arch_reset) | ||
| 50 | (at91_arch_reset)(); | ||
| 57 | } | 51 | } |
| 58 | 52 | ||
| 59 | #endif | 53 | #endif |
diff --git a/include/asm-arm/arch-at91rm9200/timex.h b/include/asm-arm/arch-at91rm9200/timex.h index 88687cefe6eb..faeca45a8d44 100644 --- a/include/asm-arm/arch-at91rm9200/timex.h +++ b/include/asm-arm/arch-at91rm9200/timex.h | |||
| @@ -23,6 +23,15 @@ | |||
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | 25 | ||
| 26 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 27 | |||
| 26 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | 28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) |
| 27 | 29 | ||
| 30 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) | ||
| 31 | |||
| 32 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 33 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
| 28 | #endif | 37 | #endif |
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h index ec7811ab0a52..34b4b93fa015 100644 --- a/include/asm-arm/arch-at91rm9200/uncompress.h +++ b/include/asm-arm/arch-at91rm9200/uncompress.h | |||
| @@ -22,11 +22,11 @@ | |||
| 22 | #define __ASM_ARCH_UNCOMPRESS_H | 22 | #define __ASM_ARCH_UNCOMPRESS_H |
| 23 | 23 | ||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/arch/at91_dbgu.h> | ||
| 25 | 26 | ||
| 26 | /* | 27 | /* |
| 27 | * The following code assumes the serial port has already been | 28 | * The following code assumes the serial port has already been |
| 28 | * initialized by the bootloader. We search for the first enabled | 29 | * initialized by the bootloader. If you didn't setup a port in |
| 29 | * port in the most probable order. If you didn't setup a port in | ||
| 30 | * your bootloader then nothing will appear (which might be desired). | 30 | * your bootloader then nothing will appear (which might be desired). |
| 31 | * | 31 | * |
| 32 | * This does not append a newline | 32 | * This does not append a newline |
diff --git a/include/asm-arm/arch-at91rm9200/vmalloc.h b/include/asm-arm/arch-at91rm9200/vmalloc.h index 4c367eb57f47..0a23b8c562b9 100644 --- a/include/asm-arm/arch-at91rm9200/vmalloc.h +++ b/include/asm-arm/arch-at91rm9200/vmalloc.h | |||
| @@ -21,6 +21,6 @@ | |||
| 21 | #ifndef __ASM_ARCH_VMALLOC_H | 21 | #ifndef __ASM_ARCH_VMALLOC_H |
| 22 | #define __ASM_ARCH_VMALLOC_H | 22 | #define __ASM_ARCH_VMALLOC_H |
| 23 | 23 | ||
| 24 | #define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK) | 24 | #define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) |
| 25 | 25 | ||
| 26 | #endif | 26 | #endif |