[ARM] 3865/1: AT91RM9200 header updates

This is more preparation for adding support for the new Atmel AT91SAM9
processors.

Changes include:
- Replace AT91_BASE_* with AT91RM9200_BASE_*
- Replace AT91_ID_* with AT91RM9200_ID_*
- ROM, SRAM and UHP address definitions moved to at91rm9200.h.
- The raw AT91_P[ABCD]_* definitions are now depreciated in favour of
the GPIO API.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 15 insertions, 22 deletions

diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..878e65f369bf 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,27 +34,23 @@
  * Virtual to Physical Address mapping for IO devices.
  */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91_BASE_SPI)
-#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91_BASE_SSC2)
-#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91_BASE_SSC1)
-#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91_BASE_SSC0)
-#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91_BASE_US3)
-#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91_BASE_US2)
-#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91_BASE_US1)
-#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91_BASE_US0)
-#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91_BASE_EMAC)
-#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91_BASE_TWI)
-#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91_BASE_MCI)
-#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91_BASE_UDP)
-#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91_BASE_TCB1)
-#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
-
-/* Internal SRAM */
-#define AT91_SRAM_BASE          0x00200000      /* Internal SRAM base address */
-#define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
+#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91RM9200_BASE_SPI)
+#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91RM9200_BASE_SSC2)
+#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91RM9200_BASE_SSC1)
+#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91RM9200_BASE_SSC0)
+#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91RM9200_BASE_US3)
+#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91RM9200_BASE_US2)
+#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91RM9200_BASE_US1)
+#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91RM9200_BASE_US0)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
+#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91RM9200_BASE_TWI)
+#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91RM9200_BASE_MCI)
+#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91RM9200_BASE_UDP)
+#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91RM9200_BASE_TCB1)
+#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91RM9200_BASE_TCB0)
 
  /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
+#define AT91_SRAM_VIRT_BASE     (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
 
 /* Serial ports */
 #define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
@@ -71,9 +67,6 @@
 /* Compact Flash */
 #define AT91_CF_BASE            0x50000000      /* NCS4-NCS6: Compact Flash physical base address */
 
-/* Multi-Master Memory controller */
-#define AT91_UHP_BASE           0x00300000      /* USB Host controller */
-
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */