diff options
| author | Andrew Victor <linux@maxim.org.za> | 2008-04-02 16:44:44 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-04 04:52:20 -0400 |
| commit | d7a2415f7a48ce4fc16cc769f96d0df818648837 (patch) | |
| tree | bda7fbcc179840009f365a7416fe83f53a739110 /include/asm-arm/arch-at91 | |
| parent | 3ef2fb426775fc2ae19b70c318dbdf4a0aeeced7 (diff) | |
[ARM] 4904/1: [AT91] Pass ECC controller to NAND driver
On AT91 processors that include an ECC controller, pass its base
address to the NAND driver via platform_device resources.
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_ecc.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h index ff93df516d6d..1e5a8caca2d1 100644 --- a/include/asm-arm/arch-at91/at91_ecc.h +++ b/include/asm-arm/arch-at91/at91_ecc.h | |||
| @@ -13,26 +13,26 @@ | |||
| 13 | #ifndef AT91_ECC_H | 13 | #ifndef AT91_ECC_H |
| 14 | #define AT91_ECC_H | 14 | #define AT91_ECC_H |
| 15 | 15 | ||
| 16 | #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ | 16 | #define AT91_ECC_CR 0x00 /* Control register */ |
| 17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ | 17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ |
| 18 | 18 | ||
| 19 | #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ | 19 | #define AT91_ECC_MR 0x04 /* Mode register */ |
| 20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ | 20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ |
| 21 | #define AT91_ECC_PAGESIZE_528 (0) | 21 | #define AT91_ECC_PAGESIZE_528 (0) |
| 22 | #define AT91_ECC_PAGESIZE_1056 (1) | 22 | #define AT91_ECC_PAGESIZE_1056 (1) |
| 23 | #define AT91_ECC_PAGESIZE_2112 (2) | 23 | #define AT91_ECC_PAGESIZE_2112 (2) |
| 24 | #define AT91_ECC_PAGESIZE_4224 (3) | 24 | #define AT91_ECC_PAGESIZE_4224 (3) |
| 25 | 25 | ||
| 26 | #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ | 26 | #define AT91_ECC_SR 0x08 /* Status register */ |
| 27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ | 27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ |
| 28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ | 28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ |
| 29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ | 29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ |
| 30 | 30 | ||
| 31 | #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ | 31 | #define AT91_ECC_PR 0x0c /* Parity register */ |
| 32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ | 32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ |
| 33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ | 33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ |
| 34 | 34 | ||
| 35 | #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ | 35 | #define AT91_ECC_NPR 0x10 /* NParity register */ |
| 36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ | 36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ |
| 37 | 37 | ||
| 38 | #endif | 38 | #endif |