diff options
author | Andrew Victor <andrew@sanpeople.com> | 2007-11-20 07:34:56 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-26 10:00:30 -0500 |
commit | 9ebbec27da6d7f4762b73985ac4929acf061d48b (patch) | |
tree | 55dd7f9c5d8e9a06a974f1799a55784566472ade /include/asm-arm/arch-at91 | |
parent | 7cbed2b507efd1bb19a574b8db14d5aad5936d6d (diff) |
[ARM] 4657/1: AT91: Header definition update
Add definitions of registers / bits found on some AT91SAM9 processors
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91')
-rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91_twi.h | 11 | ||||
-rw-r--r-- | include/asm-arm/arch-at91/at91sam9260_matrix.h | 2 |
3 files changed, 15 insertions, 2 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 33ff5b6798ee..34804eaab4f2 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h | |||
@@ -37,7 +37,9 @@ | |||
37 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | 37 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
38 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | 38 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
39 | 39 | ||
40 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | 40 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */ |
41 | |||
42 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | ||
41 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 43 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
42 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | 44 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ |
43 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | 45 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h index ca9a90733456..f9f2e3cd95c5 100644 --- a/include/asm-arm/arch-at91/at91_twi.h +++ b/include/asm-arm/arch-at91/at91_twi.h | |||
@@ -21,6 +21,8 @@ | |||
21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ | 21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ |
22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ | 22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ |
23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ | 23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ |
24 | #define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */ | ||
25 | #define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */ | ||
24 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ | 26 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ |
25 | 27 | ||
26 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ | 28 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ |
@@ -32,6 +34,9 @@ | |||
32 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ | 34 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ |
33 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ | 35 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ |
34 | 36 | ||
37 | #define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */ | ||
38 | #define AT91_TWI_SADR (0x7f << 16) /* Slave Address */ | ||
39 | |||
35 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ | 40 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ |
36 | 41 | ||
37 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ | 42 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ |
@@ -43,9 +48,15 @@ | |||
43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | 48 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ |
44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | 49 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ |
45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | 50 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ |
51 | #define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */ | ||
52 | #define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */ | ||
53 | #define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */ | ||
46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ | 54 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ |
47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ | 55 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ |
48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | 56 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ |
57 | #define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */ | ||
58 | #define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */ | ||
59 | #define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */ | ||
49 | 60 | ||
50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | 61 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ |
51 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ | 62 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ |
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h index aacb1e976422..a8e9fec6c735 100644 --- a/include/asm-arm/arch-at91/at91sam9260_matrix.h +++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h | |||
@@ -67,7 +67,7 @@ | |||
67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) |
69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) |
70 | #define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ | 70 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) |
72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |