diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
| commit | 59b8175c771040afcd4ad67022b0cc80c216b866 (patch) | |
| tree | 4ef5935bee1e342716d49b9d4b99e3fa835526e6 /include/asm-arm/arch-at91 | |
| parent | 920841d8d1d61bc12b43f95a579a5374f6d98f81 (diff) | |
| parent | 3b0eb4a195a124567cd0dd6f700f8388def542c6 (diff) | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
[ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports
[ARM] 4140/1: AACI stability add ac97 timeout and retries
[ARM] 4139/1: AACI record support
[ARM] 4138/1: AACI: multiple channel support for IRQ handling
[ARM] 4211/1: Provide a defconfig for ns9xxx
[ARM] 4210/1: base for new machine type "NetSilicon NS9360"
[ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
[ARM] 4221/1: S3C2443: DMA support
[ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
[ARM] 4219/1: S3C2443: DMA source definitions
[ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
[ARM] 4217/1: S3C24XX: remove the dma channel show at startup
[ARM] 4090/2: avoid clash between PXA and SA1111 defines
[ARM] 4216/1: add .gitignore entries for ARM specific files
[ARM] 4214/2: S3C2410: Add Armzone QT2410
[ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw
[ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
[ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
[ARM] 4137/1: Add kexec support
[ARM] 4201/1: SMP barriers pair needed for the secondary boot process
...
Fix up conflict due to typedef removal in sound/arm/aaci.h
Diffstat (limited to 'include/asm-arm/arch-at91')
42 files changed, 3687 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91_aic.h b/include/asm-arm/arch-at91/at91_aic.h new file mode 100644 index 000000000000..df44c12a12d4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_aic.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_aic.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_AIC_H | ||
| 17 | #define AT91_AIC_H | ||
| 18 | |||
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 26 | |||
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 32 | |||
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 38 | |||
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 48 | |||
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h new file mode 100644 index 000000000000..b0369e176f7b --- /dev/null +++ b/include/asm-arm/arch-at91/at91_dbgu.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_dbgu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Debug Unit (DBGU) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_DBGU_H | ||
| 17 | #define AT91_DBGU_H | ||
| 18 | |||
| 19 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 20 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 21 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 22 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 23 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 24 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 25 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 26 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 27 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 28 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 29 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 30 | |||
| 31 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 32 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 33 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 34 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 35 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 36 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 37 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 38 | #define AT91_CIDR_SRAMSIZ_1K (1 << 16) | ||
| 39 | #define AT91_CIDR_SRAMSIZ_2K (2 << 16) | ||
| 40 | #define AT91_CIDR_SRAMSIZ_112K (4 << 16) | ||
| 41 | #define AT91_CIDR_SRAMSIZ_4K (5 << 16) | ||
| 42 | #define AT91_CIDR_SRAMSIZ_80K (6 << 16) | ||
| 43 | #define AT91_CIDR_SRAMSIZ_160K (7 << 16) | ||
| 44 | #define AT91_CIDR_SRAMSIZ_8K (8 << 16) | ||
| 45 | #define AT91_CIDR_SRAMSIZ_16K (9 << 16) | ||
| 46 | #define AT91_CIDR_SRAMSIZ_32K (10 << 16) | ||
| 47 | #define AT91_CIDR_SRAMSIZ_64K (11 << 16) | ||
| 48 | #define AT91_CIDR_SRAMSIZ_128K (12 << 16) | ||
| 49 | #define AT91_CIDR_SRAMSIZ_256K (13 << 16) | ||
| 50 | #define AT91_CIDR_SRAMSIZ_96K (14 << 16) | ||
| 51 | #define AT91_CIDR_SRAMSIZ_512K (15 << 16) | ||
| 52 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 53 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 54 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 55 | |||
| 56 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
| 57 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
| 58 | |||
| 59 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h new file mode 100644 index 000000000000..ff93df516d6d --- /dev/null +++ b/include/asm-arm/arch-at91/at91_ecc.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_ecc.h | ||
| 3 | * | ||
| 4 | * Error Corrected Code Controller (ECC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_ECC_H | ||
| 14 | #define AT91_ECC_H | ||
| 15 | |||
| 16 | #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ | ||
| 17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ | ||
| 18 | |||
| 19 | #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ | ||
| 20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ | ||
| 21 | #define AT91_ECC_PAGESIZE_528 (0) | ||
| 22 | #define AT91_ECC_PAGESIZE_1056 (1) | ||
| 23 | #define AT91_ECC_PAGESIZE_2112 (2) | ||
| 24 | #define AT91_ECC_PAGESIZE_4224 (3) | ||
| 25 | |||
| 26 | #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ | ||
| 27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ | ||
| 28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ | ||
| 29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ | ||
| 30 | |||
| 31 | #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ | ||
| 32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ | ||
| 33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ | ||
| 34 | |||
| 35 | #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ | ||
| 36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h new file mode 100644 index 000000000000..ab040a40d37b --- /dev/null +++ b/include/asm-arm/arch-at91/at91_lcdc.h | |||
| @@ -0,0 +1,148 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_lcdc.h | ||
| 3 | * | ||
| 4 | * LCD Controller (LCDC). | ||
| 5 | * Based on AT91SAM9261 datasheet revision E. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_LCDC_H | ||
| 14 | #define AT91_LCDC_H | ||
| 15 | |||
| 16 | #define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ | ||
| 17 | #define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ | ||
| 18 | #define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ | ||
| 19 | #define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ | ||
| 20 | #define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ | ||
| 21 | #define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ | ||
| 22 | |||
| 23 | #define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ | ||
| 24 | #define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ | ||
| 25 | #define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ | ||
| 26 | |||
| 27 | #define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ | ||
| 28 | #define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ | ||
| 29 | #define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ | ||
| 30 | #define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ | ||
| 31 | |||
| 32 | #define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ | ||
| 33 | #define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ | ||
| 34 | #define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ | ||
| 35 | #define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ | ||
| 36 | |||
| 37 | #define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ | ||
| 38 | #define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ | ||
| 39 | #define AT91_LCDC_DISTYPE_STNMONO (0 << 0) | ||
| 40 | #define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) | ||
| 41 | #define AT91_LCDC_DISTYPE_TFT (2 << 0) | ||
| 42 | #define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ | ||
| 43 | #define AT91_LCDC_SCANMOD_SINGLE (0 << 2) | ||
| 44 | #define AT91_LCDC_SCANMOD_DUAL (1 << 2) | ||
| 45 | #define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ | ||
| 46 | #define AT91_LCDC_IFWIDTH_4 (0 << 3) | ||
| 47 | #define AT91_LCDC_IFWIDTH_8 (1 << 3) | ||
| 48 | #define AT91_LCDC_IFWIDTH_16 (2 << 3) | ||
| 49 | #define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ | ||
| 50 | #define AT91_LCDC_PIXELSIZE_1 (0 << 5) | ||
| 51 | #define AT91_LCDC_PIXELSIZE_2 (1 << 5) | ||
| 52 | #define AT91_LCDC_PIXELSIZE_4 (2 << 5) | ||
| 53 | #define AT91_LCDC_PIXELSIZE_8 (3 << 5) | ||
| 54 | #define AT91_LCDC_PIXELSIZE_16 (4 << 5) | ||
| 55 | #define AT91_LCDC_PIXELSIZE_24 (5 << 5) | ||
| 56 | #define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ | ||
| 57 | #define AT91_LCDC_INVVD_NORMAL (0 << 8) | ||
| 58 | #define AT91_LCDC_INVVD_INVERTED (1 << 8) | ||
| 59 | #define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ | ||
| 60 | #define AT91_LCDC_INVFRAME_NORMAL (0 << 9) | ||
| 61 | #define AT91_LCDC_INVFRAME_INVERTED (1 << 9) | ||
| 62 | #define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ | ||
| 63 | #define AT91_LCDC_INVLINE_NORMAL (0 << 10) | ||
| 64 | #define AT91_LCDC_INVLINE_INVERTED (1 << 10) | ||
| 65 | #define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ | ||
| 66 | #define AT91_LCDC_INVCLK_NORMAL (0 << 11) | ||
| 67 | #define AT91_LCDC_INVCLK_INVERTED (1 << 11) | ||
| 68 | #define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ | ||
| 69 | #define AT91_LCDC_INVDVAL_NORMAL (0 << 12) | ||
| 70 | #define AT91_LCDC_INVDVAL_INVERTED (1 << 12) | ||
| 71 | #define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ | ||
| 72 | #define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) | ||
| 73 | #define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) | ||
| 74 | #define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ | ||
| 75 | #define AT91_LCDC_MEMOR_BIG (0 << 31) | ||
| 76 | #define AT91_LCDC_MEMOR_LITTLE (1 << 31) | ||
| 77 | |||
| 78 | #define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ | ||
| 79 | #define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ | ||
| 80 | #define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ | ||
| 81 | #define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ | ||
| 82 | #define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ | ||
| 83 | |||
| 84 | #define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ | ||
| 85 | #define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ | ||
| 86 | #define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ | ||
| 87 | #define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ | ||
| 88 | |||
| 89 | #define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ | ||
| 90 | #define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ | ||
| 91 | #define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ | ||
| 92 | |||
| 93 | #define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ | ||
| 94 | #define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ | ||
| 95 | |||
| 96 | #define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ | ||
| 97 | #define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ | ||
| 98 | #define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ | ||
| 99 | #define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ | ||
| 100 | #define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ | ||
| 101 | #define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ | ||
| 102 | #define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ | ||
| 103 | #define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ | ||
| 104 | #define AT91_LCDC_DP1_2_VAL (0xff) | ||
| 105 | #define AT91_LCDC_DP4_7_VAL (0xfffffff) | ||
| 106 | #define AT91_LCDC_DP3_5_VAL (0xfffff) | ||
| 107 | #define AT91_LCDC_DP2_3_VAL (0xfff) | ||
| 108 | #define AT91_LCDC_DP5_7_VAL (0xfffffff) | ||
| 109 | #define AT91_LCDC_DP3_4_VAL (0xffff) | ||
| 110 | #define AT91_LCDC_DP4_5_VAL (0xfffff) | ||
| 111 | #define AT91_LCDC_DP6_7_VAL (0xfffffff) | ||
| 112 | |||
| 113 | #define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ | ||
| 114 | #define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ | ||
| 115 | #define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ | ||
| 116 | #define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ | ||
| 117 | |||
| 118 | #define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ | ||
| 119 | #define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ | ||
| 120 | #define AT91_LCDC_PS_DIV1 (0 << 0) | ||
| 121 | #define AT91_LCDC_PS_DIV2 (1 << 0) | ||
| 122 | #define AT91_LCDC_PS_DIV4 (2 << 0) | ||
| 123 | #define AT91_LCDC_PS_DIV8 (3 << 0) | ||
| 124 | #define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ | ||
| 125 | #define AT91_LCDC_POL_NEGATIVE (0 << 2) | ||
| 126 | #define AT91_LCDC_POL_POSITIVE (1 << 2) | ||
| 127 | #define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ | ||
| 128 | #define AT91_LCDC_ENA_PWMDISABLE (0 << 3) | ||
| 129 | #define AT91_LCDC_ENA_PWMENABLE (1 << 3) | ||
| 130 | |||
| 131 | #define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ | ||
| 132 | #define AT91_LCDC_CVAL (0xff) /* PWM compare value */ | ||
| 133 | |||
| 134 | #define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ | ||
| 135 | #define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ | ||
| 136 | #define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ | ||
| 137 | #define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ | ||
| 138 | #define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ | ||
| 139 | #define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ | ||
| 140 | #define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ | ||
| 141 | #define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ | ||
| 142 | #define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ | ||
| 143 | #define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ | ||
| 144 | #define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ | ||
| 145 | |||
| 146 | #define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ | ||
| 147 | |||
| 148 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h new file mode 100644 index 000000000000..40a9876b661a --- /dev/null +++ b/include/asm-arm/arch-at91/at91_mci.h | |||
| @@ -0,0 +1,106 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_mci.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * MultiMedia Card Interface (MCI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision F. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_MCI_H | ||
| 17 | #define AT91_MCI_H | ||
| 18 | |||
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ | ||
| 21 | #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ | ||
| 22 | #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ | ||
| 23 | #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ | ||
| 24 | #define AT91_MCI_SWRST (1 << 7) /* Software Reset */ | ||
| 25 | |||
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ | ||
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ | ||
| 28 | #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ | ||
| 29 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ | ||
| 30 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ | ||
| 31 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ | ||
| 32 | |||
| 33 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ | ||
| 34 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ | ||
| 35 | #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ | ||
| 36 | #define AT91_MCI_DTOMUL_1 (0 << 4) | ||
| 37 | #define AT91_MCI_DTOMUL_16 (1 << 4) | ||
| 38 | #define AT91_MCI_DTOMUL_128 (2 << 4) | ||
| 39 | #define AT91_MCI_DTOMUL_256 (3 << 4) | ||
| 40 | #define AT91_MCI_DTOMUL_1K (4 << 4) | ||
| 41 | #define AT91_MCI_DTOMUL_4K (5 << 4) | ||
| 42 | #define AT91_MCI_DTOMUL_64K (6 << 4) | ||
| 43 | #define AT91_MCI_DTOMUL_1M (7 << 4) | ||
| 44 | |||
| 45 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ | ||
| 46 | #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ | ||
| 47 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ | ||
| 48 | |||
| 49 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ | ||
| 50 | |||
| 51 | #define AT91_MCI_CMDR 0x14 /* Command Register */ | ||
| 52 | #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ | ||
| 53 | #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ | ||
| 54 | #define AT91_MCI_RSPTYP_NONE (0 << 6) | ||
| 55 | #define AT91_MCI_RSPTYP_48 (1 << 6) | ||
| 56 | #define AT91_MCI_RSPTYP_136 (2 << 6) | ||
| 57 | #define AT91_MCI_SPCMD (7 << 8) /* Special Command */ | ||
| 58 | #define AT91_MCI_SPCMD_NONE (0 << 8) | ||
| 59 | #define AT91_MCI_SPCMD_INIT (1 << 8) | ||
| 60 | #define AT91_MCI_SPCMD_SYNC (2 << 8) | ||
| 61 | #define AT91_MCI_SPCMD_ICMD (4 << 8) | ||
| 62 | #define AT91_MCI_SPCMD_IRESP (5 << 8) | ||
| 63 | #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ | ||
| 64 | #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ | ||
| 65 | #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ | ||
| 66 | #define AT91_MCI_TRCMD_NONE (0 << 16) | ||
| 67 | #define AT91_MCI_TRCMD_START (1 << 16) | ||
| 68 | #define AT91_MCI_TRCMD_STOP (2 << 16) | ||
| 69 | #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ | ||
| 70 | #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ | ||
| 71 | #define AT91_MCI_TRTYP_BLOCK (0 << 19) | ||
| 72 | #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) | ||
| 73 | #define AT91_MCI_TRTYP_STREAM (2 << 19) | ||
| 74 | |||
| 75 | #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ | ||
| 76 | #define AT91_MCR_RDR 0x30 /* Receive Data Register */ | ||
| 77 | #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ | ||
| 78 | |||
| 79 | #define AT91_MCI_SR 0x40 /* Status Register */ | ||
| 80 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ | ||
| 81 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ | ||
| 82 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ | ||
| 83 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ | ||
| 84 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ | ||
| 85 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ | ||
| 86 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ | ||
| 87 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ | ||
| 88 | #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ | ||
| 89 | #define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ | ||
| 90 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ | ||
| 91 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ | ||
| 92 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ | ||
| 93 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ | ||
| 94 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ | ||
| 95 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ | ||
| 96 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ | ||
| 97 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ | ||
| 98 | #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ | ||
| 99 | #define AT91_MCI_OVRE (1 << 30) /* Overrun */ | ||
| 100 | #define AT91_MCI_UNRE (1 << 31) /* Underrun */ | ||
| 101 | |||
| 102 | #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ | ||
| 103 | #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ | ||
| 104 | #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h new file mode 100644 index 000000000000..84c3866d309f --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pio.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Parallel I/O Controller (PIO) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PIO_H | ||
| 17 | #define AT91_PIO_H | ||
| 18 | |||
| 19 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 20 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 21 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 22 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 23 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 24 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 25 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 26 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 27 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 28 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 29 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 30 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 31 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 32 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 33 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 34 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 35 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 36 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 37 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 38 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 39 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 40 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 41 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 42 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 43 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 44 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 45 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 46 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 47 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h new file mode 100644 index 000000000000..5026325a5ae4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pit.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pit.h | ||
| 3 | * | ||
| 4 | * Periodic Interval Timer (PIT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_PIT_H | ||
| 14 | #define AT91_PIT_H | ||
| 15 | |||
| 16 | #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | ||
| 18 | #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | ||
| 19 | #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | ||
| 20 | |||
| 21 | #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | ||
| 22 | #define AT91_PIT_PITS (1 << 0) /* Timer Status */ | ||
| 23 | |||
| 24 | #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | ||
| 25 | #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | ||
| 26 | #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | ||
| 27 | #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h new file mode 100644 index 000000000000..33ff5b6798ee --- /dev/null +++ b/include/asm-arm/arch-at91/at91_pmc.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Power Management Controller (PMC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PMC_H | ||
| 17 | #define AT91_PMC_H | ||
| 18 | |||
| 19 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 20 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 21 | |||
| 22 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
| 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
| 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
| 28 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
| 29 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 30 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 31 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 32 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 33 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
| 34 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
| 35 | |||
| 36 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 37 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 38 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 39 | |||
| 40 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ | ||
| 41 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 42 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | ||
| 43 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 44 | |||
| 45 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 46 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 47 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 48 | |||
| 49 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 50 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 51 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 52 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 53 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 54 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 55 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 56 | |||
| 57 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 58 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 59 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 60 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 61 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 62 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 63 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 64 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 65 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 66 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 67 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 68 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 69 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 70 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 71 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 72 | #define AT91_PMC_MDIV_1 (0 << 8) | ||
| 73 | #define AT91_PMC_MDIV_2 (1 << 8) | ||
| 74 | #define AT91_PMC_MDIV_3 (2 << 8) | ||
| 75 | #define AT91_PMC_MDIV_4 (3 << 8) | ||
| 76 | |||
| 77 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 78 | |||
| 79 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 80 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 81 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 82 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 83 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 84 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 85 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 86 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 87 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 88 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 89 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 90 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h new file mode 100644 index 000000000000..fb8d1618a231 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rstc.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rstc.h | ||
| 3 | * | ||
| 4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RSTC_H | ||
| 14 | #define AT91_RSTC_H | ||
| 15 | |||
| 16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
| 20 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | ||
| 21 | |||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
| 24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
| 25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
| 26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
| 27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
| 28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
| 29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
| 30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
| 31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
| 32 | |||
| 33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
| 34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
| 35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
| 36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rtc.h b/include/asm-arm/arch-at91/at91_rtc.h new file mode 100644 index 000000000000..af9bd28174c0 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rtc.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rtc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Real Time Clock (RTC) - System peripheral registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_RTC_H | ||
| 17 | #define AT91_RTC_H | ||
| 18 | |||
| 19 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 20 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 21 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 22 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 23 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 24 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 25 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 26 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 27 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 28 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 29 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 30 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 31 | |||
| 32 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 33 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 34 | |||
| 35 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 36 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 37 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 38 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 39 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 40 | |||
| 41 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 42 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 43 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 44 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 45 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 46 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 47 | |||
| 48 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 49 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 50 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 51 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 52 | |||
| 53 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 54 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 55 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 56 | |||
| 57 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 58 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 59 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 60 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 61 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 62 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 63 | |||
| 64 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 65 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 66 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 67 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 68 | |||
| 69 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 70 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 71 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 72 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 73 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h new file mode 100644 index 000000000000..bae1103fbbb2 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_rtt.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rtt.h | ||
| 3 | * | ||
| 4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RTT_H | ||
| 14 | #define AT91_RTT_H | ||
| 15 | |||
| 16 | #define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ | ||
| 17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
| 18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
| 19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
| 20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ | ||
| 23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
| 24 | |||
| 25 | #define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ | ||
| 26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
| 27 | |||
| 28 | #define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ | ||
| 29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
| 30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h new file mode 100644 index 000000000000..795fcc266228 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_shdwc.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_shdwc.h | ||
| 3 | * | ||
| 4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_SHDWC_H | ||
| 14 | #define AT91_SHDWC_H | ||
| 15 | |||
| 16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
| 17 | #define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
| 21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
| 22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
| 23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
| 24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
| 25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
| 26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
| 27 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
| 28 | |||
| 29 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
| 30 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
| 31 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h new file mode 100644 index 000000000000..f9b9a8464997 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_spi.h | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_spi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Serial Peripheral Interface (SPI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_SPI_H | ||
| 17 | #define AT91_SPI_H | ||
| 18 | |||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | ||
| 21 | #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ | ||
| 22 | #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ | ||
| 23 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 24 | |||
| 25 | #define AT91_SPI_MR 0x04 /* Mode Register */ | ||
| 26 | #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ | ||
| 27 | #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ | ||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | ||
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | ||
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | ||
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ | ||
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | ||
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | ||
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 35 | #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ | ||
| 36 | |||
| 37 | #define AT91_SPI_RDR 0x08 /* Receive Data Register */ | ||
| 38 | #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ | ||
| 39 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 40 | |||
| 41 | #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ | ||
| 42 | #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ | ||
| 43 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 44 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 45 | |||
| 46 | #define AT91_SPI_SR 0x10 /* Status Register */ | ||
| 47 | #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ | ||
| 48 | #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ | ||
| 49 | #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ | ||
| 50 | #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ | ||
| 51 | #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ | ||
| 52 | #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ | ||
| 53 | #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ | ||
| 54 | #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ | ||
| 55 | #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ | ||
| 56 | #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ | ||
| 57 | #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ | ||
| 58 | |||
| 59 | #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ | ||
| 60 | #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ | ||
| 61 | #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ | ||
| 62 | |||
| 63 | #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ | ||
| 64 | #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ | ||
| 65 | #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ | ||
| 66 | #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ | ||
| 67 | #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ | ||
| 68 | #define AT91_SPI_BITS_8 (0 << 4) | ||
| 69 | #define AT91_SPI_BITS_9 (1 << 4) | ||
| 70 | #define AT91_SPI_BITS_10 (2 << 4) | ||
| 71 | #define AT91_SPI_BITS_11 (3 << 4) | ||
| 72 | #define AT91_SPI_BITS_12 (4 << 4) | ||
| 73 | #define AT91_SPI_BITS_13 (5 << 4) | ||
| 74 | #define AT91_SPI_BITS_14 (6 << 4) | ||
| 75 | #define AT91_SPI_BITS_15 (7 << 4) | ||
| 76 | #define AT91_SPI_BITS_16 (8 << 4) | ||
| 77 | #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ | ||
| 78 | #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ | ||
| 79 | #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_ssc.h b/include/asm-arm/arch-at91/at91_ssc.h new file mode 100644 index 000000000000..0ecc73460b50 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_ssc.h | |||
| @@ -0,0 +1,106 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_ssc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Serial Synchronous Controller (SSC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_SSC_H | ||
| 16 | #define AT91_SSC_H | ||
| 17 | |||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | ||
| 20 | #define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ | ||
| 21 | #define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ | ||
| 22 | #define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ | ||
| 23 | #define AT91_SSC_SWRST (1 << 15) /* Software Reset */ | ||
| 24 | |||
| 25 | #define AT91_SSC_CMR 0x04 /* Clock Mode Register */ | ||
| 26 | #define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ | ||
| 27 | |||
| 28 | #define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ | ||
| 29 | #define AT91_SSC_CKS (3 << 0) /* Clock Selection */ | ||
| 30 | #define AT91_SSC_CKS_DIV (0 << 0) | ||
| 31 | #define AT91_SSC_CKS_CLOCK (1 << 0) | ||
| 32 | #define AT91_SSC_CKS_PIN (2 << 0) | ||
| 33 | #define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ | ||
| 34 | #define AT91_SSC_CKO_NONE (0 << 2) | ||
| 35 | #define AT91_SSC_CKO_CONTINUOUS (1 << 2) | ||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | ||
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | ||
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | ||
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | ||
| 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | ||
| 45 | #define AT91_SSC_START_TX_RX (1 << 8) | ||
| 46 | #define AT91_SSC_START_LOW_RF (2 << 8) | ||
| 47 | #define AT91_SSC_START_HIGH_RF (3 << 8) | ||
| 48 | #define AT91_SSC_START_FALLING_RF (4 << 8) | ||
| 49 | #define AT91_SSC_START_RISING_RF (5 << 8) | ||
| 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | ||
| 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) | ||
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | ||
| 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | ||
| 55 | |||
| 56 | #define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ | ||
| 57 | #define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ | ||
| 58 | #define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ | ||
| 59 | #define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ | ||
| 60 | #define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ | ||
| 61 | #define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ | ||
| 62 | #define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ | ||
| 63 | #define AT91_SSC_FSOS_NONE (0 << 20) | ||
| 64 | #define AT91_SSC_FSOS_NEGATIVE (1 << 20) | ||
| 65 | #define AT91_SSC_FSOS_POSITIVE (2 << 20) | ||
| 66 | #define AT91_SSC_FSOS_LOW (3 << 20) | ||
| 67 | #define AT91_SSC_FSOS_HIGH (4 << 20) | ||
| 68 | #define AT91_SSC_FSOS_TOGGLE (5 << 20) | ||
| 69 | #define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ | ||
| 70 | #define AT91_SSC_FSEDGE_POSITIVE (0 << 24) | ||
| 71 | #define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) | ||
| 72 | |||
| 73 | #define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ | ||
| 74 | #define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ | ||
| 75 | #define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ | ||
| 76 | #define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ | ||
| 77 | |||
| 78 | #define AT91_SSC_RHR 0x20 /* Receive Holding Register */ | ||
| 79 | #define AT91_SSC_THR 0x24 /* Transmit Holding Register */ | ||
| 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | ||
| 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | ||
| 82 | |||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 86 | #define AT91_SSC_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | ||
| 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | ||
| 89 | #define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ | ||
| 90 | #define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ | ||
| 91 | #define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ | ||
| 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | ||
| 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | ||
| 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | ||
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | ||
| 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | ||
| 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | ||
| 100 | #define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ | ||
| 101 | |||
| 102 | #define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ | ||
| 103 | #define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ | ||
| 104 | #define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h new file mode 100644 index 000000000000..30446e2ea772 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_st.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_st.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System Timer (ST) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_ST_H | ||
| 17 | #define AT91_ST_H | ||
| 18 | |||
| 19 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 20 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 23 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 24 | |||
| 25 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 26 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 27 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 28 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 29 | |||
| 30 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 31 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 32 | |||
| 33 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 34 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 35 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 36 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 37 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 38 | |||
| 39 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 40 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 41 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 42 | |||
| 43 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 44 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 45 | |||
| 46 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 47 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h new file mode 100644 index 000000000000..b85d3faeef5c --- /dev/null +++ b/include/asm-arm/arch-at91/at91_tc.h | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_tc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Timer/Counter Unit (TC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_TC_H | ||
| 16 | #define AT91_TC_H | ||
| 17 | |||
| 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ | ||
| 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ | ||
| 20 | |||
| 21 | #define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ | ||
| 22 | #define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ | ||
| 23 | #define AT91_TC_TC0XC0S_TCLK0 (0 << 0) | ||
| 24 | #define AT91_TC_TC0XC0S_NONE (1 << 0) | ||
| 25 | #define AT91_TC_TC0XC0S_TIOA1 (2 << 0) | ||
| 26 | #define AT91_TC_TC0XC0S_TIOA2 (3 << 0) | ||
| 27 | #define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ | ||
| 28 | #define AT91_TC_TC1XC1S_TCLK1 (0 << 2) | ||
| 29 | #define AT91_TC_TC1XC1S_NONE (1 << 2) | ||
| 30 | #define AT91_TC_TC1XC1S_TIOA0 (2 << 2) | ||
| 31 | #define AT91_TC_TC1XC1S_TIOA2 (3 << 2) | ||
| 32 | #define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ | ||
| 33 | #define AT91_TC_TC2XC2S_TCLK2 (0 << 4) | ||
| 34 | #define AT91_TC_TC2XC2S_NONE (1 << 4) | ||
| 35 | #define AT91_TC_TC2XC2S_TIOA0 (2 << 4) | ||
| 36 | #define AT91_TC_TC2XC2S_TIOA1 (3 << 4) | ||
| 37 | |||
| 38 | |||
| 39 | #define AT91_TC_CCR 0x00 /* Channel Control Register */ | ||
| 40 | #define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ | ||
| 41 | #define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ | ||
| 42 | #define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ | ||
| 43 | |||
| 44 | #define AT91_TC_CMR 0x04 /* Channel Mode Register */ | ||
| 45 | #define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ | ||
| 46 | #define AT91_TC_TIMER_CLOCK1 (0 << 0) | ||
| 47 | #define AT91_TC_TIMER_CLOCK2 (1 << 0) | ||
| 48 | #define AT91_TC_TIMER_CLOCK3 (2 << 0) | ||
| 49 | #define AT91_TC_TIMER_CLOCK4 (3 << 0) | ||
| 50 | #define AT91_TC_TIMER_CLOCK5 (4 << 0) | ||
| 51 | #define AT91_TC_XC0 (5 << 0) | ||
| 52 | #define AT91_TC_XC1 (6 << 0) | ||
| 53 | #define AT91_TC_XC2 (7 << 0) | ||
| 54 | #define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ | ||
| 55 | #define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ | ||
| 56 | #define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ | ||
| 57 | #define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ | ||
| 58 | #define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ | ||
| 59 | #define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ | ||
| 60 | #define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ | ||
| 61 | #define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ | ||
| 62 | #define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ | ||
| 63 | #define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ | ||
| 64 | |||
| 65 | #define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ | ||
| 66 | #define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ | ||
| 67 | #define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ | ||
| 68 | #define AT91_TC_EEVTEDG_NONE (0 << 8) | ||
| 69 | #define AT91_TC_EEVTEDG_RISING (1 << 8) | ||
| 70 | #define AT91_TC_EEVTEDG_FALLING (2 << 8) | ||
| 71 | #define AT91_TC_EEVTEDG_BOTH (3 << 8) | ||
| 72 | #define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ | ||
| 73 | #define AT91_TC_EEVT_TIOB (0 << 10) | ||
| 74 | #define AT91_TC_EEVT_XC0 (1 << 10) | ||
| 75 | #define AT91_TC_EEVT_XC1 (2 << 10) | ||
| 76 | #define AT91_TC_EEVT_XC2 (3 << 10) | ||
| 77 | #define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ | ||
| 78 | #define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ | ||
| 79 | #define AT91_TC_WAVESEL_UP (0 << 13) | ||
| 80 | #define AT91_TC_WAVESEL_UP_AUTO (2 << 13) | ||
| 81 | #define AT91_TC_WAVESEL_UPDOWN (1 << 13) | ||
| 82 | #define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) | ||
| 83 | #define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ | ||
| 84 | #define AT91_TC_ACPA_NONE (0 << 16) | ||
| 85 | #define AT91_TC_ACPA_SET (1 << 16) | ||
| 86 | #define AT91_TC_ACPA_CLEAR (2 << 16) | ||
| 87 | #define AT91_TC_ACPA_TOGGLE (3 << 16) | ||
| 88 | #define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ | ||
| 89 | #define AT91_TC_ACPC_NONE (0 << 18) | ||
| 90 | #define AT91_TC_ACPC_SET (1 << 18) | ||
| 91 | #define AT91_TC_ACPC_CLEAR (2 << 18) | ||
| 92 | #define AT91_TC_ACPC_TOGGLE (3 << 18) | ||
| 93 | #define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ | ||
| 94 | #define AT91_TC_AEEVT_NONE (0 << 20) | ||
| 95 | #define AT91_TC_AEEVT_SET (1 << 20) | ||
| 96 | #define AT91_TC_AEEVT_CLEAR (2 << 20) | ||
| 97 | #define AT91_TC_AEEVT_TOGGLE (3 << 20) | ||
| 98 | #define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ | ||
| 99 | #define AT91_TC_ASWTRG_NONE (0 << 22) | ||
| 100 | #define AT91_TC_ASWTRG_SET (1 << 22) | ||
| 101 | #define AT91_TC_ASWTRG_CLEAR (2 << 22) | ||
| 102 | #define AT91_TC_ASWTRG_TOGGLE (3 << 22) | ||
| 103 | #define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ | ||
| 104 | #define AT91_TC_BCPB_NONE (0 << 24) | ||
| 105 | #define AT91_TC_BCPB_SET (1 << 24) | ||
| 106 | #define AT91_TC_BCPB_CLEAR (2 << 24) | ||
| 107 | #define AT91_TC_BCPB_TOGGLE (3 << 24) | ||
| 108 | #define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ | ||
| 109 | #define AT91_TC_BCPC_NONE (0 << 26) | ||
| 110 | #define AT91_TC_BCPC_SET (1 << 26) | ||
| 111 | #define AT91_TC_BCPC_CLEAR (2 << 26) | ||
| 112 | #define AT91_TC_BCPC_TOGGLE (3 << 26) | ||
| 113 | #define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ | ||
| 114 | #define AT91_TC_BEEVT_NONE (0 << 28) | ||
| 115 | #define AT91_TC_BEEVT_SET (1 << 28) | ||
| 116 | #define AT91_TC_BEEVT_CLEAR (2 << 28) | ||
| 117 | #define AT91_TC_BEEVT_TOGGLE (3 << 28) | ||
| 118 | #define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ | ||
| 119 | #define AT91_TC_BSWTRG_NONE (0 << 30) | ||
| 120 | #define AT91_TC_BSWTRG_SET (1 << 30) | ||
| 121 | #define AT91_TC_BSWTRG_CLEAR (2 << 30) | ||
| 122 | #define AT91_TC_BSWTRG_TOGGLE (3 << 30) | ||
| 123 | |||
| 124 | #define AT91_TC_CV 0x10 /* Counter Value */ | ||
| 125 | #define AT91_TC_RA 0x14 /* Register A */ | ||
| 126 | #define AT91_TC_RB 0x18 /* Register B */ | ||
| 127 | #define AT91_TC_RC 0x1c /* Register C */ | ||
| 128 | |||
| 129 | #define AT91_TC_SR 0x20 /* Status Register */ | ||
| 130 | #define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ | ||
| 131 | #define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ | ||
| 132 | #define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ | ||
| 133 | #define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ | ||
| 134 | #define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ | ||
| 135 | #define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ | ||
| 136 | #define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ | ||
| 137 | #define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ | ||
| 138 | #define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ | ||
| 139 | #define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ | ||
| 140 | #define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ | ||
| 141 | |||
| 142 | #define AT91_TC_IER 0x24 /* Interrupt Enable Register */ | ||
| 143 | #define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 144 | #define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ | ||
| 145 | |||
| 146 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h new file mode 100644 index 000000000000..ca9a90733456 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_twi.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_twi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Two-wire Interface (TWI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_TWI_H | ||
| 17 | #define AT91_TWI_H | ||
| 18 | |||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | ||
| 21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ | ||
| 22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ | ||
| 23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ | ||
| 24 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ | ||
| 25 | |||
| 26 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ | ||
| 27 | #define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ | ||
| 28 | #define AT91_TWI_IADRSZ_NO (0 << 8) | ||
| 29 | #define AT91_TWI_IADRSZ_1 (1 << 8) | ||
| 30 | #define AT91_TWI_IADRSZ_2 (2 << 8) | ||
| 31 | #define AT91_TWI_IADRSZ_3 (3 << 8) | ||
| 32 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ | ||
| 33 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ | ||
| 34 | |||
| 35 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ | ||
| 36 | |||
| 37 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ | ||
| 38 | #define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ | ||
| 39 | #define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ | ||
| 40 | #define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ | ||
| 41 | |||
| 42 | #define AT91_TWI_SR 0x20 /* Status Register */ | ||
| 43 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | ||
| 44 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | ||
| 45 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | ||
| 46 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ | ||
| 47 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ | ||
| 48 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | ||
| 49 | |||
| 50 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | ||
| 51 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ | ||
| 52 | #define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ | ||
| 53 | #define AT91_TWI_RHR 0x30 /* Receive Holding Register */ | ||
| 54 | #define AT91_TWI_THR 0x34 /* Transmit Holding Register */ | ||
| 55 | |||
| 56 | #endif | ||
| 57 | |||
diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h new file mode 100644 index 000000000000..7251a344c740 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_wdt.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_wdt.h | ||
| 3 | * | ||
| 4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_WDT_H | ||
| 14 | #define AT91_WDT_H | ||
| 15 | |||
| 16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
| 17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
| 18 | #define AT91_WDT_KEY (0xff << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
| 21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
| 22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
| 23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
| 24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
| 25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
| 26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
| 27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
| 28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
| 29 | |||
| 30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
| 31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
| 32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h new file mode 100644 index 000000000000..a12ac8ab2ad0 --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200.h | |||
| @@ -0,0 +1,291 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Common definitions. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_H | ||
| 17 | #define AT91RM9200_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Peripheral identifiers/interrupts. | ||
| 21 | */ | ||
| 22 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 23 | #define AT91_ID_SYS 1 /* System Peripheral */ | ||
| 24 | #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 25 | #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 26 | #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 27 | #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ | ||
| 28 | #define AT91RM9200_ID_US0 6 /* USART 0 */ | ||
| 29 | #define AT91RM9200_ID_US1 7 /* USART 1 */ | ||
| 30 | #define AT91RM9200_ID_US2 8 /* USART 2 */ | ||
| 31 | #define AT91RM9200_ID_US3 9 /* USART 3 */ | ||
| 32 | #define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ | ||
| 33 | #define AT91RM9200_ID_UDP 11 /* USB Device Port */ | ||
| 34 | #define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ | ||
| 35 | #define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ | ||
| 36 | #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 37 | #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 38 | #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 39 | #define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ | ||
| 40 | #define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ | ||
| 41 | #define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ | ||
| 42 | #define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ | ||
| 43 | #define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ | ||
| 44 | #define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ | ||
| 45 | #define AT91RM9200_ID_UHP 23 /* USB Host port */ | ||
| 46 | #define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ | ||
| 47 | #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | #define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 50 | #define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ | ||
| 51 | #define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ | ||
| 52 | #define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ | ||
| 53 | #define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ | ||
| 54 | |||
| 55 | |||
| 56 | /* | ||
| 57 | * Peripheral physical base addresses. | ||
| 58 | */ | ||
| 59 | #define AT91RM9200_BASE_TCB0 0xfffa0000 | ||
| 60 | #define AT91RM9200_BASE_TC0 0xfffa0000 | ||
| 61 | #define AT91RM9200_BASE_TC1 0xfffa0040 | ||
| 62 | #define AT91RM9200_BASE_TC2 0xfffa0080 | ||
| 63 | #define AT91RM9200_BASE_TCB1 0xfffa4000 | ||
| 64 | #define AT91RM9200_BASE_TC3 0xfffa4000 | ||
| 65 | #define AT91RM9200_BASE_TC4 0xfffa4040 | ||
| 66 | #define AT91RM9200_BASE_TC5 0xfffa4080 | ||
| 67 | #define AT91RM9200_BASE_UDP 0xfffb0000 | ||
| 68 | #define AT91RM9200_BASE_MCI 0xfffb4000 | ||
| 69 | #define AT91RM9200_BASE_TWI 0xfffb8000 | ||
| 70 | #define AT91RM9200_BASE_EMAC 0xfffbc000 | ||
| 71 | #define AT91RM9200_BASE_US0 0xfffc0000 | ||
| 72 | #define AT91RM9200_BASE_US1 0xfffc4000 | ||
| 73 | #define AT91RM9200_BASE_US2 0xfffc8000 | ||
| 74 | #define AT91RM9200_BASE_US3 0xfffcc000 | ||
| 75 | #define AT91RM9200_BASE_SSC0 0xfffd0000 | ||
| 76 | #define AT91RM9200_BASE_SSC1 0xfffd4000 | ||
| 77 | #define AT91RM9200_BASE_SSC2 0xfffd8000 | ||
| 78 | #define AT91RM9200_BASE_SPI 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xfffff000 | ||
| 80 | |||
| 81 | |||
| 82 | /* | ||
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ | ||
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ | ||
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ | ||
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ | ||
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | ||
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ | ||
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ | ||
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 95 | |||
| 96 | #define AT91_MATRIX 0 /* not supported */ | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Internal Memory. | ||
| 100 | */ | ||
| 101 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 102 | #define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 103 | |||
| 104 | #define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ | ||
| 105 | #define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
| 106 | |||
| 107 | #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ | ||
| 108 | |||
| 109 | |||
| 110 | #if 0 | ||
| 111 | /* | ||
| 112 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 113 | */ | ||
| 114 | #define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ | ||
| 115 | #define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */ | ||
| 116 | #define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */ | ||
| 117 | #define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */ | ||
| 118 | #define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */ | ||
| 119 | #define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */ | ||
| 120 | #define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */ | ||
| 121 | #define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */ | ||
| 122 | #define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */ | ||
| 123 | #define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */ | ||
| 124 | #define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */ | ||
| 125 | #define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */ | ||
| 126 | #define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */ | ||
| 127 | #define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */ | ||
| 128 | #define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */ | ||
| 129 | #define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */ | ||
| 130 | #define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */ | ||
| 131 | #define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */ | ||
| 132 | #define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */ | ||
| 133 | #define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */ | ||
| 134 | #define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */ | ||
| 135 | #define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */ | ||
| 136 | #define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */ | ||
| 137 | #define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */ | ||
| 138 | #define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */ | ||
| 139 | #define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */ | ||
| 140 | #define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */ | ||
| 141 | #define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */ | ||
| 142 | #define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */ | ||
| 143 | #define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */ | ||
| 144 | #define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */ | ||
| 145 | #define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */ | ||
| 146 | #define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */ | ||
| 147 | #define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */ | ||
| 148 | #define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */ | ||
| 149 | #define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */ | ||
| 150 | #define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */ | ||
| 151 | #define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */ | ||
| 152 | #define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */ | ||
| 153 | #define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */ | ||
| 154 | #define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */ | ||
| 155 | #define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */ | ||
| 156 | #define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ | ||
| 157 | #define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */ | ||
| 158 | #define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */ | ||
| 159 | #define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */ | ||
| 160 | #define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */ | ||
| 161 | #define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */ | ||
| 162 | #define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */ | ||
| 163 | #define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */ | ||
| 164 | #define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */ | ||
| 165 | #define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */ | ||
| 166 | #define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */ | ||
| 167 | #define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */ | ||
| 168 | #define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */ | ||
| 169 | #define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */ | ||
| 170 | #define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */ | ||
| 171 | #define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */ | ||
| 172 | #define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */ | ||
| 173 | #define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */ | ||
| 174 | #define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */ | ||
| 175 | #define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */ | ||
| 176 | #define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */ | ||
| 177 | #define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */ | ||
| 178 | |||
| 179 | #define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */ | ||
| 180 | #define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */ | ||
| 181 | #define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */ | ||
| 182 | #define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */ | ||
| 183 | #define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */ | ||
| 184 | #define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */ | ||
| 185 | #define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */ | ||
| 186 | #define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */ | ||
| 187 | #define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */ | ||
| 188 | #define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */ | ||
| 189 | #define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */ | ||
| 190 | #define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */ | ||
| 191 | #define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */ | ||
| 192 | #define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */ | ||
| 193 | #define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */ | ||
| 194 | #define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */ | ||
| 195 | #define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */ | ||
| 196 | #define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */ | ||
| 197 | #define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */ | ||
| 198 | #define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */ | ||
| 199 | #define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */ | ||
| 200 | #define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */ | ||
| 201 | #define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */ | ||
| 202 | #define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */ | ||
| 203 | #define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */ | ||
| 204 | #define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */ | ||
| 205 | #define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */ | ||
| 206 | #define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */ | ||
| 207 | #define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */ | ||
| 208 | #define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */ | ||
| 209 | #define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */ | ||
| 210 | #define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */ | ||
| 211 | #define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */ | ||
| 212 | #define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */ | ||
| 213 | #define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */ | ||
| 214 | #define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */ | ||
| 215 | #define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */ | ||
| 216 | #define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */ | ||
| 217 | #define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */ | ||
| 218 | #define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */ | ||
| 219 | #define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */ | ||
| 220 | #define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */ | ||
| 221 | #define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */ | ||
| 222 | #define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */ | ||
| 223 | #define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */ | ||
| 224 | #define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */ | ||
| 225 | #define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */ | ||
| 226 | #define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */ | ||
| 227 | #define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */ | ||
| 228 | #define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */ | ||
| 229 | #define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */ | ||
| 230 | |||
| 231 | #define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */ | ||
| 232 | #define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */ | ||
| 233 | #define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */ | ||
| 234 | #define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */ | ||
| 235 | #define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */ | ||
| 236 | #define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */ | ||
| 237 | #define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */ | ||
| 238 | #define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */ | ||
| 239 | #define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */ | ||
| 240 | #define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */ | ||
| 241 | #define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */ | ||
| 242 | #define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */ | ||
| 243 | #define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */ | ||
| 244 | #define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */ | ||
| 245 | |||
| 246 | #define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */ | ||
| 247 | #define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */ | ||
| 248 | #define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */ | ||
| 249 | #define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */ | ||
| 250 | #define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */ | ||
| 251 | #define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */ | ||
| 252 | #define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */ | ||
| 253 | #define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */ | ||
| 254 | #define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */ | ||
| 255 | #define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */ | ||
| 256 | #define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */ | ||
| 257 | #define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */ | ||
| 258 | #define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */ | ||
| 259 | #define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */ | ||
| 260 | #define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */ | ||
| 261 | #define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */ | ||
| 262 | #define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */ | ||
| 263 | #define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */ | ||
| 264 | #define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */ | ||
| 265 | #define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */ | ||
| 266 | #define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */ | ||
| 267 | #define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */ | ||
| 268 | #define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */ | ||
| 269 | #define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */ | ||
| 270 | #define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */ | ||
| 271 | #define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */ | ||
| 272 | #define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */ | ||
| 273 | #define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */ | ||
| 274 | #define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ | ||
| 275 | #define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ | ||
| 276 | #define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ | ||
| 277 | #define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ | ||
| 278 | #define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ | ||
| 279 | #define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ | ||
| 280 | #define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ | ||
| 281 | #define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */ | ||
| 282 | #define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */ | ||
| 283 | #define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */ | ||
| 284 | #define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */ | ||
| 285 | #define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */ | ||
| 286 | #define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ | ||
| 287 | #define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ | ||
| 288 | #define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ | ||
| 289 | #endif | ||
| 290 | |||
| 291 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200_emac.h b/include/asm-arm/arch-at91/at91rm9200_emac.h new file mode 100644 index 000000000000..0c417af5fe7f --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200_emac.h | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200_emac.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Ethernet MAC registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_EMAC_H | ||
| 17 | #define AT91RM9200_EMAC_H | ||
| 18 | |||
| 19 | #define AT91_EMAC_CTL 0x00 /* Control Register */ | ||
| 20 | #define AT91_EMAC_LB (1 << 0) /* Loopback */ | ||
| 21 | #define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ | ||
| 22 | #define AT91_EMAC_RE (1 << 2) /* Receive Enable */ | ||
| 23 | #define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ | ||
| 24 | #define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ | ||
| 25 | #define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ | ||
| 26 | #define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ | ||
| 27 | #define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ | ||
| 28 | #define AT91_EMAC_BP (1 << 8) /* Back Pressure */ | ||
| 29 | |||
| 30 | #define AT91_EMAC_CFG 0x04 /* Configuration Register */ | ||
| 31 | #define AT91_EMAC_SPD (1 << 0) /* Speed */ | ||
| 32 | #define AT91_EMAC_FD (1 << 1) /* Full Duplex */ | ||
| 33 | #define AT91_EMAC_BR (1 << 2) /* Bit Rate */ | ||
| 34 | #define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ | ||
| 35 | #define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ | ||
| 36 | #define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ | ||
| 37 | #define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ | ||
| 38 | #define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ | ||
| 39 | #define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ | ||
| 40 | #define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ | ||
| 41 | #define AT91_EMAC_CLK_DIV8 (0 << 10) | ||
| 42 | #define AT91_EMAC_CLK_DIV16 (1 << 10) | ||
| 43 | #define AT91_EMAC_CLK_DIV32 (2 << 10) | ||
| 44 | #define AT91_EMAC_CLK_DIV64 (3 << 10) | ||
| 45 | #define AT91_EMAC_RTY (1 << 12) /* Retry Test */ | ||
| 46 | #define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ | ||
| 47 | |||
| 48 | #define AT91_EMAC_SR 0x08 /* Status Register */ | ||
| 49 | #define AT91_EMAC_SR_LINK (1 << 0) /* Link */ | ||
| 50 | #define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ | ||
| 51 | #define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ | ||
| 52 | |||
| 53 | #define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ | ||
| 54 | |||
| 55 | #define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ | ||
| 56 | #define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ | ||
| 57 | #define AT91_EMAC_NCRC (1 << 15) /* No CRC */ | ||
| 58 | |||
| 59 | #define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ | ||
| 60 | #define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ | ||
| 61 | #define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ | ||
| 62 | #define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ | ||
| 63 | #define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ | ||
| 64 | #define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ | ||
| 65 | #define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ | ||
| 66 | #define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ | ||
| 67 | |||
| 68 | #define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ | ||
| 69 | |||
| 70 | #define AT91_EMAC_RSR 0x20 /* Receive Status Register */ | ||
| 71 | #define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ | ||
| 72 | #define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ | ||
| 73 | #define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ | ||
| 74 | |||
| 75 | #define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ | ||
| 76 | #define AT91_EMAC_DONE (1 << 0) /* Management Done */ | ||
| 77 | #define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ | ||
| 78 | #define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ | ||
| 79 | #define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ | ||
| 80 | #define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ | ||
| 81 | #define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ | ||
| 82 | #define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ | ||
| 83 | #define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ | ||
| 84 | #define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ | ||
| 85 | #define AT91_EMAC_LINK (1 << 9) /* Link */ | ||
| 86 | #define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ | ||
| 87 | #define AT91_EMAC_ABT (1 << 11) /* Abort */ | ||
| 88 | |||
| 89 | #define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ | ||
| 90 | #define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ | ||
| 91 | #define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ | ||
| 92 | |||
| 93 | #define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ | ||
| 94 | #define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ | ||
| 95 | #define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ | ||
| 96 | #define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ | ||
| 97 | #define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ | ||
| 98 | #define AT91_EMAC_RW_W (1 << 28) | ||
| 99 | #define AT91_EMAC_RW_R (2 << 28) | ||
| 100 | #define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Statistics Registers. | ||
| 104 | */ | ||
| 105 | #define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ | ||
| 106 | #define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ | ||
| 107 | #define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ | ||
| 108 | #define AT91_EMAC_OK 0x4c /* Frames Received OK */ | ||
| 109 | #define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ | ||
| 110 | #define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ | ||
| 111 | #define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ | ||
| 112 | #define AT91_EMAC_LCOL 0x5c /* Late Collision */ | ||
| 113 | #define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ | ||
| 114 | #define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ | ||
| 115 | #define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ | ||
| 116 | #define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ | ||
| 117 | #define AT91_EMAC_ROV 0x70 /* Receive Overrun */ | ||
| 118 | #define AT91_EMAC_CDE 0x74 /* Code Error */ | ||
| 119 | #define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ | ||
| 120 | #define AT91_EMAC_RJB 0x7c /* Receive Jabber */ | ||
| 121 | #define AT91_EMAC_USF 0x80 /* Undersize Frame */ | ||
| 122 | #define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Address Registers. | ||
| 126 | */ | ||
| 127 | #define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ | ||
| 128 | #define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ | ||
| 129 | #define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ | ||
| 130 | #define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ | ||
| 131 | #define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ | ||
| 132 | #define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ | ||
| 133 | #define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ | ||
| 134 | #define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ | ||
| 135 | #define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ | ||
| 136 | #define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200_mc.h b/include/asm-arm/arch-at91/at91rm9200_mc.h new file mode 100644 index 000000000000..24d012939cc4 --- /dev/null +++ b/include/asm-arm/arch-at91/at91rm9200_mc.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200_mc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_MC_H | ||
| 17 | #define AT91RM9200_MC_H | ||
| 18 | |||
| 19 | /* Memory Controller */ | ||
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 22 | |||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 27 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 28 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 29 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 30 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 31 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 32 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 33 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 34 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 35 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 36 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 37 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 38 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 39 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 42 | |||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 44 | |||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 50 | |||
| 51 | /* External Bus Interface (EBI) registers */ | ||
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 56 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 57 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 58 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 59 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 60 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 61 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 62 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 63 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 64 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 65 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 67 | |||
| 68 | /* Static Memory Controller (SMC) registers */ | ||
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 73 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 74 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 75 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 76 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 77 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 78 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 79 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 80 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 81 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 82 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 83 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 84 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 85 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 86 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 87 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 89 | |||
| 90 | /* SDRAM Controller registers */ | ||
| 91 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 92 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 93 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 94 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 95 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 96 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 97 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 98 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 99 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 100 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 101 | |||
| 102 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 103 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 104 | |||
| 105 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 106 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 107 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 108 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 109 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 110 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 111 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 112 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 113 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 114 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 115 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 116 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 117 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 118 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 119 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 120 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 121 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 122 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 123 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 124 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 125 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 126 | |||
| 127 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 128 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 129 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 130 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 131 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 132 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 133 | |||
| 134 | /* Burst Flash Controller register */ | ||
| 135 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 136 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 137 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 138 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 139 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 140 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 141 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 142 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 143 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 144 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 145 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 146 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 147 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 148 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 149 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 150 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 151 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 152 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 153 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 154 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 155 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 156 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 157 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 158 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h new file mode 100644 index 000000000000..2cadebc36af7 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9260.h | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9260.h | ||
| 3 | * | ||
| 4 | * (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9260 datasheet revision A (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9260_H | ||
| 16 | #define AT91SAM9260_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ | ||
| 27 | #define AT91SAM9260_ID_US0 6 /* USART 0 */ | ||
| 28 | #define AT91SAM9260_ID_US1 7 /* USART 1 */ | ||
| 29 | #define AT91SAM9260_ID_US2 8 /* USART 2 */ | ||
| 30 | #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 31 | #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ | ||
| 32 | #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ | ||
| 36 | #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ | ||
| 37 | #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ | ||
| 38 | #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ | ||
| 39 | #define AT91SAM9260_ID_UHP 20 /* USB Host port */ | ||
| 40 | #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ | ||
| 42 | #define AT91SAM9260_ID_US3 23 /* USART 3 */ | ||
| 43 | #define AT91SAM9260_ID_US4 24 /* USART 4 */ | ||
| 44 | #define AT91SAM9260_ID_US5 25 /* USART 5 */ | ||
| 45 | #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ | ||
| 46 | #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ | ||
| 47 | #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ | ||
| 48 | #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 49 | #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 50 | #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 51 | |||
| 52 | |||
| 53 | /* | ||
| 54 | * User Peripheral physical base addresses. | ||
| 55 | */ | ||
| 56 | #define AT91SAM9260_BASE_TCB0 0xfffa0000 | ||
| 57 | #define AT91SAM9260_BASE_TC0 0xfffa0000 | ||
| 58 | #define AT91SAM9260_BASE_TC1 0xfffa0040 | ||
| 59 | #define AT91SAM9260_BASE_TC2 0xfffa0080 | ||
| 60 | #define AT91SAM9260_BASE_UDP 0xfffa4000 | ||
| 61 | #define AT91SAM9260_BASE_MCI 0xfffa8000 | ||
| 62 | #define AT91SAM9260_BASE_TWI 0xfffac000 | ||
| 63 | #define AT91SAM9260_BASE_US0 0xfffb0000 | ||
| 64 | #define AT91SAM9260_BASE_US1 0xfffb4000 | ||
| 65 | #define AT91SAM9260_BASE_US2 0xfffb8000 | ||
| 66 | #define AT91SAM9260_BASE_SSC 0xfffbc000 | ||
| 67 | #define AT91SAM9260_BASE_ISI 0xfffc0000 | ||
| 68 | #define AT91SAM9260_BASE_EMAC 0xfffc4000 | ||
| 69 | #define AT91SAM9260_BASE_SPI0 0xfffc8000 | ||
| 70 | #define AT91SAM9260_BASE_SPI1 0xfffcc000 | ||
| 71 | #define AT91SAM9260_BASE_US3 0xfffd0000 | ||
| 72 | #define AT91SAM9260_BASE_US4 0xfffd4000 | ||
| 73 | #define AT91SAM9260_BASE_US5 0xfffd8000 | ||
| 74 | #define AT91SAM9260_BASE_TCB1 0xfffdc000 | ||
| 75 | #define AT91SAM9260_BASE_TC3 0xfffdc000 | ||
| 76 | #define AT91SAM9260_BASE_TC4 0xfffdc040 | ||
| 77 | #define AT91SAM9260_BASE_TC5 0xfffdc080 | ||
| 78 | #define AT91SAM9260_BASE_ADC 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xffffe800 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 83 | */ | ||
| 84 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 97 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 98 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 99 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 100 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 107 | #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 108 | |||
| 109 | #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 110 | #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ | ||
| 111 | #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 112 | #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ | ||
| 113 | |||
| 114 | #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 115 | |||
| 116 | #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ | ||
| 117 | #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 118 | |||
| 119 | |||
| 120 | #if 0 | ||
| 121 | /* | ||
| 122 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 123 | */ | ||
| 124 | |||
| 125 | // TODO: Add | ||
| 126 | |||
| 127 | #endif | ||
| 128 | |||
| 129 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h new file mode 100644 index 000000000000..aacb1e976422 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9260_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9260_MATRIX_H | ||
| 14 | #define AT91SAM9260_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 28 | |||
| 29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 55 | |||
| 56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 59 | |||
| 60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
| 61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 70 | #define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ | ||
| 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h new file mode 100644 index 000000000000..01b58ffe2e27 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9261.h | |||
| @@ -0,0 +1,292 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9261.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9261_H | ||
| 16 | #define AT91SAM9261_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | ||
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | ||
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | ||
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | ||
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | ||
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | ||
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | ||
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * User Peripheral physical base addresses. | ||
| 49 | */ | ||
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | ||
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | ||
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | ||
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | ||
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | ||
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | ||
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 | ||
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 | ||
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 | ||
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 | ||
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | ||
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | ||
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | ||
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | ||
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | ||
| 65 | #define AT91_BASE_SYS 0xffffea00 | ||
| 66 | |||
| 67 | |||
| 68 | /* | ||
| 69 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 70 | */ | ||
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 86 | |||
| 87 | |||
| 88 | /* | ||
| 89 | * Internal Memory. | ||
| 90 | */ | ||
| 91 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 92 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | ||
| 93 | |||
| 94 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 95 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 96 | |||
| 97 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 98 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | ||
| 99 | |||
| 100 | |||
| 101 | #if 0 | ||
| 102 | /* | ||
| 103 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 104 | */ | ||
| 105 | #define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ | ||
| 106 | #define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ | ||
| 107 | #define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ | ||
| 108 | #define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ | ||
| 109 | #define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ | ||
| 110 | #define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ | ||
| 111 | #define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ | ||
| 112 | #define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ | ||
| 113 | #define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ | ||
| 114 | #define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ | ||
| 115 | #define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ | ||
| 116 | #define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ | ||
| 117 | #define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ | ||
| 118 | #define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ | ||
| 119 | #define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ | ||
| 120 | #define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ | ||
| 121 | #define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ | ||
| 122 | #define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ | ||
| 123 | #define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ | ||
| 124 | #define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ | ||
| 125 | #define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ | ||
| 126 | #define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ | ||
| 127 | #define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ | ||
| 128 | #define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ | ||
| 129 | #define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ | ||
| 130 | #define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ | ||
| 131 | #define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ | ||
| 132 | #define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ | ||
| 133 | #define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ | ||
| 134 | #define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ | ||
| 135 | #define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ | ||
| 136 | #define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ | ||
| 137 | #define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ | ||
| 138 | #define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ | ||
| 139 | #define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ | ||
| 140 | #define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ | ||
| 141 | #define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ | ||
| 142 | #define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ | ||
| 143 | #define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ | ||
| 144 | #define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ | ||
| 145 | #define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ | ||
| 146 | #define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ | ||
| 147 | #define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ | ||
| 148 | #define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ | ||
| 149 | #define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ | ||
| 150 | #define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ | ||
| 151 | #define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ | ||
| 152 | #define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ | ||
| 153 | #define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ | ||
| 154 | #define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ | ||
| 155 | #define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 156 | #define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ | ||
| 157 | #define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 158 | #define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ | ||
| 159 | #define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ | ||
| 160 | #define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ | ||
| 161 | #define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ | ||
| 162 | #define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ | ||
| 163 | #define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ | ||
| 164 | #define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ | ||
| 165 | #define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ | ||
| 166 | #define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ | ||
| 167 | #define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ | ||
| 168 | |||
| 169 | #define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ | ||
| 170 | #define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ | ||
| 171 | #define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ | ||
| 172 | #define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ | ||
| 173 | #define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ | ||
| 174 | #define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ | ||
| 175 | #define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ | ||
| 176 | #define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ | ||
| 177 | #define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ | ||
| 178 | #define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ | ||
| 179 | #define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ | ||
| 180 | #define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ | ||
| 181 | #define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ | ||
| 182 | #define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ | ||
| 183 | #define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ | ||
| 184 | #define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ | ||
| 185 | #define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ | ||
| 186 | #define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ | ||
| 187 | #define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ | ||
| 188 | #define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ | ||
| 189 | #define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ | ||
| 190 | #define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ | ||
| 191 | #define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ | ||
| 192 | #define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ | ||
| 193 | #define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ | ||
| 194 | #define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ | ||
| 195 | #define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ | ||
| 196 | #define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ | ||
| 197 | #define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ | ||
| 198 | #define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ | ||
| 199 | #define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ | ||
| 200 | #define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ | ||
| 201 | #define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ | ||
| 202 | #define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ | ||
| 203 | #define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ | ||
| 204 | #define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ | ||
| 205 | #define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ | ||
| 206 | #define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ | ||
| 207 | #define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ | ||
| 208 | #define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ | ||
| 209 | #define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ | ||
| 210 | #define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ | ||
| 211 | #define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ | ||
| 212 | #define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ | ||
| 213 | #define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ | ||
| 214 | #define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ | ||
| 215 | #define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ | ||
| 216 | #define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ | ||
| 217 | #define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ | ||
| 218 | #define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ | ||
| 219 | #define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ | ||
| 220 | #define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ | ||
| 221 | #define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ | ||
| 222 | #define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ | ||
| 223 | #define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ | ||
| 224 | #define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ | ||
| 225 | #define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ | ||
| 226 | #define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ | ||
| 227 | #define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ | ||
| 228 | #define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ | ||
| 229 | #define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ | ||
| 230 | |||
| 231 | #define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ | ||
| 232 | #define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ | ||
| 233 | #define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ | ||
| 234 | #define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ | ||
| 235 | #define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ | ||
| 236 | #define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ | ||
| 237 | #define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ | ||
| 238 | #define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ | ||
| 239 | #define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ | ||
| 240 | #define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ | ||
| 241 | #define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ | ||
| 242 | #define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ | ||
| 243 | #define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ | ||
| 244 | #define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ | ||
| 245 | #define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ | ||
| 246 | #define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ | ||
| 247 | #define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ | ||
| 248 | #define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ | ||
| 249 | #define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ | ||
| 250 | #define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ | ||
| 251 | #define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ | ||
| 252 | #define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ | ||
| 253 | #define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ | ||
| 254 | #define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ | ||
| 255 | #define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ | ||
| 256 | #define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ | ||
| 257 | #define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ | ||
| 258 | #define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ | ||
| 259 | #define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ | ||
| 260 | #define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ | ||
| 261 | #define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ | ||
| 262 | #define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ | ||
| 263 | #define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ | ||
| 264 | #define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ | ||
| 265 | #define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ | ||
| 266 | #define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ | ||
| 267 | #define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ | ||
| 268 | #define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ | ||
| 269 | #define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ | ||
| 270 | #define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ | ||
| 271 | #define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ | ||
| 272 | #define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ | ||
| 273 | #define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ | ||
| 274 | #define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ | ||
| 275 | #define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ | ||
| 276 | #define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ | ||
| 277 | #define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ | ||
| 278 | #define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ | ||
| 279 | #define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ | ||
| 280 | #define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ | ||
| 281 | #define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ | ||
| 282 | #define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ | ||
| 283 | #define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ | ||
| 284 | #define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ | ||
| 285 | #define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ | ||
| 286 | #define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ | ||
| 287 | #define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ | ||
| 288 | #define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ | ||
| 289 | #define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ | ||
| 290 | #endif | ||
| 291 | |||
| 292 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h new file mode 100644 index 000000000000..6f072421be5b --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9261_matrix.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9261_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9261_MATRIX_H | ||
| 14 | #define AT91SAM9261_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 18 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 19 | |||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 31 | |||
| 32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
| 33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
| 38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
| 45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
| 60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h new file mode 100644 index 000000000000..f4af68ae0ea9 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9263.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9263.h | ||
| 3 | * | ||
| 4 | * (C) 2007 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_H | ||
| 16 | #define AT91SAM9263_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ | ||
| 26 | #define AT91SAM9263_ID_US0 7 /* USART 0 */ | ||
| 27 | #define AT91SAM9263_ID_US1 8 /* USART 1 */ | ||
| 28 | #define AT91SAM9263_ID_US2 9 /* USART 2 */ | ||
| 29 | #define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ | ||
| 30 | #define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ | ||
| 31 | #define AT91SAM9263_ID_CAN 12 /* CAN */ | ||
| 32 | #define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ | ||
| 36 | #define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ | ||
| 37 | #define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ | ||
| 38 | #define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ | ||
| 39 | #define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ | ||
| 40 | #define AT91SAM9263_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ | ||
| 42 | #define AT91SAM9263_ID_UDP 24 /* USB Device Port */ | ||
| 43 | #define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ | ||
| 44 | #define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ | ||
| 45 | #define AT91SAM9263_ID_DMA 27 /* DMA Controller */ | ||
| 46 | #define AT91SAM9263_ID_UHP 29 /* USB Host port */ | ||
| 47 | #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | |||
| 50 | |||
| 51 | /* | ||
| 52 | * User Peripheral physical base addresses. | ||
| 53 | */ | ||
| 54 | #define AT91SAM9263_BASE_UDP 0xfff78000 | ||
| 55 | #define AT91SAM9263_BASE_TCB0 0xfff7c000 | ||
| 56 | #define AT91SAM9263_BASE_TC0 0xfff7c000 | ||
| 57 | #define AT91SAM9263_BASE_TC1 0xfff7c040 | ||
| 58 | #define AT91SAM9263_BASE_TC2 0xfff7c080 | ||
| 59 | #define AT91SAM9263_BASE_MCI0 0xfff80000 | ||
| 60 | #define AT91SAM9263_BASE_MCI1 0xfff84000 | ||
| 61 | #define AT91SAM9263_BASE_TWI 0xfff88000 | ||
| 62 | #define AT91SAM9263_BASE_US0 0xfff8c000 | ||
| 63 | #define AT91SAM9263_BASE_US1 0xfff90000 | ||
| 64 | #define AT91SAM9263_BASE_US2 0xfff94000 | ||
| 65 | #define AT91SAM9263_BASE_SSC0 0xfff98000 | ||
| 66 | #define AT91SAM9263_BASE_SSC1 0xfff9c000 | ||
| 67 | #define AT91SAM9263_BASE_AC97C 0xfffa0000 | ||
| 68 | #define AT91SAM9263_BASE_SPI0 0xfffa4000 | ||
| 69 | #define AT91SAM9263_BASE_SPI1 0xfffa8000 | ||
| 70 | #define AT91SAM9263_BASE_CAN 0xfffac000 | ||
| 71 | #define AT91SAM9263_BASE_PWMC 0xfffb8000 | ||
| 72 | #define AT91SAM9263_BASE_EMAC 0xfffbc000 | ||
| 73 | #define AT91SAM9263_BASE_ISI 0xfffc4000 | ||
| 74 | #define AT91SAM9263_BASE_2DGE 0xfffc8000 | ||
| 75 | #define AT91_BASE_SYS 0xffffe000 | ||
| 76 | |||
| 77 | /* | ||
| 78 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 79 | */ | ||
| 80 | #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) | ||
| 82 | #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) | ||
| 83 | #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) | ||
| 84 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) | ||
| 88 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 98 | #define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) | ||
| 99 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 100 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 101 | #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) | ||
| 102 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 103 | |||
| 104 | #define AT91_SMC AT91_SMC0 | ||
| 105 | |||
| 106 | /* | ||
| 107 | * Internal Memory. | ||
| 108 | */ | ||
| 109 | #define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ | ||
| 110 | #define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ | ||
| 111 | |||
| 112 | #define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 113 | #define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 114 | |||
| 115 | #define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ | ||
| 116 | #define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ | ||
| 117 | |||
| 118 | #define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ | ||
| 119 | #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ | ||
| 120 | #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ | ||
| 121 | |||
| 122 | #if 0 | ||
| 123 | /* | ||
| 124 | * PIO pin definitions (peripheral A/B multiplexing). | ||
| 125 | */ | ||
| 126 | |||
| 127 | // TODO: Add | ||
| 128 | |||
| 129 | #endif | ||
| 130 | |||
| 131 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h new file mode 100644 index 000000000000..6fc6e4be624e --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9263_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_MATRIX_H | ||
| 16 | #define AT91SAM9263_MATRIX_H | ||
| 17 | |||
| 18 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 19 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 20 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 21 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 22 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 23 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 24 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 25 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 26 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 27 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 28 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 29 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 30 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 31 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 32 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 33 | |||
| 34 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 35 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 36 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 37 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 38 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 39 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 40 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 41 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 42 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 43 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 44 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 45 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 46 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 47 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 48 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 49 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 50 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 51 | |||
| 52 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 53 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 54 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 55 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 56 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 57 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 58 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 59 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 60 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 61 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 62 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 63 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 64 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 65 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 66 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 67 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 68 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 69 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 70 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 71 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 72 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 73 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 74 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 75 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 76 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 77 | |||
| 78 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 79 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 80 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 81 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 82 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 83 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 84 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 85 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 86 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 87 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 88 | |||
| 89 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
| 90 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 91 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 92 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 93 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 94 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 95 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 96 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 97 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 98 | |||
| 99 | #define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
| 100 | #define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 101 | #define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) | ||
| 102 | #define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) | ||
| 103 | #define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 104 | #define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) | ||
| 105 | #define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 106 | #define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 107 | #define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) | ||
| 108 | #define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) | ||
| 109 | #define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 110 | #define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) | ||
| 111 | #define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) | ||
| 112 | #define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 113 | #define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 114 | #define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) | ||
| 115 | #define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) | ||
| 116 | |||
| 117 | #define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ | ||
| 118 | #define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 119 | #define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) | ||
| 120 | #define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) | ||
| 121 | #define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 122 | #define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) | ||
| 123 | #define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) | ||
| 124 | #define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 125 | #define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 126 | #define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) | ||
| 127 | #define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) | ||
| 128 | |||
| 129 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam926x_mc.h new file mode 100644 index 000000000000..d82631c251f1 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam926x_mc.h | |||
| @@ -0,0 +1,141 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam926x_mc.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (SMC, SDRAMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM926x_MC_H | ||
| 14 | #define AT91SAM926x_MC_H | ||
| 15 | |||
| 16 | /* SDRAM Controller (SDRAMC) registers */ | ||
| 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
| 18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
| 20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
| 21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
| 22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
| 23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
| 24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
| 25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
| 26 | |||
| 27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
| 28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 29 | |||
| 30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
| 31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
| 47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
| 48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
| 49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
| 50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
| 51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
| 52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
| 53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
| 54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
| 55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
| 56 | |||
| 57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
| 58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
| 60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
| 61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
| 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
| 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ | ||
| 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 70 | |||
| 71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
| 72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
| 73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
| 74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
| 75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
| 76 | |||
| 77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
| 78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
| 79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
| 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
| 81 | |||
| 82 | |||
| 83 | /* Static Memory Controller (SMC) registers */ | ||
| 84 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 85 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| 86 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| 87 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| 88 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| 89 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| 90 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| 91 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| 92 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
| 93 | |||
| 94 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 95 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| 96 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| 97 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| 98 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| 99 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| 100 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| 101 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| 102 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
| 103 | |||
| 104 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 105 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| 106 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| 107 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| 108 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
| 109 | |||
| 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| 113 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
| 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
| 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
| 116 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
| 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| 118 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 119 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 120 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| 121 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 122 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 123 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 124 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| 125 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| 126 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| 127 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| 128 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| 129 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 130 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 131 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 132 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 133 | |||
| 134 | #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
| 135 | #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 136 | #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 137 | #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 138 | #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 139 | #endif | ||
| 140 | |||
| 141 | #endif | ||
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h new file mode 100644 index 000000000000..7b9903c2c447 --- /dev/null +++ b/include/asm-arm/arch-at91/board.h | |||
| @@ -0,0 +1,122 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/board.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * These are data structures found in platform_device.dev.platform_data, | ||
| 23 | * and describing board-specific data needed by drivers. For example, | ||
| 24 | * which pin is used for a given GPIO role. | ||
| 25 | * | ||
| 26 | * In 2.6, drivers should strongly avoid board-specific knowledge so | ||
| 27 | * that supporting new boards normally won't require driver patches. | ||
| 28 | * Most board-specific knowledge should be in arch/.../board-*.c files. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef __ASM_ARCH_BOARD_H | ||
| 32 | #define __ASM_ARCH_BOARD_H | ||
| 33 | |||
| 34 | #include <linux/mtd/partitions.h> | ||
| 35 | #include <linux/device.h> | ||
| 36 | #include <linux/spi/spi.h> | ||
| 37 | |||
| 38 | /* USB Device */ | ||
| 39 | struct at91_udc_data { | ||
| 40 | u8 vbus_pin; /* high == host powering us */ | ||
| 41 | u8 pullup_pin; /* high == D+ pulled up */ | ||
| 42 | }; | ||
| 43 | extern void __init at91_add_device_udc(struct at91_udc_data *data); | ||
| 44 | |||
| 45 | /* Compact Flash */ | ||
| 46 | struct at91_cf_data { | ||
| 47 | u8 irq_pin; /* I/O IRQ */ | ||
| 48 | u8 det_pin; /* Card detect */ | ||
| 49 | u8 vcc_pin; /* power switching */ | ||
| 50 | u8 rst_pin; /* card reset */ | ||
| 51 | u8 chipselect; /* EBI Chip Select number */ | ||
| 52 | }; | ||
| 53 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | ||
| 54 | |||
| 55 | /* MMC / SD */ | ||
| 56 | struct at91_mmc_data { | ||
| 57 | u8 det_pin; /* card detect IRQ */ | ||
| 58 | unsigned slot_b:1; /* uses Slot B */ | ||
| 59 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ | ||
| 60 | u8 wp_pin; /* (SD) writeprotect detect */ | ||
| 61 | u8 vcc_pin; /* power switching (high == on) */ | ||
| 62 | }; | ||
| 63 | extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); | ||
| 64 | |||
| 65 | /* Ethernet */ | ||
| 66 | struct at91_eth_data { | ||
| 67 | u8 phy_irq_pin; /* PHY IRQ */ | ||
| 68 | u8 is_rmii; /* using RMII interface? */ | ||
| 69 | }; | ||
| 70 | extern void __init at91_add_device_eth(struct at91_eth_data *data); | ||
| 71 | |||
| 72 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) | ||
| 73 | #define eth_platform_data at91_eth_data | ||
| 74 | #endif | ||
| 75 | |||
| 76 | /* USB Host */ | ||
| 77 | struct at91_usbh_data { | ||
| 78 | u8 ports; /* number of ports on root hub */ | ||
| 79 | u8 vbus_pin[]; /* port power-control pin */ | ||
| 80 | }; | ||
| 81 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | ||
| 82 | |||
| 83 | /* NAND / SmartMedia */ | ||
| 84 | struct at91_nand_data { | ||
| 85 | u8 enable_pin; /* chip enable */ | ||
| 86 | u8 det_pin; /* card detect */ | ||
| 87 | u8 rdy_pin; /* ready/busy */ | ||
| 88 | u8 ale; /* address line number connected to ALE */ | ||
| 89 | u8 cle; /* address line number connected to CLE */ | ||
| 90 | u8 bus_width_16; /* buswidth is 16 bit */ | ||
| 91 | struct mtd_partition* (*partition_info)(int, int*); | ||
| 92 | }; | ||
| 93 | extern void __init at91_add_device_nand(struct at91_nand_data *data); | ||
| 94 | |||
| 95 | /* I2C*/ | ||
| 96 | extern void __init at91_add_device_i2c(void); | ||
| 97 | |||
| 98 | /* SPI */ | ||
| 99 | extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); | ||
| 100 | |||
| 101 | /* Serial */ | ||
| 102 | struct at91_uart_config { | ||
| 103 | unsigned short console_tty; /* tty number of serial console */ | ||
| 104 | unsigned short nr_tty; /* number of serial tty's */ | ||
| 105 | short tty_map[]; /* map UART to tty number */ | ||
| 106 | }; | ||
| 107 | extern struct platform_device *atmel_default_console_device; | ||
| 108 | extern void __init at91_init_serial(struct at91_uart_config *config); | ||
| 109 | |||
| 110 | struct atmel_uart_data { | ||
| 111 | short use_dma_tx; /* use transmit DMA? */ | ||
| 112 | short use_dma_rx; /* use receive DMA? */ | ||
| 113 | void __iomem *regs; /* virtual base address, if any */ | ||
| 114 | }; | ||
| 115 | extern void __init at91_add_device_serial(void); | ||
| 116 | |||
| 117 | /* LEDs */ | ||
| 118 | extern u8 at91_leds_cpu; | ||
| 119 | extern u8 at91_leds_timer; | ||
| 120 | extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); | ||
| 121 | |||
| 122 | #endif | ||
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h new file mode 100644 index 000000000000..d464ca58cdbc --- /dev/null +++ b/include/asm-arm/arch-at91/cpu.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/cpu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_CPU_H | ||
| 14 | #define __ASM_ARCH_CPU_H | ||
| 15 | |||
| 16 | #include <asm/hardware.h> | ||
| 17 | #include <asm/arch/at91_dbgu.h> | ||
| 18 | |||
| 19 | |||
| 20 | #define ARCH_ID_AT91RM9200 0x09290780 | ||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | ||
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | ||
| 23 | #define ARCH_ID_AT91SAM9263 0x019607a0 | ||
| 24 | |||
| 25 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 | ||
| 26 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | ||
| 27 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | ||
| 28 | |||
| 29 | static inline unsigned long at91_cpu_identify(void) | ||
| 30 | { | ||
| 31 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | ||
| 32 | } | ||
| 33 | |||
| 34 | |||
| 35 | #define ARCH_FAMILY_AT91X92 0x09200000 | ||
| 36 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | ||
| 37 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | ||
| 38 | |||
| 39 | static inline unsigned long at91_arch_identify(void) | ||
| 40 | { | ||
| 41 | return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); | ||
| 42 | } | ||
| 43 | |||
| 44 | |||
| 45 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 46 | #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) | ||
| 47 | #else | ||
| 48 | #define cpu_is_at91rm9200() (0) | ||
| 49 | #endif | ||
| 50 | |||
| 51 | #ifdef CONFIG_ARCH_AT91SAM9260 | ||
| 52 | #define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) | ||
| 53 | #define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe()) | ||
| 54 | #else | ||
| 55 | #define cpu_is_at91sam9xe() (0) | ||
| 56 | #define cpu_is_at91sam9260() (0) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifdef CONFIG_ARCH_AT91SAM9261 | ||
| 60 | #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) | ||
| 61 | #else | ||
| 62 | #define cpu_is_at91sam9261() (0) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifdef CONFIG_ARCH_AT91SAM9263 | ||
| 66 | #define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) | ||
| 67 | #else | ||
| 68 | #define cpu_is_at91sam9263() (0) | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #endif | ||
diff --git a/include/asm-arm/arch-at91/debug-macro.S b/include/asm-arm/arch-at91/debug-macro.S new file mode 100644 index 000000000000..13e9f5e1d4ff --- /dev/null +++ b/include/asm-arm/arch-at91/debug-macro.S | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/debug-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Debugging macro include header | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/hardware.h> | ||
| 15 | #include <asm/arch/at91_dbgu.h> | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) | ||
| 21 | ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro senduart,rd,rx | ||
| 25 | strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro waituart,rd,rx | ||
| 29 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 30 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit | ||
| 31 | beq 1001b | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro busyuart,rd,rx | ||
| 35 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 36 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete | ||
| 37 | beq 1001b | ||
| 38 | .endm | ||
| 39 | |||
diff --git a/include/asm-arm/arch-at91/dma.h b/include/asm-arm/arch-at91/dma.h new file mode 100644 index 000000000000..774565412beb --- /dev/null +++ b/include/asm-arm/arch-at91/dma.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S new file mode 100644 index 000000000000..76c8cccf73aa --- /dev/null +++ b/include/asm-arm/arch-at91/entry-macro.S | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Low-level IRQ helper macros for AT91RM9200 platforms | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/hardware.h> | ||
| 14 | #include <asm/arch/at91_aic.h> | ||
| 15 | |||
| 16 | .macro disable_fiq | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 20 | ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral | ||
| 21 | ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) | ||
| 22 | ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number | ||
| 23 | teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt | ||
| 24 | streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. | ||
| 25 | .endm | ||
| 26 | |||
diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h new file mode 100644 index 000000000000..98ad2114f43a --- /dev/null +++ b/include/asm-arm/arch-at91/gpio.h | |||
| @@ -0,0 +1,252 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 14 | #define __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | |||
| 18 | #define PIN_BASE NR_AIC_IRQS | ||
| 19 | |||
| 20 | #define MAX_GPIO_BANKS 5 | ||
| 21 | |||
| 22 | /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ | ||
| 23 | |||
| 24 | #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) | ||
| 25 | #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) | ||
| 26 | #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) | ||
| 27 | #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) | ||
| 28 | #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) | ||
| 29 | #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) | ||
| 30 | #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) | ||
| 31 | #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) | ||
| 32 | #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) | ||
| 33 | #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) | ||
| 34 | #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) | ||
| 35 | #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) | ||
| 36 | #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) | ||
| 37 | #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) | ||
| 38 | #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) | ||
| 39 | #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) | ||
| 40 | #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) | ||
| 41 | #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) | ||
| 42 | #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) | ||
| 43 | #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) | ||
| 44 | #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) | ||
| 45 | #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) | ||
| 46 | #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) | ||
| 47 | #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) | ||
| 48 | #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) | ||
| 49 | #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) | ||
| 50 | #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) | ||
| 51 | #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) | ||
| 52 | #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) | ||
| 53 | #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) | ||
| 54 | #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) | ||
| 55 | #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) | ||
| 56 | |||
| 57 | #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) | ||
| 58 | #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) | ||
| 59 | #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) | ||
| 60 | #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) | ||
| 61 | #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) | ||
| 62 | #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) | ||
| 63 | #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) | ||
| 64 | #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) | ||
| 65 | #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) | ||
| 66 | #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) | ||
| 67 | #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) | ||
| 68 | #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) | ||
| 69 | #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) | ||
| 70 | #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) | ||
| 71 | #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) | ||
| 72 | #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) | ||
| 73 | #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) | ||
| 74 | #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) | ||
| 75 | #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) | ||
| 76 | #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) | ||
| 77 | #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) | ||
| 78 | #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) | ||
| 79 | #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) | ||
| 80 | #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) | ||
| 81 | #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) | ||
| 82 | #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) | ||
| 83 | #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) | ||
| 84 | #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) | ||
| 85 | #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) | ||
| 86 | #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) | ||
| 87 | #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) | ||
| 88 | #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) | ||
| 89 | |||
| 90 | #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) | ||
| 91 | #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) | ||
| 92 | #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) | ||
| 93 | #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) | ||
| 94 | #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) | ||
| 95 | #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) | ||
| 96 | #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) | ||
| 97 | #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) | ||
| 98 | #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) | ||
| 99 | #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) | ||
| 100 | #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) | ||
| 101 | #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) | ||
| 102 | #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) | ||
| 103 | #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) | ||
| 104 | #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) | ||
| 105 | #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) | ||
| 106 | #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) | ||
| 107 | #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) | ||
| 108 | #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) | ||
| 109 | #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) | ||
| 110 | #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) | ||
| 111 | #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) | ||
| 112 | #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) | ||
| 113 | #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) | ||
| 114 | #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) | ||
| 115 | #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) | ||
| 116 | #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) | ||
| 117 | #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) | ||
| 118 | #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) | ||
| 119 | #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) | ||
| 120 | #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) | ||
| 121 | #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) | ||
| 122 | |||
| 123 | #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) | ||
| 124 | #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) | ||
| 125 | #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) | ||
| 126 | #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) | ||
| 127 | #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) | ||
| 128 | #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) | ||
| 129 | #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) | ||
| 130 | #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) | ||
| 131 | #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) | ||
| 132 | #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) | ||
| 133 | #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) | ||
| 134 | #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) | ||
| 135 | #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) | ||
| 136 | #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) | ||
| 137 | #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) | ||
| 138 | #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) | ||
| 139 | #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) | ||
| 140 | #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) | ||
| 141 | #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) | ||
| 142 | #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) | ||
| 143 | #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) | ||
| 144 | #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) | ||
| 145 | #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) | ||
| 146 | #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) | ||
| 147 | #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) | ||
| 148 | #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) | ||
| 149 | #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) | ||
| 150 | #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) | ||
| 151 | #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) | ||
| 152 | #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) | ||
| 153 | #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) | ||
| 154 | #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) | ||
| 155 | |||
| 156 | #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) | ||
| 157 | #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) | ||
| 158 | #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) | ||
| 159 | #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) | ||
| 160 | #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) | ||
| 161 | #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) | ||
| 162 | #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) | ||
| 163 | #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) | ||
| 164 | #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) | ||
| 165 | #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) | ||
| 166 | #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) | ||
| 167 | #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) | ||
| 168 | #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) | ||
| 169 | #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) | ||
| 170 | #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) | ||
| 171 | #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) | ||
| 172 | #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) | ||
| 173 | #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) | ||
| 174 | #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) | ||
| 175 | #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) | ||
| 176 | #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) | ||
| 177 | #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) | ||
| 178 | #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) | ||
| 179 | #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) | ||
| 180 | #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) | ||
| 181 | #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) | ||
| 182 | #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) | ||
| 183 | #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) | ||
| 184 | #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) | ||
| 185 | #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) | ||
| 186 | #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) | ||
| 187 | #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) | ||
| 188 | |||
| 189 | #ifndef __ASSEMBLY__ | ||
| 190 | /* setup setup routines, called from board init or driver probe() */ | ||
| 191 | extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); | ||
| 192 | extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); | ||
| 193 | extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); | ||
| 194 | extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); | ||
| 195 | extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); | ||
| 196 | extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); | ||
| 197 | extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); | ||
| 198 | |||
| 199 | /* callable at any time */ | ||
| 200 | extern int at91_set_gpio_value(unsigned pin, int value); | ||
| 201 | extern int at91_get_gpio_value(unsigned pin); | ||
| 202 | |||
| 203 | /* callable only from core power-management code */ | ||
| 204 | extern void at91_gpio_suspend(void); | ||
| 205 | extern void at91_gpio_resume(void); | ||
| 206 | |||
| 207 | /*-------------------------------------------------------------------------*/ | ||
| 208 | |||
| 209 | /* wrappers for "new style" GPIO calls. the old AT91-specfic ones should | ||
| 210 | * eventually be removed (along with this errno.h inclusion), and the | ||
| 211 | * gpio request/free calls should probably be implemented. | ||
| 212 | */ | ||
| 213 | |||
| 214 | #include <asm/errno.h> | ||
| 215 | |||
| 216 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 217 | { | ||
| 218 | return 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static inline void gpio_free(unsigned gpio) | ||
| 222 | { | ||
| 223 | } | ||
| 224 | |||
| 225 | extern int gpio_direction_input(unsigned gpio); | ||
| 226 | extern int gpio_direction_output(unsigned gpio); | ||
| 227 | |||
| 228 | static inline int gpio_get_value(unsigned gpio) | ||
| 229 | { | ||
| 230 | return at91_get_gpio_value(gpio); | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 234 | { | ||
| 235 | at91_set_gpio_value(gpio, value); | ||
| 236 | } | ||
| 237 | |||
| 238 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 239 | |||
| 240 | static inline int gpio_to_irq(unsigned gpio) | ||
| 241 | { | ||
| 242 | return gpio; | ||
| 243 | } | ||
| 244 | |||
| 245 | static inline int irq_to_gpio(unsigned irq) | ||
| 246 | { | ||
| 247 | return irq; | ||
| 248 | } | ||
| 249 | |||
| 250 | #endif /* __ASSEMBLY__ */ | ||
| 251 | |||
| 252 | #endif | ||
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h new file mode 100644 index 000000000000..eaaf1c12b753 --- /dev/null +++ b/include/asm-arm/arch-at91/hardware.h | |||
| @@ -0,0 +1,90 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * Copyright (C) 2003 ATMEL | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 15 | #define __ASM_ARCH_HARDWARE_H | ||
| 16 | |||
| 17 | #include <asm/sizes.h> | ||
| 18 | |||
| 19 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 20 | #include <asm/arch/at91rm9200.h> | ||
| 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) | ||
| 22 | #include <asm/arch/at91sam9260.h> | ||
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 24 | #include <asm/arch/at91sam9261.h> | ||
| 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 26 | #include <asm/arch/at91sam9263.h> | ||
| 27 | #else | ||
| 28 | #error "Unsupported AT91 processor" | ||
| 29 | #endif | ||
| 30 | |||
| 31 | |||
| 32 | /* | ||
| 33 | * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF | ||
| 34 | * to 0xFEF78000 .. 0xFF000000. (5444Kb) | ||
| 35 | */ | ||
| 36 | #define AT91_IO_PHYS_BASE 0xFFF78000 | ||
| 37 | #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) | ||
| 38 | #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) | ||
| 39 | |||
| 40 | /* Convert a physical IO address to virtual IO address */ | ||
| 41 | #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Virtual to Physical Address mapping for IO devices. | ||
| 45 | */ | ||
| 46 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) | ||
| 47 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) | ||
| 48 | |||
| 49 | /* Internal SRAM is mapped below the IO devices */ | ||
| 50 | #define AT91_SRAM_MAX SZ_1M | ||
| 51 | #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) | ||
| 52 | |||
| 53 | /* Serial ports */ | ||
| 54 | #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ | ||
| 55 | |||
| 56 | /* External Memory Map */ | ||
| 57 | #define AT91_CHIPSELECT_0 0x10000000 | ||
| 58 | #define AT91_CHIPSELECT_1 0x20000000 | ||
| 59 | #define AT91_CHIPSELECT_2 0x30000000 | ||
| 60 | #define AT91_CHIPSELECT_3 0x40000000 | ||
| 61 | #define AT91_CHIPSELECT_4 0x50000000 | ||
| 62 | #define AT91_CHIPSELECT_5 0x60000000 | ||
| 63 | #define AT91_CHIPSELECT_6 0x70000000 | ||
| 64 | #define AT91_CHIPSELECT_7 0x80000000 | ||
| 65 | |||
| 66 | /* SDRAM */ | ||
| 67 | #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 | ||
| 68 | |||
| 69 | /* Clocks */ | ||
| 70 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | ||
| 71 | |||
| 72 | #ifndef __ASSEMBLY__ | ||
| 73 | #include <asm/io.h> | ||
| 74 | |||
| 75 | static inline unsigned int at91_sys_read(unsigned int reg_offset) | ||
| 76 | { | ||
| 77 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 78 | |||
| 79 | return __raw_readl(addr + reg_offset); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) | ||
| 83 | { | ||
| 84 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 85 | |||
| 86 | __raw_writel(value, addr + reg_offset); | ||
| 87 | } | ||
| 88 | #endif | ||
| 89 | |||
| 90 | #endif | ||
diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h new file mode 100644 index 000000000000..401f327ec047 --- /dev/null +++ b/include/asm-arm/arch-at91/io.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IO_H | ||
| 22 | #define __ASM_ARCH_IO_H | ||
| 23 | |||
| 24 | #include <asm/io.h> | ||
| 25 | |||
| 26 | #define IO_SPACE_LIMIT 0xFFFFFFFF | ||
| 27 | |||
| 28 | #define __io(a) ((void __iomem *)(a)) | ||
| 29 | #define __mem_pci(a) (a) | ||
| 30 | |||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h new file mode 100644 index 000000000000..1ffa3bb9a9c1 --- /dev/null +++ b/include/asm-arm/arch-at91/irqs.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | ||
| 22 | #define __ASM_ARCH_IRQS_H | ||
| 23 | |||
| 24 | #include <asm/arch/at91_aic.h> | ||
| 25 | |||
| 26 | #define NR_AIC_IRQS 32 | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * Acknowledge interrupt with AIC after interrupt has been handled. | ||
| 31 | * (by kernel/irq.c) | ||
| 32 | */ | ||
| 33 | #define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) | ||
| 34 | |||
| 35 | |||
| 36 | /* | ||
| 37 | * IRQ interrupt symbols are the AT91xxx_ID_* symbols | ||
| 38 | * for IRQs handled directly through the AIC, or else the AT91_PIN_* | ||
| 39 | * symbols in gpio.h for ones handled indirectly as GPIOs. | ||
| 40 | * We make provision for 5 banks of GPIO. | ||
| 41 | */ | ||
| 42 | #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) | ||
| 43 | |||
| 44 | #endif | ||
diff --git a/include/asm-arm/arch-at91/memory.h b/include/asm-arm/arch-at91/memory.h new file mode 100644 index 000000000000..4835d6784509 --- /dev/null +++ b/include/asm-arm/arch-at91/memory.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 22 | #define __ASM_ARCH_MEMORY_H | ||
| 23 | |||
| 24 | #include <asm/hardware.h> | ||
| 25 | |||
| 26 | #define PHYS_OFFSET (AT91_SDRAM_BASE) | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * Virtual view <-> DMA view memory address translations | ||
| 31 | * virt_to_bus: Used to translate the virtual address to an | ||
| 32 | * address suitable to be passed to set_dma_addr | ||
| 33 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 34 | * to an address that the kernel can use. | ||
| 35 | */ | ||
| 36 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 37 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-at91/system.h b/include/asm-arm/arch-at91/system.h new file mode 100644 index 000000000000..6bf846098ea9 --- /dev/null +++ b/include/asm-arm/arch-at91/system.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/hardware.h> | ||
| 25 | #include <asm/arch/at91_st.h> | ||
| 26 | #include <asm/arch/at91_dbgu.h> | ||
| 27 | |||
| 28 | static inline void arch_idle(void) | ||
| 29 | { | ||
| 30 | /* | ||
| 31 | * Disable the processor clock. The processor will be automatically | ||
| 32 | * re-enabled by an interrupt or by a reset. | ||
| 33 | */ | ||
| 34 | // at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Set the processor (CP15) into 'Wait for Interrupt' mode. | ||
| 38 | * Unlike disabling the processor clock via the PMC (above) | ||
| 39 | * this allows the processor to be woken via JTAG. | ||
| 40 | */ | ||
| 41 | cpu_do_idle(); | ||
| 42 | } | ||
| 43 | |||
| 44 | void (*at91_arch_reset)(void); | ||
| 45 | |||
| 46 | static inline void arch_reset(char mode) | ||
| 47 | { | ||
| 48 | /* call the CPU-specific reset function */ | ||
| 49 | if (at91_arch_reset) | ||
| 50 | (at91_arch_reset)(); | ||
| 51 | } | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h new file mode 100644 index 000000000000..f41636d607a2 --- /dev/null +++ b/include/asm-arm/arch-at91/timex.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 22 | #define __ASM_ARCH_TIMEX_H | ||
| 23 | |||
| 24 | #include <asm/hardware.h> | ||
| 25 | |||
| 26 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 27 | |||
| 28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | ||
| 29 | |||
| 30 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) | ||
| 31 | |||
| 32 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 33 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 34 | |||
| 35 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 36 | |||
| 37 | #define AT91SAM9_MASTER_CLOCK 99959500 | ||
| 38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 39 | |||
| 40 | #endif | ||
| 41 | |||
| 42 | #endif | ||
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h new file mode 100644 index 000000000000..a193d28304b6 --- /dev/null +++ b/include/asm-arm/arch-at91/uncompress.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 22 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 23 | |||
| 24 | #include <asm/hardware.h> | ||
| 25 | #include <asm/arch/at91_dbgu.h> | ||
| 26 | |||
| 27 | /* | ||
| 28 | * The following code assumes the serial port has already been | ||
| 29 | * initialized by the bootloader. If you didn't setup a port in | ||
| 30 | * your bootloader then nothing will appear (which might be desired). | ||
| 31 | * | ||
| 32 | * This does not append a newline | ||
| 33 | */ | ||
| 34 | static void putc(int c) | ||
| 35 | { | ||
| 36 | void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ | ||
| 37 | |||
| 38 | while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) | ||
| 39 | barrier(); | ||
| 40 | __raw_writel(c, sys + AT91_DBGU_THR); | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline void flush(void) | ||
| 44 | { | ||
| 45 | void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ | ||
| 46 | |||
| 47 | /* wait for transmission to complete */ | ||
| 48 | while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) | ||
| 49 | barrier(); | ||
| 50 | } | ||
| 51 | |||
| 52 | #define arch_decomp_setup() | ||
| 53 | |||
| 54 | #define arch_decomp_wdog() | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/include/asm-arm/arch-at91/vmalloc.h b/include/asm-arm/arch-at91/vmalloc.h new file mode 100644 index 000000000000..bb05e70e932a --- /dev/null +++ b/include/asm-arm/arch-at91/vmalloc.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 22 | #define __ASM_ARCH_VMALLOC_H | ||
| 23 | |||
| 24 | #define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) | ||
| 25 | |||
| 26 | #endif | ||