[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories

Now that Linux includes support for the Atmel AT91SAM9260 and
AT91SAM9261 processors in addition to the original Atmel AT91RM9200
(with support for more AT91 processors pending), the "mach-at91rm9200"
and "arch-at91rm9200" directories should be renamed to indicate their
more generic nature.

The following git commands should be run BEFORE applying this patch:
  git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91
  git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 134 insertions, 0 deletions

diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam926x_mc.h
new file mode 100644
index 000000000000..355eee67ebca
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam926x_mc.h
@@ -0,0 +1,134 @@
+/*
+ * include/asm-arm/arch-at91/at91sam926x_mc.h
+ *
+ * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM926x_MC_H
+#define AT91SAM926x_MC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
+#define                 AT91_SDRAMC_MODE_NORMAL         0
+#define                 AT91_SDRAMC_MODE_NOP            1
+#define                 AT91_SDRAMC_MODE_PRECHARGE      2
+#define                 AT91_SDRAMC_MODE_LMR            3
+#define                 AT91_SDRAMC_MODE_REFRESH        4
+#define                 AT91_SDRAMC_MODE_EXT_LMR        5
+#define                 AT91_SDRAMC_MODE_DEEP           6
+
+#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
+#define                 AT91_SDRAMC_NC_8        (0 << 0)
+#define                 AT91_SDRAMC_NC_9        (1 << 0)
+#define                 AT91_SDRAMC_NC_10       (2 << 0)
+#define                 AT91_SDRAMC_NC_11       (3 << 0)
+#define         AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
+#define                 AT91_SDRAMC_NR_11       (0 << 2)
+#define                 AT91_SDRAMC_NR_12       (1 << 2)
+#define                 AT91_SDRAMC_NR_13       (2 << 2)
+#define         AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
+#define                 AT91_SDRAMC_NB_2        (0 << 4)
+#define                 AT91_SDRAMC_NB_4        (1 << 4)
+#define         AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
+#define                 AT91_SDRAMC_CAS_1       (1 << 5)
+#define                 AT91_SDRAMC_CAS_2       (2 << 5)
+#define                 AT91_SDRAMC_CAS_3       (3 << 5)
+#define         AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
+#define                 AT91_SDRAMC_DBW_32      (0 << 7)
+#define                 AT91_SDRAMC_DBW_16      (1 << 7)
+#define         AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
+#define         AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
+#define         AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
+#define         AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
+#define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
+#define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
+#define                 AT91_SDRAMC_LPCB_DISABLE                0
+#define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
+#define                 AT91_SDRAMC_LPCB_POWER_DOWN             2
+#define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+#define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
+#define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
+
+#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
+#define                 AT91_SDRAMC_MD_SDRAM            0
+#define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
+
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+
+#endif