[ARM] 4657/1: AT91: Header definition update

Add definitions of registers / bits found on some AT91SAM9 processors

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 11 insertions, 0 deletions

diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a90733456..f9f2e3cd95c5 100644
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
 #define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
 #define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
 #define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
+#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
 #define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
 
 #define AT91_TWI_MMR            0x04            /* Master Mode Register */
@@ -32,6 +34,9 @@
 #define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
 #define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
 
+#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
+#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
+
 #define AT91_TWI_IADR           0x0c            /* Internal Address Register */
 
 #define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
 #define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
+#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
+#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
 #define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
 #define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
+#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
+#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
 
 #define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
 #define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */