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authorAndrew Victor <andrew@sanpeople.com>2007-02-05 05:42:07 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:50:56 -0500
commit9d0412680e6c7b685ee466842047bcfb924d6dc5 (patch)
treec79300964ef1aca5d24571696f95e76b37c14679 /include/asm-arm/arch-at91/at91_pmc.h
parenta93d48cc6019f84394b31d10c0d830a3b71696be (diff)
[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories
Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91/at91_pmc.h')
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h92
1 files changed, 92 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
new file mode 100644
index 000000000000..33ff5b6798ee
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -0,0 +1,92 @@
1/*
2 * include/asm-arm/arch-at91/at91_pmc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Power Management Controller (PMC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PMC_H
17#define AT91_PMC_H
18
19#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
20#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
21
22#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
28#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
29#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
30#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
31#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
32#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
33#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
34#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
35
36#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
37#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
38#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
39
40#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
41#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
42#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
43#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
44
45#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
46#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
47#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
48
49#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
50#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
51#define AT91_PMC_DIV (0xff << 0) /* Divider */
52#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
53#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
54#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
55#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
56
57#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
58#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
59#define AT91_PMC_CSS_SLOW (0 << 0)
60#define AT91_PMC_CSS_MAIN (1 << 0)
61#define AT91_PMC_CSS_PLLA (2 << 0)
62#define AT91_PMC_CSS_PLLB (3 << 0)
63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
64#define AT91_PMC_PRES_1 (0 << 2)
65#define AT91_PMC_PRES_2 (1 << 2)
66#define AT91_PMC_PRES_4 (2 << 2)
67#define AT91_PMC_PRES_8 (3 << 2)
68#define AT91_PMC_PRES_16 (4 << 2)
69#define AT91_PMC_PRES_32 (5 << 2)
70#define AT91_PMC_PRES_64 (6 << 2)
71#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
72#define AT91_PMC_MDIV_1 (0 << 8)
73#define AT91_PMC_MDIV_2 (1 << 8)
74#define AT91_PMC_MDIV_3 (2 << 8)
75#define AT91_PMC_MDIV_4 (3 << 8)
76
77#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
78
79#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
80#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
81#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
82#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
83#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
84#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
85#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
86#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
87#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
88#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
89#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
90#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
91
92#endif