ACPI: Processor native C-states using MWAIT

Intel processors starting with the Core Duo support
support processor native C-state using the MWAIT instruction.
Refer: Intel Architecture Software Developer's Manual
http://www.intel.com/design/Pentium4/manuals/253668.htm

Platform firmware exports the support for Native C-state to OS using
ACPI _PDC and _CST methods.
Refer: Intel Processor Vendor-Specific ACPI: Interface Specification
http://www.intel.com/technology/iapc/acpi/downloads/302223.htm

With Processor Native C-state, we use 'MWAIT' instruction on the processor
to enter different C-states (C1, C2, C3).  We won't use the special IO
ports to enter C-state and no SMM mode etc required to enter C-state.
Overall this will mean better C-state support.

One major advantage of using MWAIT for all C-states is, with this and
"treat interrupt as break event" feature of MWAIT, we can now get accurate
timing for the time spent in C1, C2, ..  states.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Len Brown <len.brown@intel.com>

2 files changed, 24 insertions, 3 deletions

diff --git a/include/acpi/pdc_intel.h b/include/acpi/pdc_intel.h
index c5472be6f3a2..e72bfdd887f9 100644
--- a/include/acpi/pdc_intel.h
+++ b/include/acpi/pdc_intel.h
@@ -13,6 +13,7 @@
 #define ACPI_PDC_SMP_C_SWCOORD          (0x0040)
 #define ACPI_PDC_SMP_T_SWCOORD          (0x0080)
 #define ACPI_PDC_C_C1_FFH               (0x0100)
+#define ACPI_PDC_C_C2C3_FFH             (0x0200)
 
 #define ACPI_PDC_EST_CAPABILITY_SMP     (ACPI_PDC_SMP_C1PT | \
                                          ACPI_PDC_C_C1_HALT | \
@@ -23,8 +24,10 @@
                                          ACPI_PDC_SMP_P_SWCOORD | \
                                          ACPI_PDC_P_FFH)
 
-#define ACPI_PDC_C_CAPABILITY_SMP       (ACPI_PDC_SMP_C2C3 | \
-                                         ACPI_PDC_SMP_C1PT | \
-                                         ACPI_PDC_C_C1_HALT)
+#define ACPI_PDC_C_CAPABILITY_SMP       (ACPI_PDC_SMP_C2C3  | \
+                                         ACPI_PDC_SMP_C1PT  | \
+                                         ACPI_PDC_C_C1_HALT | \
+                                         ACPI_PDC_C_C1_FFH  | \
+                                         ACPI_PDC_C_C2C3_FFH)
 
 #endif                          /* __PDC_INTEL_H__ */
diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 9dd5b75961f8..7798d2a9f793 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -29,6 +29,9 @@
 #define DOMAIN_COORD_TYPE_SW_ANY        0xfd
 #define DOMAIN_COORD_TYPE_HW_ALL        0xfe
 
+#define ACPI_CSTATE_SYSTEMIO    (0)
+#define ACPI_CSTATE_FFH         (1)
+
 /* Power Management */
 
 struct acpi_processor_cx;
@@ -58,6 +61,8 @@ struct acpi_processor_cx {
         u8 valid;
         u8 type;
         u32 address;
+        u8 space_id;
+        u8 index;
         u32 latency;
         u32 latency_ticks;
         u32 power;
@@ -206,6 +211,9 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr);
 #ifdef ARCH_HAS_POWER_INIT
 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                                         unsigned int cpu);
+int acpi_processor_ffh_cstate_probe(unsigned int cpu,
+                struct acpi_processor_cx *cx, struct acpi_power_register *reg);
+void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cstate);
 #else
 static inline void acpi_processor_power_init_bm_check(struct
                                                       acpi_processor_flags
@@ -214,6 +222,16 @@ static inline void acpi_processor_power_init_bm_check(struct
         flags->bm_check = 1;
         return;
 }
+static inline int acpi_processor_ffh_cstate_probe(unsigned int cpu,
+                struct acpi_processor_cx *cx, struct acpi_power_register *reg)
+{
+        return -1;
+}
+static inline void acpi_processor_ffh_cstate_enter(
+                struct acpi_processor_cx *cstate)
+{
+        return;
+}
 #endif
 
 /* in processor_perflib.c */