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authorGajanan Bhat <gajanan.bhat@intel.com>2012-09-27 09:43:07 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-28 11:04:38 -0400
commit19c03924d4b72eedff517f80edc6b33c14f0fe53 (patch)
tree8b07b8854e7d848e878c06584f94ab74854853dc /fs/fat
parent2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8 (diff)
drm/i915: Add eDP support for Valleyview
Eventhough Valleyview display block is derived from Cantiga, VLV supports eDP. So, added eDP checks in i9xx_crtc_mode_set path. v2: use different DPIO_DIVISOR values for VGA, DP and eDP v3: fix DPIO value calculation to use same values for all display interfaces v4: removed unconditional enabling of 6bpc dithering based on comments from Daniel & Jani Nikula. Also changed the display enabling order to force eDP detection first. Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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