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authorDavid Brownell <david-b@pacbell.net>2005-09-02 21:58:09 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2005-09-12 15:23:43 -0400
commitf7201c3dcd7799f2aa3d6ec427b194225360ecee (patch)
tree1abe4c11c210f88de270e230a61d3e0d7e96b107 /drivers
parent10f6524a8ef1413a8cbd952673997013183fe2a9 (diff)
[PATCH] USB: EHCI workaround for NForce and mem > 2GB
NVidia reports (via Mark Overby) that some of their EHCI controllers don't like certain data structure addresses beyond the 2GB mark. He provided an earlier version of this patch. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/host/ehci-hcd.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2f7037c62e88..ae5ba4ddfb40 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -400,6 +400,23 @@ static int ehci_hc_reset (struct usb_hcd *hcd)
400 return -EIO; 400 return -EIO;
401 } 401 }
402 break; 402 break;
403 case PCI_VENDOR_ID_NVIDIA:
404 /* NVidia reports that certain chips don't handle
405 * QH, ITD, or SITD addresses above 2GB. (But TD,
406 * data buffer, and periodic schedule are normal.)
407 */
408 switch (pdev->device) {
409 case 0x003c: /* MCP04 */
410 case 0x005b: /* CK804 */
411 case 0x00d8: /* CK8 */
412 case 0x00e8: /* CK8S */
413 if (pci_set_consistent_dma_mask(pdev,
414 DMA_31BIT_MASK) < 0)
415 ehci_warn (ehci, "can't enable NVidia "
416 "workaround for >2GB RAM\n");
417 break;
418 }
419 break;
403 } 420 }
404 421
405 /* optional debug port, normally in the first BAR */ 422 /* optional debug port, normally in the first BAR */