aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2013-04-22 20:23:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:30:12 -0400
commita412fce0548105f14e48d25094d98fc87f7c0df4 (patch)
treec5fbc81c66465ebe4eb8aefcb2c12dd362f1e579 /drivers
parent84a9d9eeabdca05321a7c890eef485770dade012 (diff)
drm/radeon/cik: add rlc helpers for DPM
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/cik.c29
-rw-r--r--drivers/gpu/drm/radeon/cikd.h9
2 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index a36e98c9a875..727c296662f1 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5587,6 +5587,35 @@ static u32 cik_halt_rlc(struct radeon_device *rdev)
5587 return orig; 5587 return orig;
5588} 5588}
5589 5589
5590void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
5591{
5592 u32 tmp, i, mask;
5593
5594 tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5595 WREG32(RLC_GPR_REG2, tmp);
5596
5597 mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
5598 for (i = 0; i < rdev->usec_timeout; i++) {
5599 if ((RREG32(RLC_GPM_STAT) & mask) == mask)
5600 break;
5601 udelay(1);
5602 }
5603
5604 for (i = 0; i < rdev->usec_timeout; i++) {
5605 if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
5606 break;
5607 udelay(1);
5608 }
5609}
5610
5611void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
5612{
5613 u32 tmp;
5614
5615 tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5616 WREG32(RLC_GPR_REG2, tmp);
5617}
5618
5590/** 5619/**
5591 * cik_rlc_stop - stop the RLC ME 5620 * cik_rlc_stop - stop the RLC ME
5592 * 5621 *
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 63955abb1e11..116b3131a683 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -952,6 +952,8 @@
952 952
953#define RLC_GPM_STAT 0xC400 953#define RLC_GPM_STAT 0xC400
954# define RLC_GPM_BUSY (1 << 0) 954# define RLC_GPM_BUSY (1 << 0)
955# define GFX_POWER_STATUS (1 << 1)
956# define GFX_CLOCK_STATUS (1 << 2)
955 957
956#define RLC_PG_CNTL 0xC40C 958#define RLC_PG_CNTL 0xC40C
957# define GFX_PG_ENABLE (1 << 0) 959# define GFX_PG_ENABLE (1 << 0)
@@ -1004,6 +1006,13 @@
1004#define RLC_GPM_SCRATCH_ADDR 0xC4B0 1006#define RLC_GPM_SCRATCH_ADDR 0xC4B0
1005#define RLC_GPM_SCRATCH_DATA 0xC4B4 1007#define RLC_GPM_SCRATCH_DATA 0xC4B4
1006 1008
1009#define RLC_GPR_REG2 0xC4E8
1010#define REQ 0x00000001
1011#define MESSAGE(x) ((x) << 1)
1012#define MESSAGE_MASK 0x0000001e
1013#define MSG_ENTER_RLC_SAFE_MODE 1
1014#define MSG_EXIT_RLC_SAFE_MODE 0
1015
1007#define CP_HPD_EOP_BASE_ADDR 0xC904 1016#define CP_HPD_EOP_BASE_ADDR 0xC904
1008#define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1017#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1009#define CP_HPD_EOP_VMID 0xC90C 1018#define CP_HPD_EOP_VMID 0xC90C