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authorEilon Greenstein <eilong@broadcom.com>2009-08-12 04:24:25 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-13 02:03:00 -0400
commit9c63de6293775b537614550fd61075a33ada9469 (patch)
tree67909f9fb8b1ee50c3932b366bbd4c763f5c67c8 /drivers
parent45a4864d80264f6708528dcaa2c5c0b3933a8d7f (diff)
bnx2x: Removing unused definitions
Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x_reg.h811
1 files changed, 0 insertions, 811 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 1e6f5aa4eb5a..95ebf3fb3e89 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -190,12 +190,6 @@
190 _(0..15) stands for the connection type (one of 16). */ 190 _(0..15) stands for the connection type (one of 16). */
191#define CCM_REG_N_SM_CTX_LD_0 0xd004c 191#define CCM_REG_N_SM_CTX_LD_0 0xd004c
192#define CCM_REG_N_SM_CTX_LD_1 0xd0050 192#define CCM_REG_N_SM_CTX_LD_1 0xd0050
193#define CCM_REG_N_SM_CTX_LD_10 0xd0074
194#define CCM_REG_N_SM_CTX_LD_11 0xd0078
195#define CCM_REG_N_SM_CTX_LD_12 0xd007c
196#define CCM_REG_N_SM_CTX_LD_13 0xd0080
197#define CCM_REG_N_SM_CTX_LD_14 0xd0084
198#define CCM_REG_N_SM_CTX_LD_15 0xd0088
199#define CCM_REG_N_SM_CTX_LD_2 0xd0054 193#define CCM_REG_N_SM_CTX_LD_2 0xd0054
200#define CCM_REG_N_SM_CTX_LD_3 0xd0058 194#define CCM_REG_N_SM_CTX_LD_3 0xd0058
201#define CCM_REG_N_SM_CTX_LD_4 0xd005c 195#define CCM_REG_N_SM_CTX_LD_4 0xd005c
@@ -622,24 +616,6 @@
622#define DMAE_REG_GO_C1 0x102084 616#define DMAE_REG_GO_C1 0x102084
623/* [RW 1] Command 10 go. */ 617/* [RW 1] Command 10 go. */
624#define DMAE_REG_GO_C10 0x102088 618#define DMAE_REG_GO_C10 0x102088
625#define DMAE_REG_GO_C10_SIZE 1
626/* [RW 1] Command 11 go. */
627#define DMAE_REG_GO_C11 0x10208c
628#define DMAE_REG_GO_C11_SIZE 1
629/* [RW 1] Command 12 go. */
630#define DMAE_REG_GO_C12 0x102090
631#define DMAE_REG_GO_C12_SIZE 1
632/* [RW 1] Command 13 go. */
633#define DMAE_REG_GO_C13 0x102094
634#define DMAE_REG_GO_C13_SIZE 1
635/* [RW 1] Command 14 go. */
636#define DMAE_REG_GO_C14 0x102098
637#define DMAE_REG_GO_C14_SIZE 1
638/* [RW 1] Command 15 go. */
639#define DMAE_REG_GO_C15 0x10209c
640#define DMAE_REG_GO_C15_SIZE 1
641/* [RW 1] Command 10 go. */
642#define DMAE_REG_GO_C10 0x102088
643/* [RW 1] Command 11 go. */ 619/* [RW 1] Command 11 go. */
644#define DMAE_REG_GO_C11 0x10208c 620#define DMAE_REG_GO_C11 0x10208c
645/* [RW 1] Command 12 go. */ 621/* [RW 1] Command 12 go. */
@@ -789,7 +765,6 @@
789#define MCP_REG_MCPR_NVM_READ 0x86410 765#define MCP_REG_MCPR_NVM_READ 0x86410
790#define MCP_REG_MCPR_NVM_SW_ARB 0x86420 766#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
791#define MCP_REG_MCPR_NVM_WRITE 0x86408 767#define MCP_REG_MCPR_NVM_WRITE 0x86408
792#define MCP_REG_MCPR_NVM_WRITE1 0x86428
793#define MCP_REG_MCPR_SCRATCH 0xa0000 768#define MCP_REG_MCPR_SCRATCH 0xa0000
794/* [R 32] read first 32 bit after inversion of function 0. mapped as 769/* [R 32] read first 32 bit after inversion of function 0. mapped as
795 follows: [0] NIG attention for function0; [1] NIG attention for 770 follows: [0] NIG attention for function0; [1] NIG attention for
@@ -1175,19 +1150,7 @@
1175#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1150#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1176#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1151#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1177#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1152#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1178#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1179#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1180#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1181#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1182#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1183#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1184#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1185#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1186#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1187#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1188#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1153#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1189#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1190#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1191#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1154#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1192#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1155#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1193#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1156#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
@@ -1279,133 +1242,7 @@
1279 set. if the appropriate bit is clear (the driver request to free a client 1242 set. if the appropriate bit is clear (the driver request to free a client
1280 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1243 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1281 be asserted). */ 1244 be asserted). */
1282#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1283#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1284/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1285 32 clients. Each client can be controlled by one driver only. One in each
1286 bit represent that this driver control the appropriate client (Ex: bit 5
1287 is set means this driver control client number 5). addr1 = set; addr0 =
1288 clear; read from both addresses will give the same result = status. write
1289 to address 1 will set a request to control all the clients that their
1290 appropriate bit (in the write command) is set. if the client is free (the
1291 appropriate bit in all the other drivers is clear) one will be written to
1292 that driver register; if the client isn't free the bit will remain zero.
1293 if the appropriate bit is set (the driver request to gain control on a
1294 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1295 interrupt will be asserted). write to address 0 will set a request to
1296 free all the clients that their appropriate bit (in the write command) is
1297 set. if the appropriate bit is clear (the driver request to free a client
1298 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1299 be asserted). */
1300#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1301#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1302/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1303 32 clients. Each client can be controlled by one driver only. One in each
1304 bit represent that this driver control the appropriate client (Ex: bit 5
1305 is set means this driver control client number 5). addr1 = set; addr0 =
1306 clear; read from both addresses will give the same result = status. write
1307 to address 1 will set a request to control all the clients that their
1308 appropriate bit (in the write command) is set. if the client is free (the
1309 appropriate bit in all the other drivers is clear) one will be written to
1310 that driver register; if the client isn't free the bit will remain zero.
1311 if the appropriate bit is set (the driver request to gain control on a
1312 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1313 interrupt will be asserted). write to address 0 will set a request to
1314 free all the clients that their appropriate bit (in the write command) is
1315 set. if the appropriate bit is clear (the driver request to free a client
1316 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1317 be asserted). */
1318#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1319#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1320/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1321 32 clients. Each client can be controlled by one driver only. One in each
1322 bit represent that this driver control the appropriate client (Ex: bit 5
1323 is set means this driver control client number 5). addr1 = set; addr0 =
1324 clear; read from both addresses will give the same result = status. write
1325 to address 1 will set a request to control all the clients that their
1326 appropriate bit (in the write command) is set. if the client is free (the
1327 appropriate bit in all the other drivers is clear) one will be written to
1328 that driver register; if the client isn't free the bit will remain zero.
1329 if the appropriate bit is set (the driver request to gain control on a
1330 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1331 interrupt will be asserted). write to address 0 will set a request to
1332 free all the clients that their appropriate bit (in the write command) is
1333 set. if the appropriate bit is clear (the driver request to free a client
1334 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1335 be asserted). */
1336#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1337#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1338/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1339 32 clients. Each client can be controlled by one driver only. One in each
1340 bit represent that this driver control the appropriate client (Ex: bit 5
1341 is set means this driver control client number 5). addr1 = set; addr0 =
1342 clear; read from both addresses will give the same result = status. write
1343 to address 1 will set a request to control all the clients that their
1344 appropriate bit (in the write command) is set. if the client is free (the
1345 appropriate bit in all the other drivers is clear) one will be written to
1346 that driver register; if the client isn't free the bit will remain zero.
1347 if the appropriate bit is set (the driver request to gain control on a
1348 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1349 interrupt will be asserted). write to address 0 will set a request to
1350 free all the clients that their appropriate bit (in the write command) is
1351 set. if the appropriate bit is clear (the driver request to free a client
1352 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1353 be asserted). */
1354#define MISC_REG_DRIVER_CONTROL_1 0xa510 1245#define MISC_REG_DRIVER_CONTROL_1 0xa510
1355#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1356#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1357/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1358 32 clients. Each client can be controlled by one driver only. One in each
1359 bit represent that this driver control the appropriate client (Ex: bit 5
1360 is set means this driver control client number 5). addr1 = set; addr0 =
1361 clear; read from both addresses will give the same result = status. write
1362 to address 1 will set a request to control all the clients that their
1363 appropriate bit (in the write command) is set. if the client is free (the
1364 appropriate bit in all the other drivers is clear) one will be written to
1365 that driver register; if the client isn't free the bit will remain zero.
1366 if the appropriate bit is set (the driver request to gain control on a
1367 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1368 interrupt will be asserted). write to address 0 will set a request to
1369 free all the clients that their appropriate bit (in the write command) is
1370 set. if the appropriate bit is clear (the driver request to free a client
1371 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1372 be asserted). */
1373#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1374#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1375/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1376 32 clients. Each client can be controlled by one driver only. One in each
1377 bit represent that this driver control the appropriate client (Ex: bit 5
1378 is set means this driver control client number 5). addr1 = set; addr0 =
1379 clear; read from both addresses will give the same result = status. write
1380 to address 1 will set a request to control all the clients that their
1381 appropriate bit (in the write command) is set. if the client is free (the
1382 appropriate bit in all the other drivers is clear) one will be written to
1383 that driver register; if the client isn't free the bit will remain zero.
1384 if the appropriate bit is set (the driver request to gain control on a
1385 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1386 interrupt will be asserted). write to address 0 will set a request to
1387 free all the clients that their appropriate bit (in the write command) is
1388 set. if the appropriate bit is clear (the driver request to free a client
1389 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1390 be asserted). */
1391#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1392#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1393/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1394 32 clients. Each client can be controlled by one driver only. One in each
1395 bit represent that this driver control the appropriate client (Ex: bit 5
1396 is set means this driver control client number 5). addr1 = set; addr0 =
1397 clear; read from both addresses will give the same result = status. write
1398 to address 1 will set a request to control all the clients that their
1399 appropriate bit (in the write command) is set. if the client is free (the
1400 appropriate bit in all the other drivers is clear) one will be written to
1401 that driver register; if the client isn't free the bit will remain zero.
1402 if the appropriate bit is set (the driver request to gain control on a
1403 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1404 interrupt will be asserted). write to address 0 will set a request to
1405 free all the clients that their appropriate bit (in the write command) is
1406 set. if the appropriate bit is clear (the driver request to free a client
1407 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1408 be asserted). */
1409#define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1246#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1410/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1247/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1411 only. */ 1248 only. */
@@ -1650,8 +1487,6 @@
1650/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1487/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1651 to emac for port0; other way to bmac for port0 */ 1488 to emac for port0; other way to bmac for port0 */
1652#define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1489#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1653/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1654#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1655/* [RW 1] Input enable for TX PBF user packet port0 IF */ 1490/* [RW 1] Input enable for TX PBF user packet port0 IF */
1656#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1491#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1657/* [RW 1] Input enable for TX PBF user packet port1 IF */ 1492/* [RW 1] Input enable for TX PBF user packet port1 IF */
@@ -2161,11 +1996,8 @@
2161#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 1996#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2162#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 1997#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2163#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 1998#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2164#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2165#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2166#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 1999#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2167#define PXP2_REG_PSWRQ_BW_ADD28 0x120228 2000#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2168#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2169#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 2001#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2170#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 2002#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2171#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 2003#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
@@ -2175,11 +2007,8 @@
2175#define PXP2_REG_PSWRQ_BW_L1 0x1202b0 2007#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2176#define PXP2_REG_PSWRQ_BW_L10 0x1202d4 2008#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2177#define PXP2_REG_PSWRQ_BW_L11 0x1202d8 2009#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2178#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2179#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2180#define PXP2_REG_PSWRQ_BW_L2 0x1202b4 2010#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2181#define PXP2_REG_PSWRQ_BW_L28 0x120318 2011#define PXP2_REG_PSWRQ_BW_L28 0x120318
2182#define PXP2_REG_PSWRQ_BW_L28 0x120318
2183#define PXP2_REG_PSWRQ_BW_L3 0x1202b8 2012#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2184#define PXP2_REG_PSWRQ_BW_L6 0x1202c4 2013#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2185#define PXP2_REG_PSWRQ_BW_L7 0x1202c8 2014#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
@@ -2189,11 +2018,8 @@
2189#define PXP2_REG_PSWRQ_BW_UB1 0x120238 2018#define PXP2_REG_PSWRQ_BW_UB1 0x120238
2190#define PXP2_REG_PSWRQ_BW_UB10 0x12025c 2019#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2191#define PXP2_REG_PSWRQ_BW_UB11 0x120260 2020#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2192#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2193#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2194#define PXP2_REG_PSWRQ_BW_UB2 0x12023c 2021#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2195#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 2022#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2196#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2197#define PXP2_REG_PSWRQ_BW_UB3 0x120240 2023#define PXP2_REG_PSWRQ_BW_UB3 0x120240
2198#define PXP2_REG_PSWRQ_BW_UB6 0x12024c 2024#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2199#define PXP2_REG_PSWRQ_BW_UB7 0x120250 2025#define PXP2_REG_PSWRQ_BW_UB7 0x120250
@@ -2784,16 +2610,6 @@
2784#define QM_REG_QVOQIDX_107 0x16e4b8 2610#define QM_REG_QVOQIDX_107 0x16e4b8
2785#define QM_REG_QVOQIDX_108 0x16e4bc 2611#define QM_REG_QVOQIDX_108 0x16e4bc
2786#define QM_REG_QVOQIDX_109 0x16e4c0 2612#define QM_REG_QVOQIDX_109 0x16e4c0
2787#define QM_REG_QVOQIDX_100 0x16e49c
2788#define QM_REG_QVOQIDX_101 0x16e4a0
2789#define QM_REG_QVOQIDX_102 0x16e4a4
2790#define QM_REG_QVOQIDX_103 0x16e4a8
2791#define QM_REG_QVOQIDX_104 0x16e4ac
2792#define QM_REG_QVOQIDX_105 0x16e4b0
2793#define QM_REG_QVOQIDX_106 0x16e4b4
2794#define QM_REG_QVOQIDX_107 0x16e4b8
2795#define QM_REG_QVOQIDX_108 0x16e4bc
2796#define QM_REG_QVOQIDX_109 0x16e4c0
2797#define QM_REG_QVOQIDX_11 0x168120 2613#define QM_REG_QVOQIDX_11 0x168120
2798#define QM_REG_QVOQIDX_110 0x16e4c4 2614#define QM_REG_QVOQIDX_110 0x16e4c4
2799#define QM_REG_QVOQIDX_111 0x16e4c8 2615#define QM_REG_QVOQIDX_111 0x16e4c8
@@ -2805,16 +2621,6 @@
2805#define QM_REG_QVOQIDX_117 0x16e4e0 2621#define QM_REG_QVOQIDX_117 0x16e4e0
2806#define QM_REG_QVOQIDX_118 0x16e4e4 2622#define QM_REG_QVOQIDX_118 0x16e4e4
2807#define QM_REG_QVOQIDX_119 0x16e4e8 2623#define QM_REG_QVOQIDX_119 0x16e4e8
2808#define QM_REG_QVOQIDX_110 0x16e4c4
2809#define QM_REG_QVOQIDX_111 0x16e4c8
2810#define QM_REG_QVOQIDX_112 0x16e4cc
2811#define QM_REG_QVOQIDX_113 0x16e4d0
2812#define QM_REG_QVOQIDX_114 0x16e4d4
2813#define QM_REG_QVOQIDX_115 0x16e4d8
2814#define QM_REG_QVOQIDX_116 0x16e4dc
2815#define QM_REG_QVOQIDX_117 0x16e4e0
2816#define QM_REG_QVOQIDX_118 0x16e4e4
2817#define QM_REG_QVOQIDX_119 0x16e4e8
2818#define QM_REG_QVOQIDX_12 0x168124 2624#define QM_REG_QVOQIDX_12 0x168124
2819#define QM_REG_QVOQIDX_120 0x16e4ec 2625#define QM_REG_QVOQIDX_120 0x16e4ec
2820#define QM_REG_QVOQIDX_121 0x16e4f0 2626#define QM_REG_QVOQIDX_121 0x16e4f0
@@ -2824,14 +2630,6 @@
2824#define QM_REG_QVOQIDX_125 0x16e500 2630#define QM_REG_QVOQIDX_125 0x16e500
2825#define QM_REG_QVOQIDX_126 0x16e504 2631#define QM_REG_QVOQIDX_126 0x16e504
2826#define QM_REG_QVOQIDX_127 0x16e508 2632#define QM_REG_QVOQIDX_127 0x16e508
2827#define QM_REG_QVOQIDX_120 0x16e4ec
2828#define QM_REG_QVOQIDX_121 0x16e4f0
2829#define QM_REG_QVOQIDX_122 0x16e4f4
2830#define QM_REG_QVOQIDX_123 0x16e4f8
2831#define QM_REG_QVOQIDX_124 0x16e4fc
2832#define QM_REG_QVOQIDX_125 0x16e500
2833#define QM_REG_QVOQIDX_126 0x16e504
2834#define QM_REG_QVOQIDX_127 0x16e508
2835#define QM_REG_QVOQIDX_13 0x168128 2633#define QM_REG_QVOQIDX_13 0x168128
2836#define QM_REG_QVOQIDX_14 0x16812c 2634#define QM_REG_QVOQIDX_14 0x16812c
2837#define QM_REG_QVOQIDX_15 0x168130 2635#define QM_REG_QVOQIDX_15 0x168130
@@ -2877,16 +2675,6 @@
2877#define QM_REG_QVOQIDX_57 0x1681d8 2675#define QM_REG_QVOQIDX_57 0x1681d8
2878#define QM_REG_QVOQIDX_58 0x1681dc 2676#define QM_REG_QVOQIDX_58 0x1681dc
2879#define QM_REG_QVOQIDX_59 0x1681e0 2677#define QM_REG_QVOQIDX_59 0x1681e0
2880#define QM_REG_QVOQIDX_50 0x1681bc
2881#define QM_REG_QVOQIDX_51 0x1681c0
2882#define QM_REG_QVOQIDX_52 0x1681c4
2883#define QM_REG_QVOQIDX_53 0x1681c8
2884#define QM_REG_QVOQIDX_54 0x1681cc
2885#define QM_REG_QVOQIDX_55 0x1681d0
2886#define QM_REG_QVOQIDX_56 0x1681d4
2887#define QM_REG_QVOQIDX_57 0x1681d8
2888#define QM_REG_QVOQIDX_58 0x1681dc
2889#define QM_REG_QVOQIDX_59 0x1681e0
2890#define QM_REG_QVOQIDX_6 0x16810c 2678#define QM_REG_QVOQIDX_6 0x16810c
2891#define QM_REG_QVOQIDX_60 0x1681e4 2679#define QM_REG_QVOQIDX_60 0x1681e4
2892#define QM_REG_QVOQIDX_61 0x1681e8 2680#define QM_REG_QVOQIDX_61 0x1681e8
@@ -2894,16 +2682,6 @@
2894#define QM_REG_QVOQIDX_63 0x1681f0 2682#define QM_REG_QVOQIDX_63 0x1681f0
2895#define QM_REG_QVOQIDX_64 0x16e40c 2683#define QM_REG_QVOQIDX_64 0x16e40c
2896#define QM_REG_QVOQIDX_65 0x16e410 2684#define QM_REG_QVOQIDX_65 0x16e410
2897#define QM_REG_QVOQIDX_66 0x16e414
2898#define QM_REG_QVOQIDX_67 0x16e418
2899#define QM_REG_QVOQIDX_68 0x16e41c
2900#define QM_REG_QVOQIDX_69 0x16e420
2901#define QM_REG_QVOQIDX_60 0x1681e4
2902#define QM_REG_QVOQIDX_61 0x1681e8
2903#define QM_REG_QVOQIDX_62 0x1681ec
2904#define QM_REG_QVOQIDX_63 0x1681f0
2905#define QM_REG_QVOQIDX_64 0x16e40c
2906#define QM_REG_QVOQIDX_65 0x16e410
2907#define QM_REG_QVOQIDX_69 0x16e420 2685#define QM_REG_QVOQIDX_69 0x16e420
2908#define QM_REG_QVOQIDX_7 0x168110 2686#define QM_REG_QVOQIDX_7 0x168110
2909#define QM_REG_QVOQIDX_70 0x16e424 2687#define QM_REG_QVOQIDX_70 0x16e424
@@ -2916,29 +2694,9 @@
2916#define QM_REG_QVOQIDX_77 0x16e440 2694#define QM_REG_QVOQIDX_77 0x16e440
2917#define QM_REG_QVOQIDX_78 0x16e444 2695#define QM_REG_QVOQIDX_78 0x16e444
2918#define QM_REG_QVOQIDX_79 0x16e448 2696#define QM_REG_QVOQIDX_79 0x16e448
2919#define QM_REG_QVOQIDX_70 0x16e424
2920#define QM_REG_QVOQIDX_71 0x16e428
2921#define QM_REG_QVOQIDX_72 0x16e42c
2922#define QM_REG_QVOQIDX_73 0x16e430
2923#define QM_REG_QVOQIDX_74 0x16e434
2924#define QM_REG_QVOQIDX_75 0x16e438
2925#define QM_REG_QVOQIDX_76 0x16e43c
2926#define QM_REG_QVOQIDX_77 0x16e440
2927#define QM_REG_QVOQIDX_78 0x16e444
2928#define QM_REG_QVOQIDX_79 0x16e448
2929#define QM_REG_QVOQIDX_8 0x168114 2697#define QM_REG_QVOQIDX_8 0x168114
2930#define QM_REG_QVOQIDX_80 0x16e44c 2698#define QM_REG_QVOQIDX_80 0x16e44c
2931#define QM_REG_QVOQIDX_81 0x16e450 2699#define QM_REG_QVOQIDX_81 0x16e450
2932#define QM_REG_QVOQIDX_82 0x16e454
2933#define QM_REG_QVOQIDX_83 0x16e458
2934#define QM_REG_QVOQIDX_84 0x16e45c
2935#define QM_REG_QVOQIDX_85 0x16e460
2936#define QM_REG_QVOQIDX_86 0x16e464
2937#define QM_REG_QVOQIDX_87 0x16e468
2938#define QM_REG_QVOQIDX_88 0x16e46c
2939#define QM_REG_QVOQIDX_89 0x16e470
2940#define QM_REG_QVOQIDX_80 0x16e44c
2941#define QM_REG_QVOQIDX_81 0x16e450
2942#define QM_REG_QVOQIDX_85 0x16e460 2700#define QM_REG_QVOQIDX_85 0x16e460
2943#define QM_REG_QVOQIDX_86 0x16e464 2701#define QM_REG_QVOQIDX_86 0x16e464
2944#define QM_REG_QVOQIDX_87 0x16e468 2702#define QM_REG_QVOQIDX_87 0x16e468
@@ -2955,23 +2713,11 @@
2955#define QM_REG_QVOQIDX_97 0x16e490 2713#define QM_REG_QVOQIDX_97 0x16e490
2956#define QM_REG_QVOQIDX_98 0x16e494 2714#define QM_REG_QVOQIDX_98 0x16e494
2957#define QM_REG_QVOQIDX_99 0x16e498 2715#define QM_REG_QVOQIDX_99 0x16e498
2958#define QM_REG_QVOQIDX_90 0x16e474
2959#define QM_REG_QVOQIDX_91 0x16e478
2960#define QM_REG_QVOQIDX_92 0x16e47c
2961#define QM_REG_QVOQIDX_93 0x16e480
2962#define QM_REG_QVOQIDX_94 0x16e484
2963#define QM_REG_QVOQIDX_95 0x16e488
2964#define QM_REG_QVOQIDX_96 0x16e48c
2965#define QM_REG_QVOQIDX_97 0x16e490
2966#define QM_REG_QVOQIDX_98 0x16e494
2967#define QM_REG_QVOQIDX_99 0x16e498
2968/* [RW 1] Initialization bit command */ 2716/* [RW 1] Initialization bit command */
2969#define QM_REG_SOFT_RESET 0x168428 2717#define QM_REG_SOFT_RESET 0x168428
2970/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 2718/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2971#define QM_REG_TASKCRDCOST_0 0x16809c 2719#define QM_REG_TASKCRDCOST_0 0x16809c
2972#define QM_REG_TASKCRDCOST_1 0x1680a0 2720#define QM_REG_TASKCRDCOST_1 0x1680a0
2973#define QM_REG_TASKCRDCOST_10 0x1680c4
2974#define QM_REG_TASKCRDCOST_11 0x1680c8
2975#define QM_REG_TASKCRDCOST_2 0x1680a4 2721#define QM_REG_TASKCRDCOST_2 0x1680a4
2976#define QM_REG_TASKCRDCOST_4 0x1680ac 2722#define QM_REG_TASKCRDCOST_4 0x1680ac
2977#define QM_REG_TASKCRDCOST_5 0x1680b0 2723#define QM_REG_TASKCRDCOST_5 0x1680b0
@@ -2984,24 +2730,18 @@
2984/* [R 16] The credit value for each VOQ */ 2730/* [R 16] The credit value for each VOQ */
2985#define QM_REG_VOQCREDIT_0 0x1682d0 2731#define QM_REG_VOQCREDIT_0 0x1682d0
2986#define QM_REG_VOQCREDIT_1 0x1682d4 2732#define QM_REG_VOQCREDIT_1 0x1682d4
2987#define QM_REG_VOQCREDIT_10 0x1682f8
2988#define QM_REG_VOQCREDIT_11 0x1682fc
2989#define QM_REG_VOQCREDIT_4 0x1682e0 2733#define QM_REG_VOQCREDIT_4 0x1682e0
2990/* [RW 16] The credit value that if above the QM is considered almost full */ 2734/* [RW 16] The credit value that if above the QM is considered almost full */
2991#define QM_REG_VOQCREDITAFULLTHR 0x168090 2735#define QM_REG_VOQCREDITAFULLTHR 0x168090
2992/* [RW 16] The init and maximum credit for each VoQ */ 2736/* [RW 16] The init and maximum credit for each VoQ */
2993#define QM_REG_VOQINITCREDIT_0 0x168060 2737#define QM_REG_VOQINITCREDIT_0 0x168060
2994#define QM_REG_VOQINITCREDIT_1 0x168064 2738#define QM_REG_VOQINITCREDIT_1 0x168064
2995#define QM_REG_VOQINITCREDIT_10 0x168088
2996#define QM_REG_VOQINITCREDIT_11 0x16808c
2997#define QM_REG_VOQINITCREDIT_2 0x168068 2739#define QM_REG_VOQINITCREDIT_2 0x168068
2998#define QM_REG_VOQINITCREDIT_4 0x168070 2740#define QM_REG_VOQINITCREDIT_4 0x168070
2999#define QM_REG_VOQINITCREDIT_5 0x168074 2741#define QM_REG_VOQINITCREDIT_5 0x168074
3000/* [RW 1] The port of which VOQ belongs */ 2742/* [RW 1] The port of which VOQ belongs */
3001#define QM_REG_VOQPORT_0 0x1682a0 2743#define QM_REG_VOQPORT_0 0x1682a0
3002#define QM_REG_VOQPORT_1 0x1682a4 2744#define QM_REG_VOQPORT_1 0x1682a4
3003#define QM_REG_VOQPORT_10 0x1682c8
3004#define QM_REG_VOQPORT_11 0x1682cc
3005#define QM_REG_VOQPORT_2 0x1682a8 2745#define QM_REG_VOQPORT_2 0x1682a8
3006/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2746/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3007#define QM_REG_VOQQMASK_0_LSB 0x168240 2747#define QM_REG_VOQQMASK_0_LSB 0x168240
@@ -3099,36 +2839,6 @@
3099#define QM_REG_WRRWEIGHTS_0 0x16880c 2839#define QM_REG_WRRWEIGHTS_0 0x16880c
3100#define QM_REG_WRRWEIGHTS_1 0x168810 2840#define QM_REG_WRRWEIGHTS_1 0x168810
3101#define QM_REG_WRRWEIGHTS_10 0x168814 2841#define QM_REG_WRRWEIGHTS_10 0x168814
3102#define QM_REG_WRRWEIGHTS_10_SIZE 1
3103/* [RW 32] Wrr weights */
3104#define QM_REG_WRRWEIGHTS_11 0x168818
3105#define QM_REG_WRRWEIGHTS_11_SIZE 1
3106/* [RW 32] Wrr weights */
3107#define QM_REG_WRRWEIGHTS_12 0x16881c
3108#define QM_REG_WRRWEIGHTS_12_SIZE 1
3109/* [RW 32] Wrr weights */
3110#define QM_REG_WRRWEIGHTS_13 0x168820
3111#define QM_REG_WRRWEIGHTS_13_SIZE 1
3112/* [RW 32] Wrr weights */
3113#define QM_REG_WRRWEIGHTS_14 0x168824
3114#define QM_REG_WRRWEIGHTS_14_SIZE 1
3115/* [RW 32] Wrr weights */
3116#define QM_REG_WRRWEIGHTS_15 0x168828
3117#define QM_REG_WRRWEIGHTS_15_SIZE 1
3118/* [RW 32] Wrr weights */
3119#define QM_REG_WRRWEIGHTS_16 0x16e000
3120#define QM_REG_WRRWEIGHTS_16_SIZE 1
3121/* [RW 32] Wrr weights */
3122#define QM_REG_WRRWEIGHTS_17 0x16e004
3123#define QM_REG_WRRWEIGHTS_17_SIZE 1
3124/* [RW 32] Wrr weights */
3125#define QM_REG_WRRWEIGHTS_18 0x16e008
3126#define QM_REG_WRRWEIGHTS_18_SIZE 1
3127/* [RW 32] Wrr weights */
3128#define QM_REG_WRRWEIGHTS_19 0x16e00c
3129#define QM_REG_WRRWEIGHTS_19_SIZE 1
3130/* [RW 32] Wrr weights */
3131#define QM_REG_WRRWEIGHTS_10 0x168814
3132#define QM_REG_WRRWEIGHTS_11 0x168818 2842#define QM_REG_WRRWEIGHTS_11 0x168818
3133#define QM_REG_WRRWEIGHTS_12 0x16881c 2843#define QM_REG_WRRWEIGHTS_12 0x16881c
3134#define QM_REG_WRRWEIGHTS_13 0x168820 2844#define QM_REG_WRRWEIGHTS_13 0x168820
@@ -3140,36 +2850,6 @@
3140#define QM_REG_WRRWEIGHTS_19 0x16e00c 2850#define QM_REG_WRRWEIGHTS_19 0x16e00c
3141#define QM_REG_WRRWEIGHTS_2 0x16882c 2851#define QM_REG_WRRWEIGHTS_2 0x16882c
3142#define QM_REG_WRRWEIGHTS_20 0x16e010 2852#define QM_REG_WRRWEIGHTS_20 0x16e010
3143#define QM_REG_WRRWEIGHTS_20_SIZE 1
3144/* [RW 32] Wrr weights */
3145#define QM_REG_WRRWEIGHTS_21 0x16e014
3146#define QM_REG_WRRWEIGHTS_21_SIZE 1
3147/* [RW 32] Wrr weights */
3148#define QM_REG_WRRWEIGHTS_22 0x16e018
3149#define QM_REG_WRRWEIGHTS_22_SIZE 1
3150/* [RW 32] Wrr weights */
3151#define QM_REG_WRRWEIGHTS_23 0x16e01c
3152#define QM_REG_WRRWEIGHTS_23_SIZE 1
3153/* [RW 32] Wrr weights */
3154#define QM_REG_WRRWEIGHTS_24 0x16e020
3155#define QM_REG_WRRWEIGHTS_24_SIZE 1
3156/* [RW 32] Wrr weights */
3157#define QM_REG_WRRWEIGHTS_25 0x16e024
3158#define QM_REG_WRRWEIGHTS_25_SIZE 1
3159/* [RW 32] Wrr weights */
3160#define QM_REG_WRRWEIGHTS_26 0x16e028
3161#define QM_REG_WRRWEIGHTS_26_SIZE 1
3162/* [RW 32] Wrr weights */
3163#define QM_REG_WRRWEIGHTS_27 0x16e02c
3164#define QM_REG_WRRWEIGHTS_27_SIZE 1
3165/* [RW 32] Wrr weights */
3166#define QM_REG_WRRWEIGHTS_28 0x16e030
3167#define QM_REG_WRRWEIGHTS_28_SIZE 1
3168/* [RW 32] Wrr weights */
3169#define QM_REG_WRRWEIGHTS_29 0x16e034
3170#define QM_REG_WRRWEIGHTS_29_SIZE 1
3171/* [RW 32] Wrr weights */
3172#define QM_REG_WRRWEIGHTS_20 0x16e010
3173#define QM_REG_WRRWEIGHTS_21 0x16e014 2853#define QM_REG_WRRWEIGHTS_21 0x16e014
3174#define QM_REG_WRRWEIGHTS_22 0x16e018 2854#define QM_REG_WRRWEIGHTS_22 0x16e018
3175#define QM_REG_WRRWEIGHTS_23 0x16e01c 2855#define QM_REG_WRRWEIGHTS_23 0x16e01c
@@ -3181,12 +2861,6 @@
3181#define QM_REG_WRRWEIGHTS_29 0x16e034 2861#define QM_REG_WRRWEIGHTS_29 0x16e034
3182#define QM_REG_WRRWEIGHTS_3 0x168830 2862#define QM_REG_WRRWEIGHTS_3 0x168830
3183#define QM_REG_WRRWEIGHTS_30 0x16e038 2863#define QM_REG_WRRWEIGHTS_30 0x16e038
3184#define QM_REG_WRRWEIGHTS_30_SIZE 1
3185/* [RW 32] Wrr weights */
3186#define QM_REG_WRRWEIGHTS_31 0x16e03c
3187#define QM_REG_WRRWEIGHTS_31_SIZE 1
3188/* [RW 32] Wrr weights */
3189#define QM_REG_WRRWEIGHTS_30 0x16e038
3190#define QM_REG_WRRWEIGHTS_31 0x16e03c 2864#define QM_REG_WRRWEIGHTS_31 0x16e03c
3191#define QM_REG_WRRWEIGHTS_4 0x168834 2865#define QM_REG_WRRWEIGHTS_4 0x168834
3192#define QM_REG_WRRWEIGHTS_5 0x168838 2866#define QM_REG_WRRWEIGHTS_5 0x168838
@@ -3196,362 +2870,6 @@
3196#define QM_REG_WRRWEIGHTS_9 0x168848 2870#define QM_REG_WRRWEIGHTS_9 0x168848
3197/* [R 6] Keep the fill level of the fifo from write client 1 */ 2871/* [R 6] Keep the fill level of the fifo from write client 1 */
3198#define QM_REG_XQM_WRC_FIFOLVL 0x168000 2872#define QM_REG_XQM_WRC_FIFOLVL 0x168000
3199#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3200#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3201#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3202#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3203#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3204#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3205#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3206#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3207#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3208#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3209#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3210#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3211#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3212#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3213#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3214#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3215#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3216#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3217#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3218#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3219#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3220#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3221#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3222#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3223#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3224#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3225#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3226#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3227#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3228#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3229#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3230#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3231#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3232#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3233#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3234#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3235#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3236#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3237#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3238#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3239#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3240#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3241#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3242#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3243#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3244#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3245#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3246#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3247#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3248#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3249#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3250#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3251#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3252#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3253#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3254#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3255#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3256#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3257#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3258#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3259#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3260#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3261#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3262#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3263#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3264#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3265#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3266#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3267#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3268#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3269#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3270#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3271#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3272#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3273#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3274#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3275#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3276#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3277#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3278#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3279#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3280#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3281#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3282#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3283#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3284#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3285#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3286#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3287#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3288#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3289#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3290#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3291#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3292#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3293#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3294#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3295#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3296#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3297#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3298#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3299#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3300#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3301#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3302#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3303#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3304#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3305#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3306#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3307#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3308#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3309#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3310#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3311#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3312#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3313#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3314#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3315#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3316#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3317#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3318#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3319#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3320#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3321#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3322#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3323#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3324#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3325#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3326#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3327#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3328#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3329#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3330#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3331#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3332#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3333#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3334#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3335#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3336#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3337#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3338#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3339#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3340#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3341#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3342#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3343#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3344#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3345#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3346#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3347#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3348#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3349#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3350#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3351#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3352#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3353#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3354#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3355#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3356#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3357#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3358#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3359#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3360#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3361#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3362#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3363#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3364#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3365#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3366#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3367#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3368#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3369#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3370#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3371#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3372#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3373#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3374#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3375#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3376#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3377#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3378#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3379#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3380#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3381#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3382#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3383#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3384#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3385#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3386#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3387#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3388#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3389#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3390#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3391#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3392#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3393#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3394#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3395#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3396#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3397#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3398#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3399#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3400#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3401#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3402#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3403#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3404#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3405#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3406#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3407#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3408#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3409#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3410#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3411#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3412#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3413#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3414#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3415#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3416#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3417#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3418#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3419#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3420#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3421#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3422#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3423#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3424#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3425#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3426#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3427#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3428#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3429#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3430#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3431#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3432#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3433#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3434#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3435#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3436#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3437#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3438#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3439#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3440#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3441/* [R 1] debug only: This bit indicates whether indicates that external
3442 buffer was wrapped (oldest data was thrown); Relevant only when
3443 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3444#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3445#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3446/* [R 1] debug only: This bit indicates whether the internal buffer was
3447 wrapped (oldest data was thrown) Relevant only when
3448 ~dbg_registers_debug_target=0 (internal buffer) */
3449#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3450#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3451#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3452#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3453#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3454#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3455#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3456#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3457#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3458#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
3459/* [RW 32] Wrr weights */
3460#define QM_REG_WRRWEIGHTS_0 0x16880c
3461#define QM_REG_WRRWEIGHTS_0_SIZE 1
3462/* [RW 32] Wrr weights */
3463#define QM_REG_WRRWEIGHTS_1 0x168810
3464#define QM_REG_WRRWEIGHTS_1_SIZE 1
3465/* [RW 32] Wrr weights */
3466#define QM_REG_WRRWEIGHTS_10 0x168814
3467#define QM_REG_WRRWEIGHTS_10_SIZE 1
3468/* [RW 32] Wrr weights */
3469#define QM_REG_WRRWEIGHTS_11 0x168818
3470#define QM_REG_WRRWEIGHTS_11_SIZE 1
3471/* [RW 32] Wrr weights */
3472#define QM_REG_WRRWEIGHTS_12 0x16881c
3473#define QM_REG_WRRWEIGHTS_12_SIZE 1
3474/* [RW 32] Wrr weights */
3475#define QM_REG_WRRWEIGHTS_13 0x168820
3476#define QM_REG_WRRWEIGHTS_13_SIZE 1
3477/* [RW 32] Wrr weights */
3478#define QM_REG_WRRWEIGHTS_14 0x168824
3479#define QM_REG_WRRWEIGHTS_14_SIZE 1
3480/* [RW 32] Wrr weights */
3481#define QM_REG_WRRWEIGHTS_15 0x168828
3482#define QM_REG_WRRWEIGHTS_15_SIZE 1
3483/* [RW 32] Wrr weights */
3484#define QM_REG_WRRWEIGHTS_2 0x16882c
3485#define QM_REG_WRRWEIGHTS_2_SIZE 1
3486/* [RW 32] Wrr weights */
3487#define QM_REG_WRRWEIGHTS_3 0x168830
3488#define QM_REG_WRRWEIGHTS_3_SIZE 1
3489/* [RW 32] Wrr weights */
3490#define QM_REG_WRRWEIGHTS_4 0x168834
3491#define QM_REG_WRRWEIGHTS_4_SIZE 1
3492/* [RW 32] Wrr weights */
3493#define QM_REG_WRRWEIGHTS_5 0x168838
3494#define QM_REG_WRRWEIGHTS_5_SIZE 1
3495/* [RW 32] Wrr weights */
3496#define QM_REG_WRRWEIGHTS_6 0x16883c
3497#define QM_REG_WRRWEIGHTS_6_SIZE 1
3498/* [RW 32] Wrr weights */
3499#define QM_REG_WRRWEIGHTS_7 0x168840
3500#define QM_REG_WRRWEIGHTS_7_SIZE 1
3501/* [RW 32] Wrr weights */
3502#define QM_REG_WRRWEIGHTS_8 0x168844
3503#define QM_REG_WRRWEIGHTS_8_SIZE 1
3504/* [RW 32] Wrr weights */
3505#define QM_REG_WRRWEIGHTS_9 0x168848
3506#define QM_REG_WRRWEIGHTS_9_SIZE 1
3507/* [RW 32] Wrr weights */
3508#define QM_REG_WRRWEIGHTS_16 0x16e000
3509#define QM_REG_WRRWEIGHTS_16_SIZE 1
3510/* [RW 32] Wrr weights */
3511#define QM_REG_WRRWEIGHTS_17 0x16e004
3512#define QM_REG_WRRWEIGHTS_17_SIZE 1
3513/* [RW 32] Wrr weights */
3514#define QM_REG_WRRWEIGHTS_18 0x16e008
3515#define QM_REG_WRRWEIGHTS_18_SIZE 1
3516/* [RW 32] Wrr weights */
3517#define QM_REG_WRRWEIGHTS_19 0x16e00c
3518#define QM_REG_WRRWEIGHTS_19_SIZE 1
3519/* [RW 32] Wrr weights */
3520#define QM_REG_WRRWEIGHTS_20 0x16e010
3521#define QM_REG_WRRWEIGHTS_20_SIZE 1
3522/* [RW 32] Wrr weights */
3523#define QM_REG_WRRWEIGHTS_21 0x16e014
3524#define QM_REG_WRRWEIGHTS_21_SIZE 1
3525/* [RW 32] Wrr weights */
3526#define QM_REG_WRRWEIGHTS_22 0x16e018
3527#define QM_REG_WRRWEIGHTS_22_SIZE 1
3528/* [RW 32] Wrr weights */
3529#define QM_REG_WRRWEIGHTS_23 0x16e01c
3530#define QM_REG_WRRWEIGHTS_23_SIZE 1
3531/* [RW 32] Wrr weights */
3532#define QM_REG_WRRWEIGHTS_24 0x16e020
3533#define QM_REG_WRRWEIGHTS_24_SIZE 1
3534/* [RW 32] Wrr weights */
3535#define QM_REG_WRRWEIGHTS_25 0x16e024
3536#define QM_REG_WRRWEIGHTS_25_SIZE 1
3537/* [RW 32] Wrr weights */
3538#define QM_REG_WRRWEIGHTS_26 0x16e028
3539#define QM_REG_WRRWEIGHTS_26_SIZE 1
3540/* [RW 32] Wrr weights */
3541#define QM_REG_WRRWEIGHTS_27 0x16e02c
3542#define QM_REG_WRRWEIGHTS_27_SIZE 1
3543/* [RW 32] Wrr weights */
3544#define QM_REG_WRRWEIGHTS_28 0x16e030
3545#define QM_REG_WRRWEIGHTS_28_SIZE 1
3546/* [RW 32] Wrr weights */
3547#define QM_REG_WRRWEIGHTS_29 0x16e034
3548#define QM_REG_WRRWEIGHTS_29_SIZE 1
3549/* [RW 32] Wrr weights */
3550#define QM_REG_WRRWEIGHTS_30 0x16e038
3551#define QM_REG_WRRWEIGHTS_30_SIZE 1
3552/* [RW 32] Wrr weights */
3553#define QM_REG_WRRWEIGHTS_31 0x16e03c
3554#define QM_REG_WRRWEIGHTS_31_SIZE 1
3555#define SRC_REG_COUNTFREE0 0x40500 2873#define SRC_REG_COUNTFREE0 0x40500
3556/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 2874/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3557 ports. If set the searcher support 8 functions. */ 2875 ports. If set the searcher support 8 functions. */
@@ -3651,12 +2969,6 @@
3651 type (one of 16). */ 2969 type (one of 16). */
3652#define TCM_REG_N_SM_CTX_LD_0 0x50050 2970#define TCM_REG_N_SM_CTX_LD_0 0x50050
3653#define TCM_REG_N_SM_CTX_LD_1 0x50054 2971#define TCM_REG_N_SM_CTX_LD_1 0x50054
3654#define TCM_REG_N_SM_CTX_LD_10 0x50078
3655#define TCM_REG_N_SM_CTX_LD_11 0x5007c
3656#define TCM_REG_N_SM_CTX_LD_12 0x50080
3657#define TCM_REG_N_SM_CTX_LD_13 0x50084
3658#define TCM_REG_N_SM_CTX_LD_14 0x50088
3659#define TCM_REG_N_SM_CTX_LD_15 0x5008c
3660#define TCM_REG_N_SM_CTX_LD_2 0x50058 2972#define TCM_REG_N_SM_CTX_LD_2 0x50058
3661#define TCM_REG_N_SM_CTX_LD_3 0x5005c 2973#define TCM_REG_N_SM_CTX_LD_3 0x5005c
3662#define TCM_REG_N_SM_CTX_LD_4 0x50060 2974#define TCM_REG_N_SM_CTX_LD_4 0x50060
@@ -3863,8 +3175,6 @@
3863#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 3175#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3864/* [RW 2] Load value for pci arbiter credit cnt. */ 3176/* [RW 2] Load value for pci arbiter credit cnt. */
3865#define TM_REG_PCIARB_CRDCNT_VAL 0x164260 3177#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3866/* [RW 1] Timer software reset - active high. */
3867#define TM_REG_TIMER_SOFT_RST 0x164004
3868/* [RW 20] The amount of hardware cycles for each timer tick. */ 3178/* [RW 20] The amount of hardware cycles for each timer tick. */
3869#define TM_REG_TIMER_TICK_SIZE 0x16401c 3179#define TM_REG_TIMER_TICK_SIZE 0x16401c
3870/* [RW 8] Timers Context region. */ 3180/* [RW 8] Timers Context region. */
@@ -3876,44 +3186,12 @@
3876/* [RW 8] The event id for aggregated interrupt 0 */ 3186/* [RW 8] The event id for aggregated interrupt 0 */
3877#define TSDM_REG_AGG_INT_EVENT_0 0x42038 3187#define TSDM_REG_AGG_INT_EVENT_0 0x42038
3878#define TSDM_REG_AGG_INT_EVENT_1 0x4203c 3188#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3879#define TSDM_REG_AGG_INT_EVENT_10 0x42060
3880#define TSDM_REG_AGG_INT_EVENT_11 0x42064
3881#define TSDM_REG_AGG_INT_EVENT_12 0x42068
3882#define TSDM_REG_AGG_INT_EVENT_13 0x4206c
3883#define TSDM_REG_AGG_INT_EVENT_14 0x42070
3884#define TSDM_REG_AGG_INT_EVENT_15 0x42074
3885#define TSDM_REG_AGG_INT_EVENT_16 0x42078
3886#define TSDM_REG_AGG_INT_EVENT_17 0x4207c
3887#define TSDM_REG_AGG_INT_EVENT_18 0x42080
3888#define TSDM_REG_AGG_INT_EVENT_19 0x42084
3889#define TSDM_REG_AGG_INT_EVENT_2 0x42040 3189#define TSDM_REG_AGG_INT_EVENT_2 0x42040
3890#define TSDM_REG_AGG_INT_EVENT_20 0x42088
3891#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3892#define TSDM_REG_AGG_INT_EVENT_22 0x42090
3893#define TSDM_REG_AGG_INT_EVENT_23 0x42094
3894#define TSDM_REG_AGG_INT_EVENT_24 0x42098
3895#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3896#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3897#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3898#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3899#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3900#define TSDM_REG_AGG_INT_EVENT_3 0x42044 3190#define TSDM_REG_AGG_INT_EVENT_3 0x42044
3901#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3902#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3903#define TSDM_REG_AGG_INT_EVENT_4 0x42048 3191#define TSDM_REG_AGG_INT_EVENT_4 0x42048
3904/* [RW 1] The T bit for aggregated interrupt 0 */ 3192/* [RW 1] The T bit for aggregated interrupt 0 */
3905#define TSDM_REG_AGG_INT_T_0 0x420b8 3193#define TSDM_REG_AGG_INT_T_0 0x420b8
3906#define TSDM_REG_AGG_INT_T_1 0x420bc 3194#define TSDM_REG_AGG_INT_T_1 0x420bc
3907#define TSDM_REG_AGG_INT_T_10 0x420e0
3908#define TSDM_REG_AGG_INT_T_11 0x420e4
3909#define TSDM_REG_AGG_INT_T_12 0x420e8
3910#define TSDM_REG_AGG_INT_T_13 0x420ec
3911#define TSDM_REG_AGG_INT_T_14 0x420f0
3912#define TSDM_REG_AGG_INT_T_15 0x420f4
3913#define TSDM_REG_AGG_INT_T_16 0x420f8
3914#define TSDM_REG_AGG_INT_T_17 0x420fc
3915#define TSDM_REG_AGG_INT_T_18 0x42100
3916#define TSDM_REG_AGG_INT_T_19 0x42104
3917/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 3195/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3918#define TSDM_REG_CFC_RSP_START_ADDR 0x42008 3196#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3919/* [RW 16] The maximum value of the competion counter #0 */ 3197/* [RW 16] The maximum value of the competion counter #0 */
@@ -4198,12 +3476,6 @@
4198 connection type (one of 16). */ 3476 connection type (one of 16). */
4199#define UCM_REG_N_SM_CTX_LD_0 0xe0054 3477#define UCM_REG_N_SM_CTX_LD_0 0xe0054
4200#define UCM_REG_N_SM_CTX_LD_1 0xe0058 3478#define UCM_REG_N_SM_CTX_LD_1 0xe0058
4201#define UCM_REG_N_SM_CTX_LD_10 0xe007c
4202#define UCM_REG_N_SM_CTX_LD_11 0xe0080
4203#define UCM_REG_N_SM_CTX_LD_12 0xe0084
4204#define UCM_REG_N_SM_CTX_LD_13 0xe0088
4205#define UCM_REG_N_SM_CTX_LD_14 0xe008c
4206#define UCM_REG_N_SM_CTX_LD_15 0xe0090
4207#define UCM_REG_N_SM_CTX_LD_2 0xe005c 3479#define UCM_REG_N_SM_CTX_LD_2 0xe005c
4208#define UCM_REG_N_SM_CTX_LD_3 0xe0060 3480#define UCM_REG_N_SM_CTX_LD_3 0xe0060
4209#define UCM_REG_N_SM_CTX_LD_4 0xe0064 3481#define UCM_REG_N_SM_CTX_LD_4 0xe0064
@@ -4353,30 +3625,7 @@
4353/* [RW 8] The event id for aggregated interrupt 0 */ 3625/* [RW 8] The event id for aggregated interrupt 0 */
4354#define USDM_REG_AGG_INT_EVENT_0 0xc4038 3626#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4355#define USDM_REG_AGG_INT_EVENT_1 0xc403c 3627#define USDM_REG_AGG_INT_EVENT_1 0xc403c
4356#define USDM_REG_AGG_INT_EVENT_10 0xc4060
4357#define USDM_REG_AGG_INT_EVENT_11 0xc4064
4358#define USDM_REG_AGG_INT_EVENT_12 0xc4068
4359#define USDM_REG_AGG_INT_EVENT_13 0xc406c
4360#define USDM_REG_AGG_INT_EVENT_14 0xc4070
4361#define USDM_REG_AGG_INT_EVENT_15 0xc4074
4362#define USDM_REG_AGG_INT_EVENT_16 0xc4078
4363#define USDM_REG_AGG_INT_EVENT_17 0xc407c
4364#define USDM_REG_AGG_INT_EVENT_18 0xc4080
4365#define USDM_REG_AGG_INT_EVENT_19 0xc4084
4366#define USDM_REG_AGG_INT_EVENT_2 0xc4040 3628#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4367#define USDM_REG_AGG_INT_EVENT_20 0xc4088
4368#define USDM_REG_AGG_INT_EVENT_21 0xc408c
4369#define USDM_REG_AGG_INT_EVENT_22 0xc4090
4370#define USDM_REG_AGG_INT_EVENT_23 0xc4094
4371#define USDM_REG_AGG_INT_EVENT_24 0xc4098
4372#define USDM_REG_AGG_INT_EVENT_25 0xc409c
4373#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4374#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4375#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4376#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4377#define USDM_REG_AGG_INT_EVENT_3 0xc4044
4378#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4379#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4380#define USDM_REG_AGG_INT_EVENT_4 0xc4048 3629#define USDM_REG_AGG_INT_EVENT_4 0xc4048
4381#define USDM_REG_AGG_INT_EVENT_5 0xc404c 3630#define USDM_REG_AGG_INT_EVENT_5 0xc404c
4382#define USDM_REG_AGG_INT_EVENT_6 0xc4050 3631#define USDM_REG_AGG_INT_EVENT_6 0xc4050
@@ -4384,16 +3633,6 @@
4384 or auto-mask-mode (1) */ 3633 or auto-mask-mode (1) */
4385#define USDM_REG_AGG_INT_MODE_0 0xc41b8 3634#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4386#define USDM_REG_AGG_INT_MODE_1 0xc41bc 3635#define USDM_REG_AGG_INT_MODE_1 0xc41bc
4387#define USDM_REG_AGG_INT_MODE_10 0xc41e0
4388#define USDM_REG_AGG_INT_MODE_11 0xc41e4
4389#define USDM_REG_AGG_INT_MODE_12 0xc41e8
4390#define USDM_REG_AGG_INT_MODE_13 0xc41ec
4391#define USDM_REG_AGG_INT_MODE_14 0xc41f0
4392#define USDM_REG_AGG_INT_MODE_15 0xc41f4
4393#define USDM_REG_AGG_INT_MODE_16 0xc41f8
4394#define USDM_REG_AGG_INT_MODE_17 0xc41fc
4395#define USDM_REG_AGG_INT_MODE_18 0xc4200
4396#define USDM_REG_AGG_INT_MODE_19 0xc4204
4397#define USDM_REG_AGG_INT_MODE_4 0xc41c8 3636#define USDM_REG_AGG_INT_MODE_4 0xc41c8
4398#define USDM_REG_AGG_INT_MODE_5 0xc41cc 3637#define USDM_REG_AGG_INT_MODE_5 0xc41cc
4399#define USDM_REG_AGG_INT_MODE_6 0xc41d0 3638#define USDM_REG_AGG_INT_MODE_6 0xc41d0
@@ -4703,10 +3942,6 @@
4703/* [RC 1] Set at message length mismatch (relative to last indication) at 3942/* [RC 1] Set at message length mismatch (relative to last indication) at
4704 the nig1 interface. */ 3943 the nig1 interface. */
4705#define XCM_REG_NIG1_LENGTH_MIS 0x2023c 3944#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4706/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4707 weight 8 (the most prioritised); 1 stands for weight 1(least
4708 prioritised); 2 stands for weight 2; tc. */
4709#define XCM_REG_NIG1_WEIGHT 0x200d8
4710/* [RW 5] The number of double REG-pairs; loaded from the STORM context and 3945/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4711 sent to STORM; for a specific connection type. The double REG-pairs are 3946 sent to STORM; for a specific connection type. The double REG-pairs are
4712 used in order to align to STORM context row size of 128 bits. The offset 3947 used in order to align to STORM context row size of 128 bits. The offset
@@ -4714,12 +3949,6 @@
4714 connection type (one of 16). */ 3949 connection type (one of 16). */
4715#define XCM_REG_N_SM_CTX_LD_0 0x20060 3950#define XCM_REG_N_SM_CTX_LD_0 0x20060
4716#define XCM_REG_N_SM_CTX_LD_1 0x20064 3951#define XCM_REG_N_SM_CTX_LD_1 0x20064
4717#define XCM_REG_N_SM_CTX_LD_10 0x20088
4718#define XCM_REG_N_SM_CTX_LD_11 0x2008c
4719#define XCM_REG_N_SM_CTX_LD_12 0x20090
4720#define XCM_REG_N_SM_CTX_LD_13 0x20094
4721#define XCM_REG_N_SM_CTX_LD_14 0x20098
4722#define XCM_REG_N_SM_CTX_LD_15 0x2009c
4723#define XCM_REG_N_SM_CTX_LD_2 0x20068 3952#define XCM_REG_N_SM_CTX_LD_2 0x20068
4724#define XCM_REG_N_SM_CTX_LD_3 0x2006c 3953#define XCM_REG_N_SM_CTX_LD_3 0x2006c
4725#define XCM_REG_N_SM_CTX_LD_4 0x20070 3954#define XCM_REG_N_SM_CTX_LD_4 0x20070
@@ -4896,30 +4125,8 @@
4896#define XSDM_REG_AGG_INT_EVENT_12 0x166068 4125#define XSDM_REG_AGG_INT_EVENT_12 0x166068
4897#define XSDM_REG_AGG_INT_EVENT_13 0x16606c 4126#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4898#define XSDM_REG_AGG_INT_EVENT_14 0x166070 4127#define XSDM_REG_AGG_INT_EVENT_14 0x166070
4899#define XSDM_REG_AGG_INT_EVENT_15 0x166074
4900#define XSDM_REG_AGG_INT_EVENT_16 0x166078
4901#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4902#define XSDM_REG_AGG_INT_EVENT_18 0x166080
4903#define XSDM_REG_AGG_INT_EVENT_19 0x166084
4904#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4905#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4906#define XSDM_REG_AGG_INT_EVENT_12 0x166068
4907#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4908#define XSDM_REG_AGG_INT_EVENT_14 0x166070
4909#define XSDM_REG_AGG_INT_EVENT_2 0x166040 4128#define XSDM_REG_AGG_INT_EVENT_2 0x166040
4910#define XSDM_REG_AGG_INT_EVENT_20 0x166088
4911#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4912#define XSDM_REG_AGG_INT_EVENT_22 0x166090
4913#define XSDM_REG_AGG_INT_EVENT_23 0x166094
4914#define XSDM_REG_AGG_INT_EVENT_24 0x166098
4915#define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4916#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4917#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4918#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4919#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4920#define XSDM_REG_AGG_INT_EVENT_3 0x166044 4129#define XSDM_REG_AGG_INT_EVENT_3 0x166044
4921#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4922#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4923#define XSDM_REG_AGG_INT_EVENT_4 0x166048 4130#define XSDM_REG_AGG_INT_EVENT_4 0x166048
4924#define XSDM_REG_AGG_INT_EVENT_5 0x16604c 4131#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4925#define XSDM_REG_AGG_INT_EVENT_6 0x166050 4132#define XSDM_REG_AGG_INT_EVENT_6 0x166050
@@ -4930,16 +4137,6 @@
4930 or auto-mask-mode (1) */ 4137 or auto-mask-mode (1) */
4931#define XSDM_REG_AGG_INT_MODE_0 0x1661b8 4138#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4932#define XSDM_REG_AGG_INT_MODE_1 0x1661bc 4139#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4933#define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4934#define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4935#define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4936#define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4937#define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4938#define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4939#define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4940#define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4941#define XSDM_REG_AGG_INT_MODE_18 0x166200
4942#define XSDM_REG_AGG_INT_MODE_19 0x166204
4943/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4140/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4944#define XSDM_REG_CFC_RSP_START_ADDR 0x166008 4141#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4945/* [RW 16] The maximum value of the competion counter #0 */ 4142/* [RW 16] The maximum value of the competion counter #0 */
@@ -5147,10 +4344,6 @@
5147#define MCPR_NVM_COMMAND_FIRST (1L<<7) 4344#define MCPR_NVM_COMMAND_FIRST (1L<<7)
5148#define MCPR_NVM_COMMAND_LAST (1L<<8) 4345#define MCPR_NVM_COMMAND_LAST (1L<<8)
5149#define MCPR_NVM_COMMAND_WR (1L<<5) 4346#define MCPR_NVM_COMMAND_WR (1L<<5)
5150#define MCPR_NVM_COMMAND_WREN (1L<<16)
5151#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
5152#define MCPR_NVM_COMMAND_WRDI (1L<<17)
5153#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
5154#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 4347#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5155#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 4348#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5156#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 4349#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
@@ -5251,10 +4444,6 @@
5251#define MISC_REGISTERS_SPIO_7 7 4444#define MISC_REGISTERS_SPIO_7 7
5252#define MISC_REGISTERS_SPIO_CLR_POS 16 4445#define MISC_REGISTERS_SPIO_CLR_POS 16
5253#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 4446#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5254#define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
5255#define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
5256#define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
5257#define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
5258#define MISC_REGISTERS_SPIO_FLOAT_POS 24 4447#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5259#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 4448#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5260#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 4449#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 09:04:15 -0500