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authorAlexander Duyck <alexander.h.duyck@intel.com>2011-08-26 03:43:48 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-09-20 02:58:04 -0400
commit238ac817fd23f7dd5f61a8c51b4678f8d199db57 (patch)
tree0e7a1096c71de92fdc736a5cfd5785e9ce88822a /drivers
parentc023cd8898dbee857c8e82b357b4e68dc2d9561d (diff)
igb: update ring and adapter structure to improve performance
This change is meant to improve performance by splitting the Tx and Rx rings into 3 sections. The first is primarily a read only section containing basic things like the indexes, a pointer to the dev and netdev structures, and basic information. The second section contains the stats and next_to_use and next_to_clean values. The third section is primarily unused values that can just be placed at the end of the ring and are not used in the hot path. The adapter structure has several sections that are read in the hot path. In order to improve performance there I am combining the frequent read hot path items into a single cache line. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/intel/igb/igb.h83
-rw-r--r--drivers/net/ethernet/intel/igb/igb_main.c4
2 files changed, 46 insertions, 41 deletions
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h
index b2f2a8ca46e2..7036fd5aa34c 100644
--- a/drivers/net/ethernet/intel/igb/igb.h
+++ b/drivers/net/ethernet/intel/igb/igb.h
@@ -187,26 +187,26 @@ struct igb_q_vector {
187}; 187};
188 188
189struct igb_ring { 189struct igb_ring {
190 struct igb_q_vector *q_vector; /* backlink to q_vector */ 190 struct igb_q_vector *q_vector; /* backlink to q_vector */
191 struct net_device *netdev; /* back pointer to net_device */ 191 struct net_device *netdev; /* back pointer to net_device */
192 struct device *dev; /* device pointer for dma mapping */ 192 struct device *dev; /* device pointer for dma mapping */
193 dma_addr_t dma; /* phys address of the ring */ 193 struct igb_buffer *buffer_info; /* array of buffer info structs */
194 void *desc; /* descriptor ring memory */ 194 void *desc; /* descriptor ring memory */
195 unsigned int size; /* length of desc. ring in bytes */ 195 unsigned long flags; /* ring specific flags */
196 u16 count; /* number of desc. in the ring */ 196 void __iomem *tail; /* pointer to ring tail register */
197
198 u16 count; /* number of desc. in the ring */
199 u8 queue_index; /* logical index of the ring*/
200 u8 reg_idx; /* physical index of the ring */
201 u32 size; /* length of desc. ring in bytes */
202
203 /* everything past this point are written often */
204 u16 next_to_clean ____cacheline_aligned_in_smp;
197 u16 next_to_use; 205 u16 next_to_use;
198 u16 next_to_clean;
199 u8 queue_index;
200 u8 reg_idx;
201 void __iomem *head;
202 void __iomem *tail;
203 struct igb_buffer *buffer_info; /* array of buffer info structs */
204 206
205 unsigned int total_bytes; 207 unsigned int total_bytes;
206 unsigned int total_packets; 208 unsigned int total_packets;
207 209
208 u32 flags;
209
210 union { 210 union {
211 /* TX */ 211 /* TX */
212 struct { 212 struct {
@@ -221,6 +221,8 @@ struct igb_ring {
221 struct u64_stats_sync rx_syncp; 221 struct u64_stats_sync rx_syncp;
222 }; 222 };
223 }; 223 };
224 /* Items past this point are only used during ring alloc / free */
225 dma_addr_t dma; /* phys address of the ring */
224}; 226};
225 227
226#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ 228#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
@@ -248,15 +250,15 @@ static inline int igb_desc_unused(struct igb_ring *ring)
248 250
249/* board specific private data structure */ 251/* board specific private data structure */
250struct igb_adapter { 252struct igb_adapter {
251 struct timer_list watchdog_timer;
252 struct timer_list phy_info_timer;
253 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 253 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
254 u16 mng_vlan_id; 254
255 u32 bd_number; 255 struct net_device *netdev;
256 u32 wol; 256
257 u32 en_mng_pt; 257 unsigned long state;
258 u16 link_speed; 258 unsigned int flags;
259 u16 link_duplex; 259
260 unsigned int num_q_vectors;
261 struct msix_entry *msix_entries;
260 262
261 /* Interrupt Throttle Rate */ 263 /* Interrupt Throttle Rate */
262 u32 rx_itr_setting; 264 u32 rx_itr_setting;
@@ -264,27 +266,36 @@ struct igb_adapter {
264 u16 tx_itr; 266 u16 tx_itr;
265 u16 rx_itr; 267 u16 rx_itr;
266 268
267 struct work_struct reset_task;
268 struct work_struct watchdog_task;
269 bool fc_autoneg;
270 u8 tx_timeout_factor;
271 struct timer_list blink_timer;
272 unsigned long led_status;
273
274 /* TX */ 269 /* TX */
275 struct igb_ring *tx_ring[16];
276 u32 tx_timeout_count; 270 u32 tx_timeout_count;
271 int num_tx_queues;
272 struct igb_ring *tx_ring[16];
277 273
278 /* RX */ 274 /* RX */
279 struct igb_ring *rx_ring[16];
280 int num_tx_queues;
281 int num_rx_queues; 275 int num_rx_queues;
276 struct igb_ring *rx_ring[16];
282 277
283 u32 max_frame_size; 278 u32 max_frame_size;
284 u32 min_frame_size; 279 u32 min_frame_size;
285 280
281 struct timer_list watchdog_timer;
282 struct timer_list phy_info_timer;
283
284 u16 mng_vlan_id;
285 u32 bd_number;
286 u32 wol;
287 u32 en_mng_pt;
288 u16 link_speed;
289 u16 link_duplex;
290
291 struct work_struct reset_task;
292 struct work_struct watchdog_task;
293 bool fc_autoneg;
294 u8 tx_timeout_factor;
295 struct timer_list blink_timer;
296 unsigned long led_status;
297
286 /* OS defined structs */ 298 /* OS defined structs */
287 struct net_device *netdev;
288 struct pci_dev *pdev; 299 struct pci_dev *pdev;
289 struct cyclecounter cycles; 300 struct cyclecounter cycles;
290 struct timecounter clock; 301 struct timecounter clock;
@@ -306,15 +317,11 @@ struct igb_adapter {
306 317
307 int msg_enable; 318 int msg_enable;
308 319
309 unsigned int num_q_vectors;
310 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 320 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
311 struct msix_entry *msix_entries;
312 u32 eims_enable_mask; 321 u32 eims_enable_mask;
313 u32 eims_other; 322 u32 eims_other;
314 323
315 /* to not mess up cache alignment, always add to the bottom */ 324 /* to not mess up cache alignment, always add to the bottom */
316 unsigned long state;
317 unsigned int flags;
318 u32 eeprom_wol; 325 u32 eeprom_wol;
319 326
320 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES]; 327 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index af8c2f783a90..9fa2ad01c6b7 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -2679,7 +2679,6 @@ void igb_configure_tx_ring(struct igb_adapter *adapter,
2679 tdba & 0x00000000ffffffffULL); 2679 tdba & 0x00000000ffffffffULL);
2680 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2680 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2681 2681
2682 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2683 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2682 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2684 wr32(E1000_TDH(reg_idx), 0); 2683 wr32(E1000_TDH(reg_idx), 0);
2685 writel(0, ring->tail); 2684 writel(0, ring->tail);
@@ -3040,7 +3039,6 @@ void igb_configure_rx_ring(struct igb_adapter *adapter,
3040 ring->count * sizeof(union e1000_adv_rx_desc)); 3039 ring->count * sizeof(union e1000_adv_rx_desc));
3041 3040
3042 /* initialize head and tail */ 3041 /* initialize head and tail */
3043 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
3044 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3042 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3045 wr32(E1000_RDH(reg_idx), 0); 3043 wr32(E1000_RDH(reg_idx), 0);
3046 writel(0, ring->tail); 3044 writel(0, ring->tail);
@@ -5653,7 +5651,7 @@ static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5653 " jiffies <%lx>\n" 5651 " jiffies <%lx>\n"
5654 " desc.status <%x>\n", 5652 " desc.status <%x>\n",
5655 tx_ring->queue_index, 5653 tx_ring->queue_index,
5656 readl(tx_ring->head), 5654 rd32(E1000_TDH(tx_ring->reg_idx)),
5657 readl(tx_ring->tail), 5655 readl(tx_ring->tail),
5658 tx_ring->next_to_use, 5656 tx_ring->next_to_use,
5659 tx_ring->next_to_clean, 5657 tx_ring->next_to_clean,