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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-08-13 18:43:26 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2010-08-18 16:21:50 -0400
commitd240f20f545fa4ed78ce48d1eb62ab529f2b1467 (patch)
tree77f410b91940ae2e42cd2b328d538a71bdcbb991 /drivers
parent9cce37f4855a30cc7c364edf18522282782f7ddc (diff)
drm/i915: make sure eDP PLL is enabled at the right time
We need to make sure the eDP PLL is enabled before the pipes or planes, so do it as part of the DP prepare mode set function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c39
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c60
2 files changed, 60 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fbe42f0a315d..14c45b1e8778 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1622,32 +1622,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1622 return 0; 1622 return 0;
1623} 1623}
1624 1624
1625static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1626{
1627 struct drm_device *dev = crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 u32 dpa_ctl;
1630
1631 DRM_DEBUG_KMS("\n");
1632 dpa_ctl = I915_READ(DP_A);
1633 dpa_ctl &= ~DP_PLL_ENABLE;
1634 I915_WRITE(DP_A, dpa_ctl);
1635}
1636
1637static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1638{
1639 struct drm_device *dev = crtc->dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpa_ctl;
1642
1643 dpa_ctl = I915_READ(DP_A);
1644 dpa_ctl |= DP_PLL_ENABLE;
1645 I915_WRITE(DP_A, dpa_ctl);
1646 POSTING_READ(DP_A);
1647 udelay(200);
1648}
1649
1650
1651static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) 1625static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1652{ 1626{
1653 struct drm_device *dev = crtc->dev; 1627 struct drm_device *dev = crtc->dev;
@@ -1940,10 +1914,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1940 } 1914 }
1941 } 1915 }
1942 1916
1943 if (HAS_eDP) { 1917 if (!HAS_eDP) {
1944 /* enable eDP PLL */
1945 ironlake_enable_pll_edp(crtc);
1946 } else {
1947 1918
1948 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1919 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1949 temp = I915_READ(fdi_rx_reg); 1920 temp = I915_READ(fdi_rx_reg);
@@ -2242,10 +2213,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2242 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2213 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2243 I915_READ(pch_dpll_reg); 2214 I915_READ(pch_dpll_reg);
2244 2215
2245 if (HAS_eDP) {
2246 ironlake_disable_pll_edp(crtc);
2247 }
2248
2249 /* Switch from PCDclk to Rawclk */ 2216 /* Switch from PCDclk to Rawclk */
2250 temp = I915_READ(fdi_rx_reg); 2217 temp = I915_READ(fdi_rx_reg);
2251 temp &= ~FDI_SEL_PCDCLK; 2218 temp &= ~FDI_SEL_PCDCLK;
@@ -3930,9 +3897,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3930 dpll_reg = pch_dpll_reg; 3897 dpll_reg = pch_dpll_reg;
3931 } 3898 }
3932 3899
3933 if (is_edp) { 3900 if (!is_edp) {
3934 ironlake_disable_pll_edp(crtc);
3935 } else if ((dpll & DPLL_VCO_ENABLE)) {
3936 I915_WRITE(fp_reg, fp); 3901 I915_WRITE(fp_reg, fp);
3937 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3902 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3938 I915_READ(dpll_reg); 3903 I915_READ(dpll_reg);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8061a48804a3..caaaa8f9db3e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -831,6 +831,60 @@ static void ironlake_edp_backlight_off (struct drm_device *dev)
831 I915_WRITE(PCH_PP_CONTROL, pp); 831 I915_WRITE(PCH_PP_CONTROL, pp);
832} 832}
833 833
834static void ironlake_edp_pll_on(struct drm_encoder *encoder)
835{
836 struct drm_device *dev = encoder->dev;
837 struct drm_i915_private *dev_priv = dev->dev_private;
838 u32 dpa_ctl;
839
840 DRM_DEBUG_KMS("\n");
841 dpa_ctl = I915_READ(DP_A);
842 dpa_ctl &= ~DP_PLL_ENABLE;
843 I915_WRITE(DP_A, dpa_ctl);
844}
845
846static void ironlake_edp_pll_off(struct drm_encoder *encoder)
847{
848 struct drm_device *dev = encoder->dev;
849 struct drm_i915_private *dev_priv = dev->dev_private;
850 u32 dpa_ctl;
851
852 dpa_ctl = I915_READ(DP_A);
853 dpa_ctl |= DP_PLL_ENABLE;
854 I915_WRITE(DP_A, dpa_ctl);
855 udelay(200);
856}
857
858static void intel_dp_prepare(struct drm_encoder *encoder)
859{
860 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
861 struct drm_device *dev = encoder->dev;
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
864
865 if (IS_eDP(intel_dp)) {
866 ironlake_edp_backlight_off(dev);
867 ironlake_edp_panel_on(dev);
868 ironlake_edp_pll_on(encoder);
869 }
870 if (dp_reg & DP_PORT_EN)
871 intel_dp_link_down(intel_dp);
872}
873
874static void intel_dp_commit(struct drm_encoder *encoder)
875{
876 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
877 struct drm_device *dev = encoder->dev;
878 struct drm_i915_private *dev_priv = dev->dev_private;
879 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
880
881 if (!(dp_reg & DP_PORT_EN)) {
882 intel_dp_link_train(intel_dp);
883 }
884 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
885 ironlake_edp_backlight_on(dev);
886}
887
834static void 888static void
835intel_dp_dpms(struct drm_encoder *encoder, int mode) 889intel_dp_dpms(struct drm_encoder *encoder, int mode)
836{ 890{
@@ -846,6 +900,8 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
846 } 900 }
847 if (dp_reg & DP_PORT_EN) 901 if (dp_reg & DP_PORT_EN)
848 intel_dp_link_down(intel_dp); 902 intel_dp_link_down(intel_dp);
903 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
904 ironlake_edp_pll_off(encoder);
849 } else { 905 } else {
850 if (!(dp_reg & DP_PORT_EN)) { 906 if (!(dp_reg & DP_PORT_EN)) {
851 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) 907 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
@@ -1427,9 +1483,9 @@ intel_dp_destroy (struct drm_connector *connector)
1427static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1483static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1428 .dpms = intel_dp_dpms, 1484 .dpms = intel_dp_dpms,
1429 .mode_fixup = intel_dp_mode_fixup, 1485 .mode_fixup = intel_dp_mode_fixup,
1430 .prepare = intel_encoder_prepare, 1486 .prepare = intel_dp_prepare,
1431 .mode_set = intel_dp_mode_set, 1487 .mode_set = intel_dp_mode_set,
1432 .commit = intel_encoder_commit, 1488 .commit = intel_dp_commit,
1433}; 1489};
1434 1490
1435static const struct drm_connector_funcs intel_dp_connector_funcs = { 1491static const struct drm_connector_funcs intel_dp_connector_funcs = {