diff options
author | Bruce Allan <bruce.w.allan@intel.com> | 2009-10-26 07:22:47 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-10-26 19:16:18 -0400 |
commit | db2932ecf8dc07f65b410e921f96c5c51170c0ae (patch) | |
tree | b98ee7bcf484dfa04d1906aae860bba21b2a6396 /drivers | |
parent | 39305965f31e080d6ed96e0ff51ed11e7639d52e (diff) |
e1000e: clear PHY wakeup bit after LCD reset on 82577/82578
Performing a dummy read of the PHY Wakeup Control (WUC) register clears the
wakeup enable bit set by an PHY reset. If this bit remains set, link
problems may occur.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index aa0ab0eb8c7d..ead66510e22f 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -844,7 +844,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |||
844 | u32 i; | 844 | u32 i; |
845 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | 845 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; |
846 | s32 ret_val; | 846 | s32 ret_val; |
847 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | 847 | u16 reg, word_addr, reg_data, reg_addr, phy_page = 0; |
848 | 848 | ||
849 | ret_val = e1000e_phy_hw_reset_generic(hw); | 849 | ret_val = e1000e_phy_hw_reset_generic(hw); |
850 | if (ret_val) | 850 | if (ret_val) |
@@ -859,6 +859,10 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |||
859 | return ret_val; | 859 | return ret_val; |
860 | } | 860 | } |
861 | 861 | ||
862 | /* Dummy read to clear the phy wakeup bit after lcd reset */ | ||
863 | if (hw->mac.type == e1000_pchlan) | ||
864 | e1e_rphy(hw, BM_WUC, ®); | ||
865 | |||
862 | /* | 866 | /* |
863 | * Initialize the PHY from the NVM on ICH platforms. This | 867 | * Initialize the PHY from the NVM on ICH platforms. This |
864 | * is needed due to an issue where the NVM configuration is | 868 | * is needed due to an issue where the NVM configuration is |
@@ -2229,6 +2233,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |||
2229 | **/ | 2233 | **/ |
2230 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | 2234 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) |
2231 | { | 2235 | { |
2236 | u16 reg; | ||
2232 | u32 ctrl, icr, kab; | 2237 | u32 ctrl, icr, kab; |
2233 | s32 ret_val; | 2238 | s32 ret_val; |
2234 | 2239 | ||
@@ -2304,6 +2309,9 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
2304 | hw_dbg(hw, "Auto Read Done did not complete\n"); | 2309 | hw_dbg(hw, "Auto Read Done did not complete\n"); |
2305 | } | 2310 | } |
2306 | } | 2311 | } |
2312 | /* Dummy read to clear the phy wakeup bit after lcd reset */ | ||
2313 | if (hw->mac.type == e1000_pchlan) | ||
2314 | e1e_rphy(hw, BM_WUC, ®); | ||
2307 | 2315 | ||
2308 | /* | 2316 | /* |
2309 | * For PCH, this write will make sure that any noise | 2317 | * For PCH, this write will make sure that any noise |