[TG3]: Prescaler fix

Internal hardware timers become inaccurate after link events.  Clock
frequency switches performed by the CPMU fail to adjust timer
prescalers.  The fix is to detect core clock frequency changes during
link events and adjust the timer prescalers accordingly.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 24 insertions, 1 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index bb3b73435170..ecd64a224e95 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3154,6 +3154,22 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
                 err = tg3_setup_copper_phy(tp, force_reset);
         }
 
+        if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
+                u32 val, scale;
+
+                val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
+                if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
+                        scale = 65;
+                else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
+                        scale = 6;
+                else
+                        scale = 12;
+
+                val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
+                val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
+                tw32(GRC_MISC_CFG, val);
+        }
+
         if (tp->link_config.active_speed == SPEED_1000 &&
             tp->link_config.active_duplex == DUPLEX_HALF)
                 tw32(MAC_TX_LENGTHS,
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5b799ff2c4d6..d325ab59b391 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -874,7 +874,14 @@
 #define TG3_CPMU_HST_ACC                0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
-/* 0x3620 --> 0x365c unused */
+/* 0x3620 --> 0x3630 unused */
+
+#define TG3_CPMU_CLCK_STAT              0x00003630
+#define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
+#define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
+#define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
+#define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
+/* 0x3634 --> 0x365c unused */
 
 #define TG3_CPMU_MUTEX_REQ              0x0000365c
 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000