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authorDavid S. Miller <davem@davemloft.net>2008-01-03 23:11:31 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-04 06:55:22 -0500
commit9e1848b60d09a715ff1e19aa6fda47e061d04965 (patch)
treeef9394389d1568c0146718677246fbcbad614c5e /drivers
parent9de4dfb4c7176e5bb232a21cdd8df78da2b15cac (diff)
[CASSINI]: Program parent Intel31154 bridge when necessary.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/cassini.c86
1 files changed, 86 insertions, 0 deletions
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index 9c77eadb6767..33ac2ef67778 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -4846,6 +4846,90 @@ static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4846 return rc; 4846 return rc;
4847} 4847}
4848 4848
4849/* When this chip sits underneath an Intel 31154 bridge, it is the
4850 * only subordinate device and we can tweak the bridge settings to
4851 * reflect that fact.
4852 */
4853static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4854{
4855 struct pci_dev *pdev = cas_pdev->bus->self;
4856 u32 val;
4857
4858 if (!pdev)
4859 return;
4860
4861 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4862 return;
4863
4864 /* Clear bit 10 (Bus Parking Control) in the Secondary
4865 * Arbiter Control/Status Register which lives at offset
4866 * 0x41. Using a 32-bit word read/modify/write at 0x40
4867 * is much simpler so that's how we do this.
4868 */
4869 pci_read_config_dword(pdev, 0x40, &val);
4870 val &= ~0x00040000;
4871 pci_write_config_dword(pdev, 0x40, val);
4872
4873 /* Max out the Multi-Transaction Timer settings since
4874 * Cassini is the only device present.
4875 *
4876 * The register is 16-bit and lives at 0x50. When the
4877 * settings are enabled, it extends the GRANT# signal
4878 * for a requestor after a transaction is complete. This
4879 * allows the next request to run without first needing
4880 * to negotiate the GRANT# signal back.
4881 *
4882 * Bits 12:10 define the grant duration:
4883 *
4884 * 1 -- 16 clocks
4885 * 2 -- 32 clocks
4886 * 3 -- 64 clocks
4887 * 4 -- 128 clocks
4888 * 5 -- 256 clocks
4889 *
4890 * All other values are illegal.
4891 *
4892 * Bits 09:00 define which REQ/GNT signal pairs get the
4893 * GRANT# signal treatment. We set them all.
4894 */
4895 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4896
4897 /* The Read Prefecth Policy register is 16-bit and sits at
4898 * offset 0x52. It enables a "smart" pre-fetch policy. We
4899 * enable it and max out all of the settings since only one
4900 * device is sitting underneath and thus bandwidth sharing is
4901 * not an issue.
4902 *
4903 * The register has several 3 bit fields, which indicates a
4904 * multiplier applied to the base amount of prefetching the
4905 * chip would do. These fields are at:
4906 *
4907 * 15:13 --- ReRead Primary Bus
4908 * 12:10 --- FirstRead Primary Bus
4909 * 09:07 --- ReRead Secondary Bus
4910 * 06:04 --- FirstRead Secondary Bus
4911 *
4912 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4913 * get enabled on. Bit 3 is a grouped enabler which controls
4914 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4915 * the individual REQ/GNT pairs [2:0].
4916 */
4917 pci_write_config_word(pdev, 0x52,
4918 (0x7 << 13) |
4919 (0x7 << 10) |
4920 (0x7 << 7) |
4921 (0x7 << 4) |
4922 (0xf << 0));
4923
4924 /* Force cacheline size to 0x8 */
4925 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4926
4927 /* Force latency timer to maximum setting so Cassini can
4928 * sit on the bus as long as it likes.
4929 */
4930 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4931}
4932
4849static int __devinit cas_init_one(struct pci_dev *pdev, 4933static int __devinit cas_init_one(struct pci_dev *pdev,
4850 const struct pci_device_id *ent) 4934 const struct pci_device_id *ent)
4851{ 4935{
@@ -4901,6 +4985,8 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
4901 printk(KERN_WARNING PFX "Could not enable MWI for %s\n", 4985 printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
4902 pci_name(pdev)); 4986 pci_name(pdev));
4903 4987
4988 cas_program_bridge(pdev);
4989
4904 /* 4990 /*
4905 * On some architectures, the default cache line size set 4991 * On some architectures, the default cache line size set
4906 * by pci_try_set_mwi reduces perforamnce. We have to increase 4992 * by pci_try_set_mwi reduces perforamnce. We have to increase