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authorRichard Cochran <richardcochran@gmail.com>2011-04-22 06:04:55 -0400
committerJohn Stultz <john.stultz@linaro.org>2011-05-23 16:10:23 -0400
commitcb646e2b02b27a33a1d1eabd016749606254071c (patch)
tree28961fc0c9c26ef2d7b8c3e3e5ecc471f31b3d48 /drivers
parent32bd93e8f924c23b8cc2e2a12fef0d8cc9cda0c5 (diff)
ptp: Added a clock driver for the National Semiconductor PHYTER.
This patch adds support for the PTP clock found on the DP83640. The basic clock operations and one external time stamp have been implemented. Signed-off-by: Richard Cochran <richard.cochran@omicron.at> Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/dp83640.c1100
-rw-r--r--drivers/net/phy/dp83640_reg.h267
-rw-r--r--drivers/ptp/Kconfig19
4 files changed, 1387 insertions, 0 deletions
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab65d02..2333215bbb32 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
19obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o 19obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o 20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
21obj-$(CONFIG_NATIONAL_PHY) += national.o 21obj-$(CONFIG_NATIONAL_PHY) += national.o
22obj-$(CONFIG_DP83640_PHY) += dp83640.o
22obj-$(CONFIG_STE10XP) += ste10Xp.o 23obj-$(CONFIG_STE10XP) += ste10Xp.o
23obj-$(CONFIG_MICREL_PHY) += micrel.o 24obj-$(CONFIG_MICREL_PHY) += micrel.o
24obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o 25obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000000000000..d463b8a4afa1
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1100 @@
1/*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/ethtool.h>
21#include <linux/kernel.h>
22#include <linux/list.h>
23#include <linux/mii.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/netdevice.h>
27#include <linux/phy.h>
28#include <linux/ptp_classify.h>
29#include <linux/ptp_clock_kernel.h>
30
31#include "dp83640_reg.h"
32
33#define DP83640_PHY_ID 0x20005ce1
34#define PAGESEL 0x13
35#define LAYER4 0x02
36#define LAYER2 0x01
37#define MAX_RXTS 4
38#define MAX_TXTS 4
39#define N_EXT_TS 1
40#define PSF_PTPVER 2
41#define PSF_EVNT 0x4000
42#define PSF_RX 0x2000
43#define PSF_TX 0x1000
44#define EXT_EVENT 1
45#define EXT_GPIO 1
46#define CAL_EVENT 2
47#define CAL_GPIO 9
48#define CAL_TRIGGER 2
49
50/* phyter seems to miss the mark by 16 ns */
51#define ADJTIME_FIX 16
52
53#if defined(__BIG_ENDIAN)
54#define ENDIAN_FLAG 0
55#elif defined(__LITTLE_ENDIAN)
56#define ENDIAN_FLAG PSF_ENDIAN
57#endif
58
59#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
60
61struct phy_rxts {
62 u16 ns_lo; /* ns[15:0] */
63 u16 ns_hi; /* overflow[1:0], ns[29:16] */
64 u16 sec_lo; /* sec[15:0] */
65 u16 sec_hi; /* sec[31:16] */
66 u16 seqid; /* sequenceId[15:0] */
67 u16 msgtype; /* messageType[3:0], hash[11:0] */
68};
69
70struct phy_txts {
71 u16 ns_lo; /* ns[15:0] */
72 u16 ns_hi; /* overflow[1:0], ns[29:16] */
73 u16 sec_lo; /* sec[15:0] */
74 u16 sec_hi; /* sec[31:16] */
75};
76
77struct rxts {
78 struct list_head list;
79 unsigned long tmo;
80 u64 ns;
81 u16 seqid;
82 u8 msgtype;
83 u16 hash;
84};
85
86struct dp83640_clock;
87
88struct dp83640_private {
89 struct list_head list;
90 struct dp83640_clock *clock;
91 struct phy_device *phydev;
92 struct work_struct ts_work;
93 int hwts_tx_en;
94 int hwts_rx_en;
95 int layer;
96 int version;
97 /* remember state of cfg0 during calibration */
98 int cfg0;
99 /* remember the last event time stamp */
100 struct phy_txts edata;
101 /* list of rx timestamps */
102 struct list_head rxts;
103 struct list_head rxpool;
104 struct rxts rx_pool_data[MAX_RXTS];
105 /* protects above three fields from concurrent access */
106 spinlock_t rx_lock;
107 /* queues of incoming and outgoing packets */
108 struct sk_buff_head rx_queue;
109 struct sk_buff_head tx_queue;
110};
111
112struct dp83640_clock {
113 /* keeps the instance in the 'phyter_clocks' list */
114 struct list_head list;
115 /* we create one clock instance per MII bus */
116 struct mii_bus *bus;
117 /* protects extended registers from concurrent access */
118 struct mutex extreg_lock;
119 /* remembers which page was last selected */
120 int page;
121 /* our advertised capabilities */
122 struct ptp_clock_info caps;
123 /* protects the three fields below from concurrent access */
124 struct mutex clock_lock;
125 /* the one phyter from which we shall read */
126 struct dp83640_private *chosen;
127 /* list of the other attached phyters, not chosen */
128 struct list_head phylist;
129 /* reference to our PTP hardware clock */
130 struct ptp_clock *ptp_clock;
131};
132
133/* globals */
134
135static int chosen_phy = -1;
136static ushort cal_gpio = 4;
137
138module_param(chosen_phy, int, 0444);
139module_param(cal_gpio, ushort, 0444);
140
141MODULE_PARM_DESC(chosen_phy, \
142 "The address of the PHY to use for the ancillary clock features");
143MODULE_PARM_DESC(cal_gpio, \
144 "Which GPIO line to use for synchronizing multiple PHYs");
145
146/* a list of clocks and a mutex to protect it */
147static LIST_HEAD(phyter_clocks);
148static DEFINE_MUTEX(phyter_clocks_lock);
149
150static void rx_timestamp_work(struct work_struct *work);
151
152/* extended register access functions */
153
154#define BROADCAST_ADDR 31
155
156static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
157{
158 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
159}
160
161/* Caller must hold extreg_lock. */
162static int ext_read(struct phy_device *phydev, int page, u32 regnum)
163{
164 struct dp83640_private *dp83640 = phydev->priv;
165 int val;
166
167 if (dp83640->clock->page != page) {
168 broadcast_write(phydev->bus, PAGESEL, page);
169 dp83640->clock->page = page;
170 }
171 val = phy_read(phydev, regnum);
172
173 return val;
174}
175
176/* Caller must hold extreg_lock. */
177static void ext_write(int broadcast, struct phy_device *phydev,
178 int page, u32 regnum, u16 val)
179{
180 struct dp83640_private *dp83640 = phydev->priv;
181
182 if (dp83640->clock->page != page) {
183 broadcast_write(phydev->bus, PAGESEL, page);
184 dp83640->clock->page = page;
185 }
186 if (broadcast)
187 broadcast_write(phydev->bus, regnum, val);
188 else
189 phy_write(phydev, regnum, val);
190}
191
192/* Caller must hold extreg_lock. */
193static int tdr_write(int bc, struct phy_device *dev,
194 const struct timespec *ts, u16 cmd)
195{
196 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
197 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
198 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
199 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
200
201 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
202
203 return 0;
204}
205
206/* convert phy timestamps into driver timestamps */
207
208static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
209{
210 u32 sec;
211
212 sec = p->sec_lo;
213 sec |= p->sec_hi << 16;
214
215 rxts->ns = p->ns_lo;
216 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
217 rxts->ns += ((u64)sec) * 1000000000ULL;
218 rxts->seqid = p->seqid;
219 rxts->msgtype = (p->msgtype >> 12) & 0xf;
220 rxts->hash = p->msgtype & 0x0fff;
221 rxts->tmo = jiffies + HZ;
222}
223
224static u64 phy2txts(struct phy_txts *p)
225{
226 u64 ns;
227 u32 sec;
228
229 sec = p->sec_lo;
230 sec |= p->sec_hi << 16;
231
232 ns = p->ns_lo;
233 ns |= (p->ns_hi & 0x3fff) << 16;
234 ns += ((u64)sec) * 1000000000ULL;
235
236 return ns;
237}
238
239/* ptp clock methods */
240
241static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
242{
243 struct dp83640_clock *clock =
244 container_of(ptp, struct dp83640_clock, caps);
245 struct phy_device *phydev = clock->chosen->phydev;
246 u64 rate;
247 int neg_adj = 0;
248 u16 hi, lo;
249
250 if (ppb < 0) {
251 neg_adj = 1;
252 ppb = -ppb;
253 }
254 rate = ppb;
255 rate <<= 26;
256 rate = div_u64(rate, 1953125);
257
258 hi = (rate >> 16) & PTP_RATE_HI_MASK;
259 if (neg_adj)
260 hi |= PTP_RATE_DIR;
261
262 lo = rate & 0xffff;
263
264 mutex_lock(&clock->extreg_lock);
265
266 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
267 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
268
269 mutex_unlock(&clock->extreg_lock);
270
271 return 0;
272}
273
274static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
275{
276 struct dp83640_clock *clock =
277 container_of(ptp, struct dp83640_clock, caps);
278 struct phy_device *phydev = clock->chosen->phydev;
279 struct timespec ts;
280 int err;
281
282 delta += ADJTIME_FIX;
283
284 ts = ns_to_timespec(delta);
285
286 mutex_lock(&clock->extreg_lock);
287
288 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
289
290 mutex_unlock(&clock->extreg_lock);
291
292 return err;
293}
294
295static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
296{
297 struct dp83640_clock *clock =
298 container_of(ptp, struct dp83640_clock, caps);
299 struct phy_device *phydev = clock->chosen->phydev;
300 unsigned int val[4];
301
302 mutex_lock(&clock->extreg_lock);
303
304 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
305
306 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
307 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
308 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
309 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
310
311 mutex_unlock(&clock->extreg_lock);
312
313 ts->tv_nsec = val[0] | (val[1] << 16);
314 ts->tv_sec = val[2] | (val[3] << 16);
315
316 return 0;
317}
318
319static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
320 const struct timespec *ts)
321{
322 struct dp83640_clock *clock =
323 container_of(ptp, struct dp83640_clock, caps);
324 struct phy_device *phydev = clock->chosen->phydev;
325 int err;
326
327 mutex_lock(&clock->extreg_lock);
328
329 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
330
331 mutex_unlock(&clock->extreg_lock);
332
333 return err;
334}
335
336static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
337 struct ptp_clock_request *rq, int on)
338{
339 struct dp83640_clock *clock =
340 container_of(ptp, struct dp83640_clock, caps);
341 struct phy_device *phydev = clock->chosen->phydev;
342 u16 evnt;
343
344 switch (rq->type) {
345 case PTP_CLK_REQ_EXTTS:
346 if (rq->extts.index != 0)
347 return -EINVAL;
348 evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
349 if (on) {
350 evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
351 evnt |= EVNT_RISE;
352 }
353 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
354 return 0;
355 default:
356 break;
357 }
358
359 return -EOPNOTSUPP;
360}
361
362static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
363static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
364
365static void enable_status_frames(struct phy_device *phydev, bool on)
366{
367 u16 cfg0 = 0, ver;
368
369 if (on)
370 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
371
372 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
373
374 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
375 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
376
377 if (!phydev->attached_dev) {
378 pr_warning("dp83640: expected to find an attached netdevice\n");
379 return;
380 }
381
382 if (on) {
383 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
384 pr_warning("dp83640: failed to add mc address\n");
385 } else {
386 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
387 pr_warning("dp83640: failed to delete mc address\n");
388 }
389}
390
391static bool is_status_frame(struct sk_buff *skb, int type)
392{
393 struct ethhdr *h = eth_hdr(skb);
394
395 if (PTP_CLASS_V2_L2 == type &&
396 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
397 return true;
398 else
399 return false;
400}
401
402static int expired(struct rxts *rxts)
403{
404 return time_after(jiffies, rxts->tmo);
405}
406
407/* Caller must hold rx_lock. */
408static void prune_rx_ts(struct dp83640_private *dp83640)
409{
410 struct list_head *this, *next;
411 struct rxts *rxts;
412
413 list_for_each_safe(this, next, &dp83640->rxts) {
414 rxts = list_entry(this, struct rxts, list);
415 if (expired(rxts)) {
416 list_del_init(&rxts->list);
417 list_add(&rxts->list, &dp83640->rxpool);
418 }
419 }
420}
421
422/* synchronize the phyters so they act as one clock */
423
424static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
425{
426 int val;
427 phy_write(phydev, PAGESEL, 0);
428 val = phy_read(phydev, PHYCR2);
429 if (on)
430 val |= BC_WRITE;
431 else
432 val &= ~BC_WRITE;
433 phy_write(phydev, PHYCR2, val);
434 phy_write(phydev, PAGESEL, init_page);
435}
436
437static void recalibrate(struct dp83640_clock *clock)
438{
439 s64 now, diff;
440 struct phy_txts event_ts;
441 struct timespec ts;
442 struct list_head *this;
443 struct dp83640_private *tmp;
444 struct phy_device *master = clock->chosen->phydev;
445 u16 cfg0, evnt, ptp_trig, trigger, val;
446
447 trigger = CAL_TRIGGER;
448
449 mutex_lock(&clock->extreg_lock);
450
451 /*
452 * enable broadcast, disable status frames, enable ptp clock
453 */
454 list_for_each(this, &clock->phylist) {
455 tmp = list_entry(this, struct dp83640_private, list);
456 enable_broadcast(tmp->phydev, clock->page, 1);
457 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
458 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
459 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
460 }
461 enable_broadcast(master, clock->page, 1);
462 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
463 ext_write(0, master, PAGE5, PSF_CFG0, 0);
464 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
465
466 /*
467 * enable an event timestamp
468 */
469 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
470 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
471 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
472
473 list_for_each(this, &clock->phylist) {
474 tmp = list_entry(this, struct dp83640_private, list);
475 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
476 }
477 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
478
479 /*
480 * configure a trigger
481 */
482 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
483 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
484 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
485 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
486
487 /* load trigger */
488 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
489 val |= TRIG_LOAD;
490 ext_write(0, master, PAGE4, PTP_CTL, val);
491
492 /* enable trigger */
493 val &= ~TRIG_LOAD;
494 val |= TRIG_EN;
495 ext_write(0, master, PAGE4, PTP_CTL, val);
496
497 /* disable trigger */
498 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
499 val |= TRIG_DIS;
500 ext_write(0, master, PAGE4, PTP_CTL, val);
501
502 /*
503 * read out and correct offsets
504 */
505 val = ext_read(master, PAGE4, PTP_STS);
506 pr_info("master PTP_STS 0x%04hx", val);
507 val = ext_read(master, PAGE4, PTP_ESTS);
508 pr_info("master PTP_ESTS 0x%04hx", val);
509 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
510 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
511 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
512 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
513 now = phy2txts(&event_ts);
514
515 list_for_each(this, &clock->phylist) {
516 tmp = list_entry(this, struct dp83640_private, list);
517 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
518 pr_info("slave PTP_STS 0x%04hx", val);
519 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
520 pr_info("slave PTP_ESTS 0x%04hx", val);
521 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
522 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
523 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
524 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
525 diff = now - (s64) phy2txts(&event_ts);
526 pr_info("slave offset %lld nanoseconds\n", diff);
527 diff += ADJTIME_FIX;
528 ts = ns_to_timespec(diff);
529 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
530 }
531
532 /*
533 * restore status frames
534 */
535 list_for_each(this, &clock->phylist) {
536 tmp = list_entry(this, struct dp83640_private, list);
537 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
538 }
539 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
540
541 mutex_unlock(&clock->extreg_lock);
542}
543
544/* time stamping methods */
545
546static void decode_evnt(struct dp83640_private *dp83640,
547 struct phy_txts *phy_txts, u16 ests)
548{
549 struct ptp_clock_event event;
550 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
551
552 switch (words) { /* fall through in every case */
553 case 3:
554 dp83640->edata.sec_hi = phy_txts->sec_hi;
555 case 2:
556 dp83640->edata.sec_lo = phy_txts->sec_lo;
557 case 1:
558 dp83640->edata.ns_hi = phy_txts->ns_hi;
559 case 0:
560 dp83640->edata.ns_lo = phy_txts->ns_lo;
561 }
562
563 event.type = PTP_CLOCK_EXTTS;
564 event.index = 0;
565 event.timestamp = phy2txts(&dp83640->edata);
566
567 ptp_clock_event(dp83640->clock->ptp_clock, &event);
568}
569
570static void decode_rxts(struct dp83640_private *dp83640,
571 struct phy_rxts *phy_rxts)
572{
573 struct rxts *rxts;
574 unsigned long flags;
575
576 spin_lock_irqsave(&dp83640->rx_lock, flags);
577
578 prune_rx_ts(dp83640);
579
580 if (list_empty(&dp83640->rxpool)) {
581 pr_warning("dp83640: rx timestamp pool is empty\n");
582 goto out;
583 }
584 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
585 list_del_init(&rxts->list);
586 phy2rxts(phy_rxts, rxts);
587 list_add_tail(&rxts->list, &dp83640->rxts);
588out:
589 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
590}
591
592static void decode_txts(struct dp83640_private *dp83640,
593 struct phy_txts *phy_txts)
594{
595 struct skb_shared_hwtstamps shhwtstamps;
596 struct sk_buff *skb;
597 u64 ns;
598
599 /* We must already have the skb that triggered this. */
600
601 skb = skb_dequeue(&dp83640->tx_queue);
602
603 if (!skb) {
604 pr_warning("dp83640: have timestamp but tx_queue empty\n");
605 return;
606 }
607 ns = phy2txts(phy_txts);
608 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
609 shhwtstamps.hwtstamp = ns_to_ktime(ns);
610 skb_complete_tx_timestamp(skb, &shhwtstamps);
611}
612
613static void decode_status_frame(struct dp83640_private *dp83640,
614 struct sk_buff *skb)
615{
616 struct phy_rxts *phy_rxts;
617 struct phy_txts *phy_txts;
618 u8 *ptr;
619 int len, size;
620 u16 ests, type;
621
622 ptr = skb->data + 2;
623
624 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
625
626 type = *(u16 *)ptr;
627 ests = type & 0x0fff;
628 type = type & 0xf000;
629 len -= sizeof(type);
630 ptr += sizeof(type);
631
632 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
633
634 phy_rxts = (struct phy_rxts *) ptr;
635 decode_rxts(dp83640, phy_rxts);
636 size = sizeof(*phy_rxts);
637
638 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
639
640 phy_txts = (struct phy_txts *) ptr;
641 decode_txts(dp83640, phy_txts);
642 size = sizeof(*phy_txts);
643
644 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
645
646 phy_txts = (struct phy_txts *) ptr;
647 decode_evnt(dp83640, phy_txts, ests);
648 size = sizeof(*phy_txts);
649
650 } else {
651 size = 0;
652 break;
653 }
654 ptr += size;
655 }
656}
657
658static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
659{
660 u16 *seqid;
661 unsigned int offset;
662 u8 *msgtype, *data = skb_mac_header(skb);
663
664 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
665
666 switch (type) {
667 case PTP_CLASS_V1_IPV4:
668 case PTP_CLASS_V2_IPV4:
669 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
670 break;
671 case PTP_CLASS_V1_IPV6:
672 case PTP_CLASS_V2_IPV6:
673 offset = OFF_PTP6;
674 break;
675 case PTP_CLASS_V2_L2:
676 offset = ETH_HLEN;
677 break;
678 case PTP_CLASS_V2_VLAN:
679 offset = ETH_HLEN + VLAN_HLEN;
680 break;
681 default:
682 return 0;
683 }
684
685 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
686 return 0;
687
688 if (unlikely(type & PTP_CLASS_V1))
689 msgtype = data + offset + OFF_PTP_CONTROL;
690 else
691 msgtype = data + offset;
692
693 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
694
695 return (rxts->msgtype == (*msgtype & 0xf) &&
696 rxts->seqid == ntohs(*seqid));
697}
698
699static void dp83640_free_clocks(void)
700{
701 struct dp83640_clock *clock;
702 struct list_head *this, *next;
703
704 mutex_lock(&phyter_clocks_lock);
705
706 list_for_each_safe(this, next, &phyter_clocks) {
707 clock = list_entry(this, struct dp83640_clock, list);
708 if (!list_empty(&clock->phylist)) {
709 pr_warning("phy list non-empty while unloading");
710 BUG();
711 }
712 list_del(&clock->list);
713 mutex_destroy(&clock->extreg_lock);
714 mutex_destroy(&clock->clock_lock);
715 put_device(&clock->bus->dev);
716 kfree(clock);
717 }
718
719 mutex_unlock(&phyter_clocks_lock);
720}
721
722static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
723{
724 INIT_LIST_HEAD(&clock->list);
725 clock->bus = bus;
726 mutex_init(&clock->extreg_lock);
727 mutex_init(&clock->clock_lock);
728 INIT_LIST_HEAD(&clock->phylist);
729 clock->caps.owner = THIS_MODULE;
730 sprintf(clock->caps.name, "dp83640 timer");
731 clock->caps.max_adj = 1953124;
732 clock->caps.n_alarm = 0;
733 clock->caps.n_ext_ts = N_EXT_TS;
734 clock->caps.n_per_out = 0;
735 clock->caps.pps = 0;
736 clock->caps.adjfreq = ptp_dp83640_adjfreq;
737 clock->caps.adjtime = ptp_dp83640_adjtime;
738 clock->caps.gettime = ptp_dp83640_gettime;
739 clock->caps.settime = ptp_dp83640_settime;
740 clock->caps.enable = ptp_dp83640_enable;
741 /*
742 * Get a reference to this bus instance.
743 */
744 get_device(&bus->dev);
745}
746
747static int choose_this_phy(struct dp83640_clock *clock,
748 struct phy_device *phydev)
749{
750 if (chosen_phy == -1 && !clock->chosen)
751 return 1;
752
753 if (chosen_phy == phydev->addr)
754 return 1;
755
756 return 0;
757}
758
759static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
760{
761 if (clock)
762 mutex_lock(&clock->clock_lock);
763 return clock;
764}
765
766/*
767 * Look up and lock a clock by bus instance.
768 * If there is no clock for this bus, then create it first.
769 */
770static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
771{
772 struct dp83640_clock *clock = NULL, *tmp;
773 struct list_head *this;
774
775 mutex_lock(&phyter_clocks_lock);
776
777 list_for_each(this, &phyter_clocks) {
778 tmp = list_entry(this, struct dp83640_clock, list);
779 if (tmp->bus == bus) {
780 clock = tmp;
781 break;
782 }
783 }
784 if (clock)
785 goto out;
786
787 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
788 if (!clock)
789 goto out;
790
791 dp83640_clock_init(clock, bus);
792 list_add_tail(&phyter_clocks, &clock->list);
793out:
794 mutex_unlock(&phyter_clocks_lock);
795
796 return dp83640_clock_get(clock);
797}
798
799static void dp83640_clock_put(struct dp83640_clock *clock)
800{
801 mutex_unlock(&clock->clock_lock);
802}
803
804static int dp83640_probe(struct phy_device *phydev)
805{
806 struct dp83640_clock *clock;
807 struct dp83640_private *dp83640;
808 int err = -ENOMEM, i;
809
810 if (phydev->addr == BROADCAST_ADDR)
811 return 0;
812
813 clock = dp83640_clock_get_bus(phydev->bus);
814 if (!clock)
815 goto no_clock;
816
817 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
818 if (!dp83640)
819 goto no_memory;
820
821 dp83640->phydev = phydev;
822 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
823
824 INIT_LIST_HEAD(&dp83640->rxts);
825 INIT_LIST_HEAD(&dp83640->rxpool);
826 for (i = 0; i < MAX_RXTS; i++)
827 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
828
829 phydev->priv = dp83640;
830
831 spin_lock_init(&dp83640->rx_lock);
832 skb_queue_head_init(&dp83640->rx_queue);
833 skb_queue_head_init(&dp83640->tx_queue);
834
835 dp83640->clock = clock;
836
837 if (choose_this_phy(clock, phydev)) {
838 clock->chosen = dp83640;
839 clock->ptp_clock = ptp_clock_register(&clock->caps);
840 if (IS_ERR(clock->ptp_clock)) {
841 err = PTR_ERR(clock->ptp_clock);
842 goto no_register;
843 }
844 } else
845 list_add_tail(&dp83640->list, &clock->phylist);
846
847 if (clock->chosen && !list_empty(&clock->phylist))
848 recalibrate(clock);
849 else
850 enable_broadcast(dp83640->phydev, clock->page, 1);
851
852 dp83640_clock_put(clock);
853 return 0;
854
855no_register:
856 clock->chosen = NULL;
857 kfree(dp83640);
858no_memory:
859 dp83640_clock_put(clock);
860no_clock:
861 return err;
862}
863
864static void dp83640_remove(struct phy_device *phydev)
865{
866 struct dp83640_clock *clock;
867 struct list_head *this, *next;
868 struct dp83640_private *tmp, *dp83640 = phydev->priv;
869
870 if (phydev->addr == BROADCAST_ADDR)
871 return;
872
873 enable_status_frames(phydev, false);
874 cancel_work_sync(&dp83640->ts_work);
875
876 clock = dp83640_clock_get(dp83640->clock);
877
878 if (dp83640 == clock->chosen) {
879 ptp_clock_unregister(clock->ptp_clock);
880 clock->chosen = NULL;
881 } else {
882 list_for_each_safe(this, next, &clock->phylist) {
883 tmp = list_entry(this, struct dp83640_private, list);
884 if (tmp == dp83640) {
885 list_del_init(&tmp->list);
886 break;
887 }
888 }
889 }
890
891 dp83640_clock_put(clock);
892 kfree(dp83640);
893}
894
895static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
896{
897 struct dp83640_private *dp83640 = phydev->priv;
898 struct hwtstamp_config cfg;
899 u16 txcfg0, rxcfg0;
900
901 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
902 return -EFAULT;
903
904 if (cfg.flags) /* reserved for future extensions */
905 return -EINVAL;
906
907 switch (cfg.tx_type) {
908 case HWTSTAMP_TX_OFF:
909 dp83640->hwts_tx_en = 0;
910 break;
911 case HWTSTAMP_TX_ON:
912 dp83640->hwts_tx_en = 1;
913 break;
914 default:
915 return -ERANGE;
916 }
917
918 switch (cfg.rx_filter) {
919 case HWTSTAMP_FILTER_NONE:
920 dp83640->hwts_rx_en = 0;
921 dp83640->layer = 0;
922 dp83640->version = 0;
923 break;
924 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
925 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
926 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
927 dp83640->hwts_rx_en = 1;
928 dp83640->layer = LAYER4;
929 dp83640->version = 1;
930 break;
931 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
932 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
933 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
934 dp83640->hwts_rx_en = 1;
935 dp83640->layer = LAYER4;
936 dp83640->version = 2;
937 break;
938 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
939 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
940 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
941 dp83640->hwts_rx_en = 1;
942 dp83640->layer = LAYER2;
943 dp83640->version = 2;
944 break;
945 case HWTSTAMP_FILTER_PTP_V2_EVENT:
946 case HWTSTAMP_FILTER_PTP_V2_SYNC:
947 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
948 dp83640->hwts_rx_en = 1;
949 dp83640->layer = LAYER4|LAYER2;
950 dp83640->version = 2;
951 break;
952 default:
953 return -ERANGE;
954 }
955
956 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
957 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
958
959 if (dp83640->layer & LAYER2) {
960 txcfg0 |= TX_L2_EN;
961 rxcfg0 |= RX_L2_EN;
962 }
963 if (dp83640->layer & LAYER4) {
964 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
965 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
966 }
967
968 if (dp83640->hwts_tx_en)
969 txcfg0 |= TX_TS_EN;
970
971 if (dp83640->hwts_rx_en)
972 rxcfg0 |= RX_TS_EN;
973
974 mutex_lock(&dp83640->clock->extreg_lock);
975
976 if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
977 enable_status_frames(phydev, true);
978 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
979 }
980
981 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
982 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
983
984 mutex_unlock(&dp83640->clock->extreg_lock);
985
986 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
987}
988
989static void rx_timestamp_work(struct work_struct *work)
990{
991 struct dp83640_private *dp83640 =
992 container_of(work, struct dp83640_private, ts_work);
993 struct list_head *this, *next;
994 struct rxts *rxts;
995 struct skb_shared_hwtstamps *shhwtstamps;
996 struct sk_buff *skb;
997 unsigned int type;
998 unsigned long flags;
999
1000 /* Deliver each deferred packet, with or without a time stamp. */
1001
1002 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1003 type = SKB_PTP_TYPE(skb);
1004 spin_lock_irqsave(&dp83640->rx_lock, flags);
1005 list_for_each_safe(this, next, &dp83640->rxts) {
1006 rxts = list_entry(this, struct rxts, list);
1007 if (match(skb, type, rxts)) {
1008 shhwtstamps = skb_hwtstamps(skb);
1009 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1010 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1011 list_del_init(&rxts->list);
1012 list_add(&rxts->list, &dp83640->rxpool);
1013 break;
1014 }
1015 }
1016 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1017 netif_rx(skb);
1018 }
1019
1020 /* Clear out expired time stamps. */
1021
1022 spin_lock_irqsave(&dp83640->rx_lock, flags);
1023 prune_rx_ts(dp83640);
1024 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1025}
1026
1027static bool dp83640_rxtstamp(struct phy_device *phydev,
1028 struct sk_buff *skb, int type)
1029{
1030 struct dp83640_private *dp83640 = phydev->priv;
1031
1032 if (!dp83640->hwts_rx_en)
1033 return false;
1034
1035 if (is_status_frame(skb, type)) {
1036 decode_status_frame(dp83640, skb);
1037 /* Let the stack drop this frame. */
1038 return false;
1039 }
1040
1041 SKB_PTP_TYPE(skb) = type;
1042 skb_queue_tail(&dp83640->rx_queue, skb);
1043 schedule_work(&dp83640->ts_work);
1044
1045 return true;
1046}
1047
1048static void dp83640_txtstamp(struct phy_device *phydev,
1049 struct sk_buff *skb, int type)
1050{
1051 struct dp83640_private *dp83640 = phydev->priv;
1052
1053 if (!dp83640->hwts_tx_en) {
1054 kfree_skb(skb);
1055 return;
1056 }
1057 skb_queue_tail(&dp83640->tx_queue, skb);
1058 schedule_work(&dp83640->ts_work);
1059}
1060
1061static struct phy_driver dp83640_driver = {
1062 .phy_id = DP83640_PHY_ID,
1063 .phy_id_mask = 0xfffffff0,
1064 .name = "NatSemi DP83640",
1065 .features = PHY_BASIC_FEATURES,
1066 .flags = 0,
1067 .probe = dp83640_probe,
1068 .remove = dp83640_remove,
1069 .config_aneg = genphy_config_aneg,
1070 .read_status = genphy_read_status,
1071 .hwtstamp = dp83640_hwtstamp,
1072 .rxtstamp = dp83640_rxtstamp,
1073 .txtstamp = dp83640_txtstamp,
1074 .driver = {.owner = THIS_MODULE,}
1075};
1076
1077static int __init dp83640_init(void)
1078{
1079 return phy_driver_register(&dp83640_driver);
1080}
1081
1082static void __exit dp83640_exit(void)
1083{
1084 dp83640_free_clocks();
1085 phy_driver_unregister(&dp83640_driver);
1086}
1087
1088MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1089MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
1090MODULE_LICENSE("GPL");
1091
1092module_init(dp83640_init);
1093module_exit(dp83640_exit);
1094
1095static struct mdio_device_id dp83640_tbl[] = {
1096 { DP83640_PHY_ID, 0xfffffff0 },
1097 { }
1098};
1099
1100MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
new file mode 100644
index 000000000000..e7fe41117003
--- /dev/null
+++ b/drivers/net/phy/dp83640_reg.h
@@ -0,0 +1,267 @@
1/* dp83640_reg.h
2 * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
3 */
4#ifndef HAVE_DP83640_REGISTERS
5#define HAVE_DP83640_REGISTERS
6
7#define PAGE0 0x0000
8#define PHYCR2 0x001c /* PHY Control Register 2 */
9
10#define PAGE4 0x0004
11#define PTP_CTL 0x0014 /* PTP Control Register */
12#define PTP_TDR 0x0015 /* PTP Time Data Register */
13#define PTP_STS 0x0016 /* PTP Status Register */
14#define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
15#define PTP_RATEL 0x0018 /* PTP Rate Low Register */
16#define PTP_RATEH 0x0019 /* PTP Rate High Register */
17#define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
18#define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
19#define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
20#define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
21#define PTP_ESTS 0x001e /* PTP Event Status Register */
22#define PTP_EDATA 0x001f /* PTP Event Data Register */
23
24#define PAGE5 0x0005
25#define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
26#define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
27#define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
28#define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
29#define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
30#define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
31#define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
32#define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
33#define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
34#define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
35#define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
36#define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
37
38#define PAGE6 0x0006
39#define PTP_COC 0x0014 /* PTP Clock Output Control Register */
40#define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
41#define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
42#define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
43#define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
44#define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
45#define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
46#define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
47#define PTP_ETR 0x001c /* PTP Ethernet Type Register */
48#define PTP_OFF 0x001d /* PTP Offset Register */
49#define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
50#define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
51
52/* Bit definitions for the PHYCR2 register */
53#define BC_WRITE (1<<11) /* Broadcast Write Enable */
54
55/* Bit definitions for the PTP_CTL register */
56#define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
57#define TRIG_SEL_MASK (0x7)
58#define TRIG_DIS (1<<9) /* Disable PTP Trigger */
59#define TRIG_EN (1<<8) /* Enable PTP Trigger */
60#define TRIG_READ (1<<7) /* Read PTP Trigger */
61#define TRIG_LOAD (1<<6) /* Load PTP Trigger */
62#define PTP_RD_CLK (1<<5) /* Read PTP Clock */
63#define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
64#define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
65#define PTP_ENABLE (1<<2) /* Enable PTP Clock */
66#define PTP_DISABLE (1<<1) /* Disable PTP Clock */
67#define PTP_RESET (1<<0) /* Reset PTP Clock */
68
69/* Bit definitions for the PTP_STS register */
70#define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
71#define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
72#define TRIG_DONE (1<<9) /* PTP Trigger Done */
73#define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
74#define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
75#define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
76#define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
77#define EVENT_IE (1<<0) /* Event Interrupt Enable */
78
79/* Bit definitions for the PTP_TSTS register */
80#define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
81#define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
82#define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
83#define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
84#define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
85#define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
86#define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
87#define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
88#define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
89#define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
90#define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
91#define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
92#define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
93#define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
94#define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
95#define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
96
97/* Bit definitions for the PTP_RATEH register */
98#define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
99#define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
100#define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
101#define PTP_RATE_HI_MASK (0x3ff)
102
103/* Bit definitions for the PTP_ESTS register */
104#define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
105#define EVNTS_MISSED_MASK (0x7)
106#define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
107#define EVNT_TS_LEN_MASK (0x3)
108#define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
109#define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
110#define EVNT_NUM_MASK (0x7)
111#define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
112#define EVENT_DET (1<<0) /* PTP Event Detected */
113
114/* Bit definitions for the PTP_EDATA register */
115#define E7_RISE (1<<15) /* Indicates direction of Event 7 */
116#define E7_DET (1<<14) /* Indicates Event 7 detected */
117#define E6_RISE (1<<13) /* Indicates direction of Event 6 */
118#define E6_DET (1<<12) /* Indicates Event 6 detected */
119#define E5_RISE (1<<11) /* Indicates direction of Event 5 */
120#define E5_DET (1<<10) /* Indicates Event 5 detected */
121#define E4_RISE (1<<9) /* Indicates direction of Event 4 */
122#define E4_DET (1<<8) /* Indicates Event 4 detected */
123#define E3_RISE (1<<7) /* Indicates direction of Event 3 */
124#define E3_DET (1<<6) /* Indicates Event 3 detected */
125#define E2_RISE (1<<5) /* Indicates direction of Event 2 */
126#define E2_DET (1<<4) /* Indicates Event 2 detected */
127#define E1_RISE (1<<3) /* Indicates direction of Event 1 */
128#define E1_DET (1<<2) /* Indicates Event 1 detected */
129#define E0_RISE (1<<1) /* Indicates direction of Event 0 */
130#define E0_DET (1<<0) /* Indicates Event 0 detected */
131
132/* Bit definitions for the PTP_TRIG register */
133#define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
134#define TRIG_PER (1<<14) /* generate a periodic signal */
135#define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
136#define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
137#define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
138#define TRIG_GPIO_MASK (0xf)
139#define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
140#define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
141#define TRIG_CSEL_MASK (0x7)
142#define TRIG_WR (1<<0) /* Trigger Configuration Write */
143
144/* Bit definitions for the PTP_EVNT register */
145#define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
146#define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
147#define EVNT_SINGLE (1<<12) /* enable single event capture operation */
148#define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
149#define EVNT_GPIO_MASK (0xf)
150#define EVNT_SEL_SHIFT (1) /* Event Select */
151#define EVNT_SEL_MASK (0x7)
152#define EVNT_WR (1<<0) /* Event Configuration Write */
153
154/* Bit definitions for the PTP_TXCFG0 register */
155#define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
156#define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
157#define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
158#define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
159#define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
160#define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
161#define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
162#define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
163#define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
164#define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
165#define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
166#define TX_PTP_VER_MASK (0xf)
167#define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
168
169/* Bit definitions for the PTP_TXCFG1 register */
170#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
171#define BYTE0_MASK_MASK (0xff)
172#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
173#define BYTE0_DATA_MASK (0xff)
174
175/* Bit definitions for the PSF_CFG0 register */
176#define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
177#define MAC_SRC_ADD_MASK (0x3)
178#define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
179#define MIN_PRE_MASK (0x7)
180#define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
181#define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
182#define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
183#define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
184#define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
185#define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
186#define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
187#define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
188
189/* Bit definitions for the PTP_RXCFG0 register */
190#define DOMAIN_EN (1<<15) /* Domain Match Enable */
191#define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
192#define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
193#define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
194#define RX_SLAVE (1<<11) /* Receive Slave Only */
195#define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
196#define IP1588_EN_MASK (0xf)
197#define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
198#define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
199#define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
200#define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
201#define RX_PTP_VER_MASK (0xf)
202#define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
203
204/* Bit definitions for the PTP_RXCFG1 register */
205#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
206#define BYTE0_MASK_MASK (0xff)
207#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
208#define BYTE0_DATA_MASK (0xff)
209
210/* Bit definitions for the PTP_RXCFG3 register */
211#define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
212#define TS_MIN_IFG_MASK (0xf)
213#define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
214#define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
215#define TS_APPEND (1<<9) /* Append Timestamp for L2 */
216#define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
217#define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
218#define PTP_DOMAIN_MASK (0xff)
219
220/* Bit definitions for the PTP_RXCFG4 register */
221#define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
222#define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
223#define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
224#define TS_SEC_LEN_MASK (0x3)
225#define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
226#define RXTS_NS_OFF_MASK (0x3f)
227#define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
228#define RXTS_SEC_OFF_MASK (0x3f)
229
230/* Bit definitions for the PTP_COC register */
231#define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
232#define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
233#define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
234#define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
235#define PTP_CLKDIV_MASK (0xff)
236
237/* Bit definitions for the PSF_CFG1 register */
238#define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
239#define PTPRESERVED_MASK (0xf)
240#define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
241#define VERSIONPTP_MASK (0xf)
242#define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
243#define TRANSPORT_SPECIFIC_MASK (0xf)
244#define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
245#define MESSAGETYPE_MASK (0xf)
246
247/* Bit definitions for the PTP_SFDCFG register */
248#define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
249#define TX_SFD_GPIO_MASK (0xf)
250#define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
251#define RX_SFD_GPIO_MASK (0xf)
252
253/* Bit definitions for the PTP_INTCTL register */
254#define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
255#define PTP_INT_GPIO_MASK (0xf)
256
257/* Bit definitions for the PTP_CLKSRC register */
258#define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
259#define CLK_SRC_MASK (0x3)
260#define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
261#define CLK_SRC_PER_MASK (0x7f)
262
263/* Bit definitions for the PTP_OFF register */
264#define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
265#define PTP_OFFSET_MASK (0xff)
266
267#endif
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index fcfafd091fdd..68d720102296 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -53,4 +53,23 @@ config PTP_1588_CLOCK_IXP46X
53 To compile this driver as a module, choose M here: the module 53 To compile this driver as a module, choose M here: the module
54 will be called ptp_ixp46x. 54 will be called ptp_ixp46x.
55 55
56comment "Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks."
57 depends on PTP_1588_CLOCK && (PHYLIB=n || NETWORK_PHY_TIMESTAMPING=n)
58
59config DP83640_PHY
60 tristate "Driver for the National Semiconductor DP83640 PHYTER"
61 depends on PTP_1588_CLOCK
62 depends on NETWORK_PHY_TIMESTAMPING
63 depends on PHYLIB
64 ---help---
65 Supports the DP83640 PHYTER with IEEE 1588 features.
66
67 This driver adds support for using the DP83640 as a PTP
68 clock. This clock is only useful if your PTP programs are
69 getting hardware time stamps on the PTP Ethernet packets
70 using the SO_TIMESTAMPING API.
71
72 In order for this to work, your MAC driver must also
73 implement the skb_tx_timetamp() function.
74
56endmenu 75endmenu
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 11:39:36 -0500