diff options
| author | Igor M. Liplianin <liplianin@netup.ru> | 2009-11-06 21:23:29 -0500 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2009-12-05 15:41:25 -0500 |
| commit | ab7134f1bd26a547a51c36dd44c55b15b3e15a6f (patch) | |
| tree | 732da2bcdd26a523d0262baa5535e18be711de7a /drivers | |
| parent | 46960eea9c0f7abb3a0a65276939762b97eac337 (diff) | |
V4L/DVB (13339): stv0900: big rework to support cut 3.0.
Patch 2 of 4.
Also patch changes logic to prevent code repetitions and big indents.
It makes checkpatch silent :)
Signed-off-by: Igor M. Liplianin <liplianin@netup.ru>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/dvb/frontends/stv0900_reg.h | 5000 |
1 files changed, 2594 insertions, 2406 deletions
diff --git a/drivers/media/dvb/frontends/stv0900_reg.h b/drivers/media/dvb/frontends/stv0900_reg.h index 264f9cf9a17e..7b8edf192e97 100644 --- a/drivers/media/dvb/frontends/stv0900_reg.h +++ b/drivers/media/dvb/frontends/stv0900_reg.h | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | * | 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, | 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * | 18 | * |
| 19 | * GNU General Public License for more details. | 19 | * GNU General Public License for more details. |
| 20 | * | 20 | * |
| @@ -26,3762 +26,3950 @@ | |||
| 26 | #ifndef STV0900_REG_H | 26 | #ifndef STV0900_REG_H |
| 27 | #define STV0900_REG_H | 27 | #define STV0900_REG_H |
| 28 | 28 | ||
| 29 | extern s32 shiftx(s32 x, int demod, s32 shift); | ||
| 30 | |||
| 31 | #define REGx(x) shiftx(x, demod, 0x200) | ||
| 32 | #define FLDx(x) shiftx(x, demod, 0x2000000) | ||
| 33 | |||
| 29 | /*MID*/ | 34 | /*MID*/ |
| 30 | #define R0900_MID 0xf100 | 35 | #define R0900_MID 0xf100 |
| 31 | #define F0900_MCHIP_IDENT 0xf10000f0 | 36 | #define F0900_MCHIP_IDENT 0xf10000f0 |
| 32 | #define F0900_MRELEASE 0xf100000f | 37 | #define F0900_MRELEASE 0xf100000f |
| 33 | 38 | ||
| 34 | /*DACR1*/ | 39 | /*DACR1*/ |
| 35 | #define R0900_DACR1 0xf113 | 40 | #define R0900_DACR1 0xf113 |
| 36 | #define F0900_DAC_MODE 0xf11300e0 | 41 | #define F0900_DAC_MODE 0xf11300e0 |
| 37 | #define F0900_DAC_VALUE1 0xf113000f | 42 | #define F0900_DAC_VALUE1 0xf113000f |
| 38 | 43 | ||
| 39 | /*DACR2*/ | 44 | /*DACR2*/ |
| 40 | #define R0900_DACR2 0xf114 | 45 | #define R0900_DACR2 0xf114 |
| 41 | #define F0900_DAC_VALUE0 0xf11400ff | 46 | #define F0900_DAC_VALUE0 0xf11400ff |
| 42 | 47 | ||
| 43 | /*OUTCFG*/ | 48 | /*OUTCFG*/ |
| 44 | #define R0900_OUTCFG 0xf11c | 49 | #define R0900_OUTCFG 0xf11c |
| 45 | #define F0900_INV_DATA6 0xf11c0080 | 50 | #define F0900_OUTSERRS1_HZ 0xf11c0040 |
| 46 | #define F0900_OUTSERRS1_HZ 0xf11c0040 | 51 | #define F0900_OUTSERRS2_HZ 0xf11c0020 |
| 47 | #define F0900_OUTSERRS2_HZ 0xf11c0020 | 52 | #define F0900_OUTSERRS3_HZ 0xf11c0010 |
| 48 | #define F0900_OUTSERRS3_HZ 0xf11c0010 | 53 | #define F0900_OUTPARRS3_HZ 0xf11c0008 |
| 49 | #define F0900_OUTPARRS3_HZ 0xf11c0008 | ||
| 50 | #define F0900_OUTHZ3_CONTROL 0xf11c0007 | ||
| 51 | |||
| 52 | /*MODECFG*/ | ||
| 53 | #define R0900_MODECFG 0xf11d | ||
| 54 | #define F0900_FECSPY_SEL_2 0xf11d0020 | ||
| 55 | #define F0900_HWARE_SEL_2 0xf11d0010 | ||
| 56 | #define F0900_PKTDEL_SEL_2 0xf11d0008 | ||
| 57 | #define F0900_DISEQC_SEL_2 0xf11d0004 | ||
| 58 | #define F0900_VIT_SEL_2 0xf11d0002 | ||
| 59 | #define F0900_DEMOD_SEL_2 0xf11d0001 | ||
| 60 | 54 | ||
| 61 | /*IRQSTATUS3*/ | 55 | /*IRQSTATUS3*/ |
| 62 | #define R0900_IRQSTATUS3 0xf120 | 56 | #define R0900_IRQSTATUS3 0xf120 |
| 63 | #define F0900_SPLL_LOCK 0xf1200020 | 57 | #define F0900_SPLL_LOCK 0xf1200020 |
| 64 | #define F0900_SSTREAM_LCK_3 0xf1200010 | 58 | #define F0900_SSTREAM_LCK_3 0xf1200010 |
| 65 | #define F0900_SSTREAM_LCK_2 0xf1200008 | 59 | #define F0900_SSTREAM_LCK_2 0xf1200008 |
| 66 | #define F0900_SSTREAM_LCK_1 0xf1200004 | 60 | #define F0900_SSTREAM_LCK_1 0xf1200004 |
| 67 | #define F0900_SDVBS1_PRF_2 0xf1200002 | 61 | #define F0900_SDVBS1_PRF_2 0xf1200002 |
| 68 | #define F0900_SDVBS1_PRF_1 0xf1200001 | 62 | #define F0900_SDVBS1_PRF_1 0xf1200001 |
| 69 | 63 | ||
| 70 | /*IRQSTATUS2*/ | 64 | /*IRQSTATUS2*/ |
| 71 | #define R0900_IRQSTATUS2 0xf121 | 65 | #define R0900_IRQSTATUS2 0xf121 |
| 72 | #define F0900_SSPY_ENDSIM_3 0xf1210080 | 66 | #define F0900_SSPY_ENDSIM_3 0xf1210080 |
| 73 | #define F0900_SSPY_ENDSIM_2 0xf1210040 | 67 | #define F0900_SSPY_ENDSIM_2 0xf1210040 |
| 74 | #define F0900_SSPY_ENDSIM_1 0xf1210020 | 68 | #define F0900_SSPY_ENDSIM_1 0xf1210020 |
| 75 | #define F0900_SPKTDEL_ERROR_2 0xf1210010 | 69 | #define F0900_SPKTDEL_ERROR_2 0xf1210010 |
| 76 | #define F0900_SPKTDEL_LOCKB_2 0xf1210008 | 70 | #define F0900_SPKTDEL_LOCKB_2 0xf1210008 |
| 77 | #define F0900_SPKTDEL_LOCK_2 0xf1210004 | 71 | #define F0900_SPKTDEL_LOCK_2 0xf1210004 |
| 78 | #define F0900_SPKTDEL_ERROR_1 0xf1210002 | 72 | #define F0900_SPKTDEL_ERROR_1 0xf1210002 |
| 79 | #define F0900_SPKTDEL_LOCKB_1 0xf1210001 | 73 | #define F0900_SPKTDEL_LOCKB_1 0xf1210001 |
| 80 | 74 | ||
| 81 | /*IRQSTATUS1*/ | 75 | /*IRQSTATUS1*/ |
| 82 | #define R0900_IRQSTATUS1 0xf122 | 76 | #define R0900_IRQSTATUS1 0xf122 |
| 83 | #define F0900_SPKTDEL_LOCK_1 0xf1220080 | 77 | #define F0900_SPKTDEL_LOCK_1 0xf1220080 |
| 84 | #define F0900_SEXTPINB2 0xf1220040 | 78 | #define F0900_SDEMOD_LOCKB_2 0xf1220004 |
| 85 | #define F0900_SEXTPIN2 0xf1220020 | 79 | #define F0900_SDEMOD_LOCK_2 0xf1220002 |
| 86 | #define F0900_SEXTPINB1 0xf1220010 | 80 | #define F0900_SDEMOD_IRQ_2 0xf1220001 |
| 87 | #define F0900_SEXTPIN1 0xf1220008 | ||
| 88 | #define F0900_SDEMOD_LOCKB_2 0xf1220004 | ||
| 89 | #define F0900_SDEMOD_LOCK_2 0xf1220002 | ||
| 90 | #define F0900_SDEMOD_IRQ_2 0xf1220001 | ||
| 91 | 81 | ||
| 92 | /*IRQSTATUS0*/ | 82 | /*IRQSTATUS0*/ |
| 93 | #define R0900_IRQSTATUS0 0xf123 | 83 | #define R0900_IRQSTATUS0 0xf123 |
| 94 | #define F0900_SDEMOD_LOCKB_1 0xf1230080 | 84 | #define F0900_SDEMOD_LOCKB_1 0xf1230080 |
| 95 | #define F0900_SDEMOD_LOCK_1 0xf1230040 | 85 | #define F0900_SDEMOD_LOCK_1 0xf1230040 |
| 96 | #define F0900_SDEMOD_IRQ_1 0xf1230020 | 86 | #define F0900_SDEMOD_IRQ_1 0xf1230020 |
| 97 | #define F0900_SBCH_ERRFLAG 0xf1230010 | 87 | #define F0900_SBCH_ERRFLAG 0xf1230010 |
| 98 | #define F0900_SDISEQC2RX_IRQ 0xf1230008 | 88 | #define F0900_SDISEQC2RX_IRQ 0xf1230008 |
| 99 | #define F0900_SDISEQC2TX_IRQ 0xf1230004 | 89 | #define F0900_SDISEQC2TX_IRQ 0xf1230004 |
| 100 | #define F0900_SDISEQC1RX_IRQ 0xf1230002 | 90 | #define F0900_SDISEQC1RX_IRQ 0xf1230002 |
| 101 | #define F0900_SDISEQC1TX_IRQ 0xf1230001 | 91 | #define F0900_SDISEQC1TX_IRQ 0xf1230001 |
| 102 | 92 | ||
| 103 | /*IRQMASK3*/ | 93 | /*IRQMASK3*/ |
| 104 | #define R0900_IRQMASK3 0xf124 | 94 | #define R0900_IRQMASK3 0xf124 |
| 105 | #define F0900_MPLL_LOCK 0xf1240020 | 95 | #define F0900_MPLL_LOCK 0xf1240020 |
| 106 | #define F0900_MSTREAM_LCK_3 0xf1240010 | 96 | #define F0900_MSTREAM_LCK_3 0xf1240010 |
| 107 | #define F0900_MSTREAM_LCK_2 0xf1240008 | 97 | #define F0900_MSTREAM_LCK_2 0xf1240008 |
| 108 | #define F0900_MSTREAM_LCK_1 0xf1240004 | 98 | #define F0900_MSTREAM_LCK_1 0xf1240004 |
| 109 | #define F0900_MDVBS1_PRF_2 0xf1240002 | 99 | #define F0900_MDVBS1_PRF_2 0xf1240002 |
| 110 | #define F0900_MDVBS1_PRF_1 0xf1240001 | 100 | #define F0900_MDVBS1_PRF_1 0xf1240001 |
| 111 | 101 | ||
| 112 | /*IRQMASK2*/ | 102 | /*IRQMASK2*/ |
| 113 | #define R0900_IRQMASK2 0xf125 | 103 | #define R0900_IRQMASK2 0xf125 |
| 114 | #define F0900_MSPY_ENDSIM_3 0xf1250080 | 104 | #define F0900_MSPY_ENDSIM_3 0xf1250080 |
| 115 | #define F0900_MSPY_ENDSIM_2 0xf1250040 | 105 | #define F0900_MSPY_ENDSIM_2 0xf1250040 |
| 116 | #define F0900_MSPY_ENDSIM_1 0xf1250020 | 106 | #define F0900_MSPY_ENDSIM_1 0xf1250020 |
| 117 | #define F0900_MPKTDEL_ERROR_2 0xf1250010 | 107 | #define F0900_MPKTDEL_ERROR_2 0xf1250010 |
| 118 | #define F0900_MPKTDEL_LOCKB_2 0xf1250008 | 108 | #define F0900_MPKTDEL_LOCKB_2 0xf1250008 |
| 119 | #define F0900_MPKTDEL_LOCK_2 0xf1250004 | 109 | #define F0900_MPKTDEL_LOCK_2 0xf1250004 |
| 120 | #define F0900_MPKTDEL_ERROR_1 0xf1250002 | 110 | #define F0900_MPKTDEL_ERROR_1 0xf1250002 |
| 121 | #define F0900_MPKTDEL_LOCKB_1 0xf1250001 | 111 | #define F0900_MPKTDEL_LOCKB_1 0xf1250001 |
| 122 | 112 | ||
| 123 | /*IRQMASK1*/ | 113 | /*IRQMASK1*/ |
| 124 | #define R0900_IRQMASK1 0xf126 | 114 | #define R0900_IRQMASK1 0xf126 |
| 125 | #define F0900_MPKTDEL_LOCK_1 0xf1260080 | 115 | #define F0900_MPKTDEL_LOCK_1 0xf1260080 |
| 126 | #define F0900_MEXTPINB2 0xf1260040 | 116 | #define F0900_MEXTPINB2 0xf1260040 |
| 127 | #define F0900_MEXTPIN2 0xf1260020 | 117 | #define F0900_MEXTPIN2 0xf1260020 |
| 128 | #define F0900_MEXTPINB1 0xf1260010 | 118 | #define F0900_MEXTPINB1 0xf1260010 |
| 129 | #define F0900_MEXTPIN1 0xf1260008 | 119 | #define F0900_MEXTPIN1 0xf1260008 |
| 130 | #define F0900_MDEMOD_LOCKB_2 0xf1260004 | 120 | #define F0900_MDEMOD_LOCKB_2 0xf1260004 |
| 131 | #define F0900_MDEMOD_LOCK_2 0xf1260002 | 121 | #define F0900_MDEMOD_LOCK_2 0xf1260002 |
| 132 | #define F0900_MDEMOD_IRQ_2 0xf1260001 | 122 | #define F0900_MDEMOD_IRQ_2 0xf1260001 |
| 133 | 123 | ||
| 134 | /*IRQMASK0*/ | 124 | /*IRQMASK0*/ |
| 135 | #define R0900_IRQMASK0 0xf127 | 125 | #define R0900_IRQMASK0 0xf127 |
| 136 | #define F0900_MDEMOD_LOCKB_1 0xf1270080 | 126 | #define F0900_MDEMOD_LOCKB_1 0xf1270080 |
| 137 | #define F0900_MDEMOD_LOCK_1 0xf1270040 | 127 | #define F0900_MDEMOD_LOCK_1 0xf1270040 |
| 138 | #define F0900_MDEMOD_IRQ_1 0xf1270020 | 128 | #define F0900_MDEMOD_IRQ_1 0xf1270020 |
| 139 | #define F0900_MBCH_ERRFLAG 0xf1270010 | 129 | #define F0900_MBCH_ERRFLAG 0xf1270010 |
| 140 | #define F0900_MDISEQC2RX_IRQ 0xf1270008 | 130 | #define F0900_MDISEQC2RX_IRQ 0xf1270008 |
| 141 | #define F0900_MDISEQC2TX_IRQ 0xf1270004 | 131 | #define F0900_MDISEQC2TX_IRQ 0xf1270004 |
| 142 | #define F0900_MDISEQC1RX_IRQ 0xf1270002 | 132 | #define F0900_MDISEQC1RX_IRQ 0xf1270002 |
| 143 | #define F0900_MDISEQC1TX_IRQ 0xf1270001 | 133 | #define F0900_MDISEQC1TX_IRQ 0xf1270001 |
| 144 | 134 | ||
| 145 | /*I2CCFG*/ | 135 | /*I2CCFG*/ |
| 146 | #define R0900_I2CCFG 0xf129 | 136 | #define R0900_I2CCFG 0xf129 |
| 147 | #define F0900_I2C2_FASTMODE 0xf1290080 | 137 | #define F0900_I2C_FASTMODE 0xf1290008 |
| 148 | #define F0900_STATUS_WR2 0xf1290040 | 138 | #define F0900_I2CADDR_INC 0xf1290003 |
| 149 | #define F0900_I2C2ADDR_INC 0xf1290030 | ||
| 150 | #define F0900_I2C_FASTMODE 0xf1290008 | ||
| 151 | #define F0900_STATUS_WR 0xf1290004 | ||
| 152 | #define F0900_I2CADDR_INC 0xf1290003 | ||
| 153 | 139 | ||
| 154 | /*P1_I2CRPT*/ | 140 | /*P1_I2CRPT*/ |
| 155 | #define R0900_P1_I2CRPT 0xf12a | 141 | #define R0900_P1_I2CRPT 0xf12a |
| 156 | #define F0900_P1_I2CT_ON 0xf12a0080 | 142 | #define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1) |
| 157 | #define F0900_P1_ENARPT_LEVEL 0xf12a0070 | 143 | #define F0900_P1_I2CT_ON 0xf12a0080 |
| 158 | #define F0900_P1_SCLT_DELAY 0xf12a0008 | 144 | #define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000) |
| 159 | #define F0900_P1_STOP_ENABLE 0xf12a0004 | 145 | #define F0900_P1_ENARPT_LEVEL 0xf12a0070 |
| 160 | #define F0900_P1_STOP_SDAT2SDA 0xf12a0002 | 146 | #define F0900_P1_SCLT_DELAY 0xf12a0008 |
| 147 | #define F0900_P1_STOP_ENABLE 0xf12a0004 | ||
| 148 | #define F0900_P1_STOP_SDAT2SDA 0xf12a0002 | ||
| 161 | 149 | ||
| 162 | /*P2_I2CRPT*/ | 150 | /*P2_I2CRPT*/ |
| 163 | #define R0900_P2_I2CRPT 0xf12b | 151 | #define R0900_P2_I2CRPT 0xf12b |
| 164 | #define F0900_P2_I2CT_ON 0xf12b0080 | 152 | #define F0900_P2_I2CT_ON 0xf12b0080 |
| 165 | #define F0900_P2_ENARPT_LEVEL 0xf12b0070 | 153 | #define F0900_P2_ENARPT_LEVEL 0xf12b0070 |
| 166 | #define F0900_P2_SCLT_DELAY 0xf12b0008 | 154 | #define F0900_P2_SCLT_DELAY 0xf12b0008 |
| 167 | #define F0900_P2_STOP_ENABLE 0xf12b0004 | 155 | #define F0900_P2_STOP_ENABLE 0xf12b0004 |
| 168 | #define F0900_P2_STOP_SDAT2SDA 0xf12b0002 | 156 | #define F0900_P2_STOP_SDAT2SDA 0xf12b0002 |
| 157 | |||
| 158 | /*IOPVALUE6*/ | ||
| 159 | #define R0900_IOPVALUE6 0xf138 | ||
| 160 | #define F0900_VSCL 0xf1380004 | ||
| 161 | #define F0900_VSDA 0xf1380002 | ||
| 162 | #define F0900_VDATA3_0 0xf1380001 | ||
| 163 | |||
| 164 | /*IOPVALUE5*/ | ||
| 165 | #define R0900_IOPVALUE5 0xf139 | ||
| 166 | #define F0900_VDATA3_1 0xf1390080 | ||
| 167 | #define F0900_VDATA3_2 0xf1390040 | ||
| 168 | #define F0900_VDATA3_3 0xf1390020 | ||
| 169 | #define F0900_VDATA3_4 0xf1390010 | ||
| 170 | #define F0900_VDATA3_5 0xf1390008 | ||
| 171 | #define F0900_VDATA3_6 0xf1390004 | ||
| 172 | #define F0900_VDATA3_7 0xf1390002 | ||
| 173 | #define F0900_VCLKOUT3 0xf1390001 | ||
| 174 | |||
| 175 | /*IOPVALUE4*/ | ||
| 176 | #define R0900_IOPVALUE4 0xf13a | ||
| 177 | #define F0900_VSTROUT3 0xf13a0080 | ||
| 178 | #define F0900_VDPN3 0xf13a0040 | ||
| 179 | #define F0900_VERROR3 0xf13a0020 | ||
| 180 | #define F0900_VDATA2_7 0xf13a0010 | ||
| 181 | #define F0900_VCLKOUT2 0xf13a0008 | ||
| 182 | #define F0900_VSTROUT2 0xf13a0004 | ||
| 183 | #define F0900_VDPN2 0xf13a0002 | ||
| 184 | #define F0900_VERROR2 0xf13a0001 | ||
| 185 | |||
| 186 | /*IOPVALUE3*/ | ||
| 187 | #define R0900_IOPVALUE3 0xf13b | ||
| 188 | #define F0900_VDATA1_7 0xf13b0080 | ||
| 189 | #define F0900_VCLKOUT1 0xf13b0040 | ||
| 190 | #define F0900_VSTROUT1 0xf13b0020 | ||
| 191 | #define F0900_VDPN1 0xf13b0010 | ||
| 192 | #define F0900_VERROR1 0xf13b0008 | ||
| 193 | #define F0900_VCLKOUT27 0xf13b0004 | ||
| 194 | #define F0900_VDISEQCOUT2 0xf13b0002 | ||
| 195 | #define F0900_VSCLT2 0xf13b0001 | ||
| 196 | |||
| 197 | /*IOPVALUE2*/ | ||
| 198 | #define R0900_IOPVALUE2 0xf13c | ||
| 199 | #define F0900_VSDAT2 0xf13c0080 | ||
| 200 | #define F0900_VAGCRF2 0xf13c0040 | ||
| 201 | #define F0900_VDISEQCOUT1 0xf13c0020 | ||
| 202 | #define F0900_VSCLT1 0xf13c0010 | ||
| 203 | #define F0900_VSDAT1 0xf13c0008 | ||
| 204 | #define F0900_VAGCRF1 0xf13c0004 | ||
| 205 | #define F0900_VDIRCLK 0xf13c0002 | ||
| 206 | #define F0900_VSTDBY 0xf13c0001 | ||
| 207 | |||
| 208 | /*IOPVALUE1*/ | ||
| 209 | #define R0900_IOPVALUE1 0xf13d | ||
| 210 | #define F0900_VCS1 0xf13d0080 | ||
| 211 | #define F0900_VCS0 0xf13d0040 | ||
| 212 | #define F0900_VGPIO13 0xf13d0020 | ||
| 213 | #define F0900_VGPIO12 0xf13d0010 | ||
| 214 | #define F0900_VGPIO11 0xf13d0008 | ||
| 215 | #define F0900_VGPIO10 0xf13d0004 | ||
| 216 | #define F0900_VGPIO9 0xf13d0002 | ||
| 217 | #define F0900_VGPIO8 0xf13d0001 | ||
| 218 | |||
| 219 | /*IOPVALUE0*/ | ||
| 220 | #define R0900_IOPVALUE0 0xf13e | ||
| 221 | #define F0900_VGPIO7 0xf13e0080 | ||
| 222 | #define F0900_VGPIO6 0xf13e0040 | ||
| 223 | #define F0900_VGPIO5 0xf13e0020 | ||
| 224 | #define F0900_VGPIO4 0xf13e0010 | ||
| 225 | #define F0900_VGPIO3 0xf13e0008 | ||
| 226 | #define F0900_VGPIO2 0xf13e0004 | ||
| 227 | #define F0900_VGPIO1 0xf13e0002 | ||
| 228 | #define F0900_VCLKI2 0xf13e0001 | ||
| 169 | 229 | ||
| 170 | /*CLKI2CFG*/ | 230 | /*CLKI2CFG*/ |
| 171 | #define R0900_CLKI2CFG 0xf140 | 231 | #define R0900_CLKI2CFG 0xf140 |
| 172 | #define F0900_CLKI2_OPD 0xf1400080 | 232 | #define F0900_CLKI2_OPD 0xf1400080 |
| 173 | #define F0900_CLKI2_CONFIG 0xf140007e | 233 | #define F0900_CLKI2_CONFIG 0xf140007e |
| 174 | #define F0900_CLKI2_XOR 0xf1400001 | 234 | #define F0900_CLKI2_XOR 0xf1400001 |
| 175 | 235 | ||
| 176 | /*GPIO1CFG*/ | 236 | /*GPIO1CFG*/ |
| 177 | #define R0900_GPIO1CFG 0xf141 | 237 | #define R0900_GPIO1CFG 0xf141 |
| 178 | #define F0900_GPIO1_OPD 0xf1410080 | 238 | #define F0900_GPIO1_OPD 0xf1410080 |
| 179 | #define F0900_GPIO1_CONFIG 0xf141007e | 239 | #define F0900_GPIO1_CONFIG 0xf141007e |
| 180 | #define F0900_GPIO1_XOR 0xf1410001 | 240 | #define F0900_GPIO1_XOR 0xf1410001 |
| 181 | 241 | ||
| 182 | /*GPIO2CFG*/ | 242 | /*GPIO2CFG*/ |
| 183 | #define R0900_GPIO2CFG 0xf142 | 243 | #define R0900_GPIO2CFG 0xf142 |
| 184 | #define F0900_GPIO2_OPD 0xf1420080 | 244 | #define F0900_GPIO2_OPD 0xf1420080 |
| 185 | #define F0900_GPIO2_CONFIG 0xf142007e | 245 | #define F0900_GPIO2_CONFIG 0xf142007e |
| 186 | #define F0900_GPIO2_XOR 0xf1420001 | 246 | #define F0900_GPIO2_XOR 0xf1420001 |
| 187 | 247 | ||
| 188 | /*GPIO3CFG*/ | 248 | /*GPIO3CFG*/ |
| 189 | #define R0900_GPIO3CFG 0xf143 | 249 | #define R0900_GPIO3CFG 0xf143 |
| 190 | #define F0900_GPIO3_OPD 0xf1430080 | 250 | #define F0900_GPIO3_OPD 0xf1430080 |
| 191 | #define F0900_GPIO3_CONFIG 0xf143007e | 251 | #define F0900_GPIO3_CONFIG 0xf143007e |
| 192 | #define F0900_GPIO3_XOR 0xf1430001 | 252 | #define F0900_GPIO3_XOR 0xf1430001 |
| 193 | 253 | ||
| 194 | /*GPIO4CFG*/ | 254 | /*GPIO4CFG*/ |
| 195 | #define R0900_GPIO4CFG 0xf144 | 255 | #define R0900_GPIO4CFG 0xf144 |
| 196 | #define F0900_GPIO4_OPD 0xf1440080 | 256 | #define F0900_GPIO4_OPD 0xf1440080 |
| 197 | #define F0900_GPIO4_CONFIG 0xf144007e | 257 | #define F0900_GPIO4_CONFIG 0xf144007e |
| 198 | #define F0900_GPIO4_XOR 0xf1440001 | 258 | #define F0900_GPIO4_XOR 0xf1440001 |
| 199 | 259 | ||
| 200 | /*GPIO5CFG*/ | 260 | /*GPIO5CFG*/ |
| 201 | #define R0900_GPIO5CFG 0xf145 | 261 | #define R0900_GPIO5CFG 0xf145 |
| 202 | #define F0900_GPIO5_OPD 0xf1450080 | 262 | #define F0900_GPIO5_OPD 0xf1450080 |
| 203 | #define F0900_GPIO5_CONFIG 0xf145007e | 263 | #define F0900_GPIO5_CONFIG 0xf145007e |
| 204 | #define F0900_GPIO5_XOR 0xf1450001 | 264 | #define F0900_GPIO5_XOR 0xf1450001 |
| 205 | 265 | ||
| 206 | /*GPIO6CFG*/ | 266 | /*GPIO6CFG*/ |
| 207 | #define R0900_GPIO6CFG 0xf146 | 267 | #define R0900_GPIO6CFG 0xf146 |
| 208 | #define F0900_GPIO6_OPD 0xf1460080 | 268 | #define F0900_GPIO6_OPD 0xf1460080 |
| 209 | #define F0900_GPIO6_CONFIG 0xf146007e | 269 | #define F0900_GPIO6_CONFIG 0xf146007e |
| 210 | #define F0900_GPIO6_XOR 0xf1460001 | 270 | #define F0900_GPIO6_XOR 0xf1460001 |
| 211 | 271 | ||
| 212 | /*GPIO7CFG*/ | 272 | /*GPIO7CFG*/ |
| 213 | #define R0900_GPIO7CFG 0xf147 | 273 | #define R0900_GPIO7CFG 0xf147 |
| 214 | #define F0900_GPIO7_OPD 0xf1470080 | 274 | #define F0900_GPIO7_OPD 0xf1470080 |
| 215 | #define F0900_GPIO7_CONFIG 0xf147007e | 275 | #define F0900_GPIO7_CONFIG 0xf147007e |
| 216 | #define F0900_GPIO7_XOR 0xf1470001 | 276 | #define F0900_GPIO7_XOR 0xf1470001 |
| 217 | 277 | ||
| 218 | /*GPIO8CFG*/ | 278 | /*GPIO8CFG*/ |
| 219 | #define R0900_GPIO8CFG 0xf148 | 279 | #define R0900_GPIO8CFG 0xf148 |
| 220 | #define F0900_GPIO8_OPD 0xf1480080 | 280 | #define F0900_GPIO8_OPD 0xf1480080 |
| 221 | #define F0900_GPIO8_CONFIG 0xf148007e | 281 | #define F0900_GPIO8_CONFIG 0xf148007e |
| 222 | #define F0900_GPIO8_XOR 0xf1480001 | 282 | #define F0900_GPIO8_XOR 0xf1480001 |
| 223 | 283 | ||
| 224 | /*GPIO9CFG*/ | 284 | /*GPIO9CFG*/ |
| 225 | #define R0900_GPIO9CFG 0xf149 | 285 | #define R0900_GPIO9CFG 0xf149 |
| 226 | #define F0900_GPIO9_OPD 0xf1490080 | 286 | #define F0900_GPIO9_OPD 0xf1490080 |
| 227 | #define F0900_GPIO9_CONFIG 0xf149007e | 287 | #define F0900_GPIO9_CONFIG 0xf149007e |
| 228 | #define F0900_GPIO9_XOR 0xf1490001 | 288 | #define F0900_GPIO9_XOR 0xf1490001 |
| 229 | 289 | ||
| 230 | /*GPIO10CFG*/ | 290 | /*GPIO10CFG*/ |
| 231 | #define R0900_GPIO10CFG 0xf14a | 291 | #define R0900_GPIO10CFG 0xf14a |
| 232 | #define F0900_GPIO10_OPD 0xf14a0080 | 292 | #define F0900_GPIO10_OPD 0xf14a0080 |
| 233 | #define F0900_GPIO10_CONFIG 0xf14a007e | 293 | #define F0900_GPIO10_CONFIG 0xf14a007e |
| 234 | #define F0900_GPIO10_XOR 0xf14a0001 | 294 | #define F0900_GPIO10_XOR 0xf14a0001 |
| 235 | 295 | ||
| 236 | /*GPIO11CFG*/ | 296 | /*GPIO11CFG*/ |
| 237 | #define R0900_GPIO11CFG 0xf14b | 297 | #define R0900_GPIO11CFG 0xf14b |
| 238 | #define F0900_GPIO11_OPD 0xf14b0080 | 298 | #define F0900_GPIO11_OPD 0xf14b0080 |
| 239 | #define F0900_GPIO11_CONFIG 0xf14b007e | 299 | #define F0900_GPIO11_CONFIG 0xf14b007e |
| 240 | #define F0900_GPIO11_XOR 0xf14b0001 | 300 | #define F0900_GPIO11_XOR 0xf14b0001 |
| 241 | 301 | ||
| 242 | /*GPIO12CFG*/ | 302 | /*GPIO12CFG*/ |
| 243 | #define R0900_GPIO12CFG 0xf14c | 303 | #define R0900_GPIO12CFG 0xf14c |
| 244 | #define F0900_GPIO12_OPD 0xf14c0080 | 304 | #define F0900_GPIO12_OPD 0xf14c0080 |
| 245 | #define F0900_GPIO12_CONFIG 0xf14c007e | 305 | #define F0900_GPIO12_CONFIG 0xf14c007e |
| 246 | #define F0900_GPIO12_XOR 0xf14c0001 | 306 | #define F0900_GPIO12_XOR 0xf14c0001 |
| 247 | 307 | ||
| 248 | /*GPIO13CFG*/ | 308 | /*GPIO13CFG*/ |
| 249 | #define R0900_GPIO13CFG 0xf14d | 309 | #define R0900_GPIO13CFG 0xf14d |
| 250 | #define F0900_GPIO13_OPD 0xf14d0080 | 310 | #define F0900_GPIO13_OPD 0xf14d0080 |
| 251 | #define F0900_GPIO13_CONFIG 0xf14d007e | 311 | #define F0900_GPIO13_CONFIG 0xf14d007e |
| 252 | #define F0900_GPIO13_XOR 0xf14d0001 | 312 | #define F0900_GPIO13_XOR 0xf14d0001 |
| 253 | 313 | ||
| 254 | /*CS0CFG*/ | 314 | /*CS0CFG*/ |
| 255 | #define R0900_CS0CFG 0xf14e | 315 | #define R0900_CS0CFG 0xf14e |
| 256 | #define F0900_CS0_OPD 0xf14e0080 | 316 | #define F0900_CS0_OPD 0xf14e0080 |
| 257 | #define F0900_CS0_CONFIG 0xf14e007e | 317 | #define F0900_CS0_CONFIG 0xf14e007e |
| 258 | #define F0900_CS0_XOR 0xf14e0001 | 318 | #define F0900_CS0_XOR 0xf14e0001 |
| 259 | 319 | ||
| 260 | /*CS1CFG*/ | 320 | /*CS1CFG*/ |
| 261 | #define R0900_CS1CFG 0xf14f | 321 | #define R0900_CS1CFG 0xf14f |
| 262 | #define F0900_CS1_OPD 0xf14f0080 | 322 | #define F0900_CS1_OPD 0xf14f0080 |
| 263 | #define F0900_CS1_CONFIG 0xf14f007e | 323 | #define F0900_CS1_CONFIG 0xf14f007e |
| 264 | #define F0900_CS1_XOR 0xf14f0001 | 324 | #define F0900_CS1_XOR 0xf14f0001 |
| 265 | 325 | ||
| 266 | /*STDBYCFG*/ | 326 | /*STDBYCFG*/ |
| 267 | #define R0900_STDBYCFG 0xf150 | 327 | #define R0900_STDBYCFG 0xf150 |
| 268 | #define F0900_STDBY_OPD 0xf1500080 | 328 | #define F0900_STDBY_OPD 0xf1500080 |
| 269 | #define F0900_STDBY_CONFIG 0xf150007e | 329 | #define F0900_STDBY_CONFIG 0xf150007e |
| 270 | #define F0900_STBDY_XOR 0xf1500001 | 330 | #define F0900_STBDY_XOR 0xf1500001 |
| 271 | 331 | ||
| 272 | /*DIRCLKCFG*/ | 332 | /*DIRCLKCFG*/ |
| 273 | #define R0900_DIRCLKCFG 0xf151 | 333 | #define R0900_DIRCLKCFG 0xf151 |
| 274 | #define F0900_DIRCLK_OPD 0xf1510080 | 334 | #define F0900_DIRCLK_OPD 0xf1510080 |
| 275 | #define F0900_DIRCLK_CONFIG 0xf151007e | 335 | #define F0900_DIRCLK_CONFIG 0xf151007e |
| 276 | #define F0900_DIRCLK_XOR 0xf1510001 | 336 | #define F0900_DIRCLK_XOR 0xf1510001 |
| 277 | 337 | ||
| 278 | /*AGCRF1CFG*/ | 338 | /*AGCRF1CFG*/ |
| 279 | #define R0900_AGCRF1CFG 0xf152 | 339 | #define R0900_AGCRF1CFG 0xf152 |
| 280 | #define F0900_AGCRF1_OPD 0xf1520080 | 340 | #define F0900_AGCRF1_OPD 0xf1520080 |
| 281 | #define F0900_AGCRF1_CONFIG 0xf152007e | 341 | #define F0900_AGCRF1_CONFIG 0xf152007e |
| 282 | #define F0900_AGCRF1_XOR 0xf1520001 | 342 | #define F0900_AGCRF1_XOR 0xf1520001 |
| 283 | 343 | ||
| 284 | /*SDAT1CFG*/ | 344 | /*SDAT1CFG*/ |
| 285 | #define R0900_SDAT1CFG 0xf153 | 345 | #define R0900_SDAT1CFG 0xf153 |
| 286 | #define F0900_SDAT1_OPD 0xf1530080 | 346 | #define F0900_SDAT1_OPD 0xf1530080 |
| 287 | #define F0900_SDAT1_CONFIG 0xf153007e | 347 | #define F0900_SDAT1_CONFIG 0xf153007e |
| 288 | #define F0900_SDAT1_XOR 0xf1530001 | 348 | #define F0900_SDAT1_XOR 0xf1530001 |
| 289 | 349 | ||
| 290 | /*SCLT1CFG*/ | 350 | /*SCLT1CFG*/ |
| 291 | #define R0900_SCLT1CFG 0xf154 | 351 | #define R0900_SCLT1CFG 0xf154 |
| 292 | #define F0900_SCLT1_OPD 0xf1540080 | 352 | #define F0900_SCLT1_OPD 0xf1540080 |
| 293 | #define F0900_SCLT1_CONFIG 0xf154007e | 353 | #define F0900_SCLT1_CONFIG 0xf154007e |
| 294 | #define F0900_SCLT1_XOR 0xf1540001 | 354 | #define F0900_SCLT1_XOR 0xf1540001 |
| 295 | 355 | ||
| 296 | /*DISEQCO1CFG*/ | 356 | /*DISEQCO1CFG*/ |
| 297 | #define R0900_DISEQCO1CFG 0xf155 | 357 | #define R0900_DISEQCO1CFG 0xf155 |
| 298 | #define F0900_DISEQCO1_OPD 0xf1550080 | 358 | #define F0900_DISEQCO1_OPD 0xf1550080 |
| 299 | #define F0900_DISEQCO1_CONFIG 0xf155007e | 359 | #define F0900_DISEQCO1_CONFIG 0xf155007e |
| 300 | #define F0900_DISEQC1_XOR 0xf1550001 | 360 | #define F0900_DISEQC1_XOR 0xf1550001 |
| 301 | 361 | ||
| 302 | /*AGCRF2CFG*/ | 362 | /*AGCRF2CFG*/ |
| 303 | #define R0900_AGCRF2CFG 0xf156 | 363 | #define R0900_AGCRF2CFG 0xf156 |
| 304 | #define F0900_AGCRF2_OPD 0xf1560080 | 364 | #define F0900_AGCRF2_OPD 0xf1560080 |
| 305 | #define F0900_AGCRF2_CONFIG 0xf156007e | 365 | #define F0900_AGCRF2_CONFIG 0xf156007e |
| 306 | #define F0900_AGCRF2_XOR 0xf1560001 | 366 | #define F0900_AGCRF2_XOR 0xf1560001 |
| 307 | 367 | ||
| 308 | /*SDAT2CFG*/ | 368 | /*SDAT2CFG*/ |
| 309 | #define R0900_SDAT2CFG 0xf157 | 369 | #define R0900_SDAT2CFG 0xf157 |
| 310 | #define F0900_SDAT2_OPD 0xf1570080 | 370 | #define F0900_SDAT2_OPD 0xf1570080 |
| 311 | #define F0900_SDAT2_CONFIG 0xf157007e | 371 | #define F0900_SDAT2_CONFIG 0xf157007e |
| 312 | #define F0900_SDAT2_XOR 0xf1570001 | 372 | #define F0900_SDAT2_XOR 0xf1570001 |
| 313 | 373 | ||
| 314 | /*SCLT2CFG*/ | 374 | /*SCLT2CFG*/ |
| 315 | #define R0900_SCLT2CFG 0xf158 | 375 | #define R0900_SCLT2CFG 0xf158 |
| 316 | #define F0900_SCLT2_OPD 0xf1580080 | 376 | #define F0900_SCLT2_OPD 0xf1580080 |
| 317 | #define F0900_SCLT2_CONFIG 0xf158007e | 377 | #define F0900_SCLT2_CONFIG 0xf158007e |
| 318 | #define F0900_SCLT2_XOR 0xf1580001 | 378 | #define F0900_SCLT2_XOR 0xf1580001 |
| 319 | 379 | ||
| 320 | /*DISEQCO2CFG*/ | 380 | /*DISEQCO2CFG*/ |
| 321 | #define R0900_DISEQCO2CFG 0xf159 | 381 | #define R0900_DISEQCO2CFG 0xf159 |
| 322 | #define F0900_DISEQCO2_OPD 0xf1590080 | 382 | #define F0900_DISEQCO2_OPD 0xf1590080 |
| 323 | #define F0900_DISEQCO2_CONFIG 0xf159007e | 383 | #define F0900_DISEQCO2_CONFIG 0xf159007e |
| 324 | #define F0900_DISEQC2_XOR 0xf1590001 | 384 | #define F0900_DISEQC2_XOR 0xf1590001 |
| 325 | 385 | ||
| 326 | /*CLKOUT27CFG*/ | 386 | /*CLKOUT27CFG*/ |
| 327 | #define R0900_CLKOUT27CFG 0xf15a | 387 | #define R0900_CLKOUT27CFG 0xf15a |
| 328 | #define F0900_CLKOUT27_OPD 0xf15a0080 | 388 | #define F0900_CLKOUT27_OPD 0xf15a0080 |
| 329 | #define F0900_CLKOUT27_CONFIG 0xf15a007e | 389 | #define F0900_CLKOUT27_CONFIG 0xf15a007e |
| 330 | #define F0900_CLKOUT27_XOR 0xf15a0001 | 390 | #define F0900_CLKOUT27_XOR 0xf15a0001 |
| 331 | 391 | ||
| 332 | /*ERROR1CFG*/ | 392 | /*ERROR1CFG*/ |
| 333 | #define R0900_ERROR1CFG 0xf15b | 393 | #define R0900_ERROR1CFG 0xf15b |
| 334 | #define F0900_ERROR1_OPD 0xf15b0080 | 394 | #define F0900_ERROR1_OPD 0xf15b0080 |
| 335 | #define F0900_ERROR1_CONFIG 0xf15b007e | 395 | #define F0900_ERROR1_CONFIG 0xf15b007e |
| 336 | #define F0900_ERROR1_XOR 0xf15b0001 | 396 | #define F0900_ERROR1_XOR 0xf15b0001 |
| 337 | 397 | ||
| 338 | /*DPN1CFG*/ | 398 | /*DPN1CFG*/ |
| 339 | #define R0900_DPN1CFG 0xf15c | 399 | #define R0900_DPN1CFG 0xf15c |
| 340 | #define F0900_DPN1_OPD 0xf15c0080 | 400 | #define F0900_DPN1_OPD 0xf15c0080 |
| 341 | #define F0900_DPN1_CONFIG 0xf15c007e | 401 | #define F0900_DPN1_CONFIG 0xf15c007e |
| 342 | #define F0900_DPN1_XOR 0xf15c0001 | 402 | #define F0900_DPN1_XOR 0xf15c0001 |
| 343 | 403 | ||
| 344 | /*STROUT1CFG*/ | 404 | /*STROUT1CFG*/ |
| 345 | #define R0900_STROUT1CFG 0xf15d | 405 | #define R0900_STROUT1CFG 0xf15d |
| 346 | #define F0900_STROUT1_OPD 0xf15d0080 | 406 | #define F0900_STROUT1_OPD 0xf15d0080 |
| 347 | #define F0900_STROUT1_CONFIG 0xf15d007e | 407 | #define F0900_STROUT1_CONFIG 0xf15d007e |
| 348 | #define F0900_STROUT1_XOR 0xf15d0001 | 408 | #define F0900_STROUT1_XOR 0xf15d0001 |
| 349 | 409 | ||
| 350 | /*CLKOUT1CFG*/ | 410 | /*CLKOUT1CFG*/ |
| 351 | #define R0900_CLKOUT1CFG 0xf15e | 411 | #define R0900_CLKOUT1CFG 0xf15e |
| 352 | #define F0900_CLKOUT1_OPD 0xf15e0080 | 412 | #define F0900_CLKOUT1_OPD 0xf15e0080 |
| 353 | #define F0900_CLKOUT1_CONFIG 0xf15e007e | 413 | #define F0900_CLKOUT1_CONFIG 0xf15e007e |
| 354 | #define F0900_CLKOUT1_XOR 0xf15e0001 | 414 | #define F0900_CLKOUT1_XOR 0xf15e0001 |
| 355 | 415 | ||
| 356 | /*DATA71CFG*/ | 416 | /*DATA71CFG*/ |
| 357 | #define R0900_DATA71CFG 0xf15f | 417 | #define R0900_DATA71CFG 0xf15f |
| 358 | #define F0900_DATA71_OPD 0xf15f0080 | 418 | #define F0900_DATA71_OPD 0xf15f0080 |
| 359 | #define F0900_DATA71_CONFIG 0xf15f007e | 419 | #define F0900_DATA71_CONFIG 0xf15f007e |
| 360 | #define F0900_DATA71_XOR 0xf15f0001 | 420 | #define F0900_DATA71_XOR 0xf15f0001 |
| 361 | 421 | ||
| 362 | /*ERROR2CFG*/ | 422 | /*ERROR2CFG*/ |
| 363 | #define R0900_ERROR2CFG 0xf160 | 423 | #define R0900_ERROR2CFG 0xf160 |
| 364 | #define F0900_ERROR2_OPD 0xf1600080 | 424 | #define F0900_ERROR2_OPD 0xf1600080 |
| 365 | #define F0900_ERROR2_CONFIG 0xf160007e | 425 | #define F0900_ERROR2_CONFIG 0xf160007e |
| 366 | #define F0900_ERROR2_XOR 0xf1600001 | 426 | #define F0900_ERROR2_XOR 0xf1600001 |
| 367 | 427 | ||
| 368 | /*DPN2CFG*/ | 428 | /*DPN2CFG*/ |
| 369 | #define R0900_DPN2CFG 0xf161 | 429 | #define R0900_DPN2CFG 0xf161 |
| 370 | #define F0900_DPN2_OPD 0xf1610080 | 430 | #define F0900_DPN2_OPD 0xf1610080 |
| 371 | #define F0900_DPN2_CONFIG 0xf161007e | 431 | #define F0900_DPN2_CONFIG 0xf161007e |
| 372 | #define F0900_DPN2_XOR 0xf1610001 | 432 | #define F0900_DPN2_XOR 0xf1610001 |
| 373 | 433 | ||
| 374 | /*STROUT2CFG*/ | 434 | /*STROUT2CFG*/ |
| 375 | #define R0900_STROUT2CFG 0xf162 | 435 | #define R0900_STROUT2CFG 0xf162 |
| 376 | #define F0900_STROUT2_OPD 0xf1620080 | 436 | #define F0900_STROUT2_OPD 0xf1620080 |
| 377 | #define F0900_STROUT2_CONFIG 0xf162007e | 437 | #define F0900_STROUT2_CONFIG 0xf162007e |
| 378 | #define F0900_STROUT2_XOR 0xf1620001 | 438 | #define F0900_STROUT2_XOR 0xf1620001 |
| 379 | 439 | ||
| 380 | /*CLKOUT2CFG*/ | 440 | /*CLKOUT2CFG*/ |
| 381 | #define R0900_CLKOUT2CFG 0xf163 | 441 | #define R0900_CLKOUT2CFG 0xf163 |
| 382 | #define F0900_CLKOUT2_OPD 0xf1630080 | 442 | #define F0900_CLKOUT2_OPD 0xf1630080 |
| 383 | #define F0900_CLKOUT2_CONFIG 0xf163007e | 443 | #define F0900_CLKOUT2_CONFIG 0xf163007e |
| 384 | #define F0900_CLKOUT2_XOR 0xf1630001 | 444 | #define F0900_CLKOUT2_XOR 0xf1630001 |
| 385 | 445 | ||
| 386 | /*DATA72CFG*/ | 446 | /*DATA72CFG*/ |
| 387 | #define R0900_DATA72CFG 0xf164 | 447 | #define R0900_DATA72CFG 0xf164 |
| 388 | #define F0900_DATA72_OPD 0xf1640080 | 448 | #define F0900_DATA72_OPD 0xf1640080 |
| 389 | #define F0900_DATA72_CONFIG 0xf164007e | 449 | #define F0900_DATA72_CONFIG 0xf164007e |
| 390 | #define F0900_DATA72_XOR 0xf1640001 | 450 | #define F0900_DATA72_XOR 0xf1640001 |
| 391 | 451 | ||
| 392 | /*ERROR3CFG*/ | 452 | /*ERROR3CFG*/ |
| 393 | #define R0900_ERROR3CFG 0xf165 | 453 | #define R0900_ERROR3CFG 0xf165 |
| 394 | #define F0900_ERROR3_OPD 0xf1650080 | 454 | #define F0900_ERROR3_OPD 0xf1650080 |
| 395 | #define F0900_ERROR3_CONFIG 0xf165007e | 455 | #define F0900_ERROR3_CONFIG 0xf165007e |
| 396 | #define F0900_ERROR3_XOR 0xf1650001 | 456 | #define F0900_ERROR3_XOR 0xf1650001 |
| 397 | 457 | ||
| 398 | /*DPN3CFG*/ | 458 | /*DPN3CFG*/ |
| 399 | #define R0900_DPN3CFG 0xf166 | 459 | #define R0900_DPN3CFG 0xf166 |
| 400 | #define F0900_DPN3_OPD 0xf1660080 | 460 | #define F0900_DPN3_OPD 0xf1660080 |
| 401 | #define F0900_DPN3_CONFIG 0xf166007e | 461 | #define F0900_DPN3_CONFIG 0xf166007e |
| 402 | #define F0900_DPN3_XOR 0xf1660001 | 462 | #define F0900_DPN3_XOR 0xf1660001 |
| 403 | 463 | ||
| 404 | /*STROUT3CFG*/ | 464 | /*STROUT3CFG*/ |
| 405 | #define R0900_STROUT3CFG 0xf167 | 465 | #define R0900_STROUT3CFG 0xf167 |
| 406 | #define F0900_STROUT3_OPD 0xf1670080 | 466 | #define F0900_STROUT3_OPD 0xf1670080 |
| 407 | #define F0900_STROUT3_CONFIG 0xf167007e | 467 | #define F0900_STROUT3_CONFIG 0xf167007e |
| 408 | #define F0900_STROUT3_XOR 0xf1670001 | 468 | #define F0900_STROUT3_XOR 0xf1670001 |
| 409 | 469 | ||
| 410 | /*CLKOUT3CFG*/ | 470 | /*CLKOUT3CFG*/ |
| 411 | #define R0900_CLKOUT3CFG 0xf168 | 471 | #define R0900_CLKOUT3CFG 0xf168 |
| 412 | #define F0900_CLKOUT3_OPD 0xf1680080 | 472 | #define F0900_CLKOUT3_OPD 0xf1680080 |
| 413 | #define F0900_CLKOUT3_CONFIG 0xf168007e | 473 | #define F0900_CLKOUT3_CONFIG 0xf168007e |
| 414 | #define F0900_CLKOUT3_XOR 0xf1680001 | 474 | #define F0900_CLKOUT3_XOR 0xf1680001 |
| 415 | 475 | ||
| 416 | /*DATA73CFG*/ | 476 | /*DATA73CFG*/ |
| 417 | #define R0900_DATA73CFG 0xf169 | 477 | #define R0900_DATA73CFG 0xf169 |
| 418 | #define F0900_DATA73_OPD 0xf1690080 | 478 | #define F0900_DATA73_OPD 0xf1690080 |
| 419 | #define F0900_DATA73_CONFIG 0xf169007e | 479 | #define F0900_DATA73_CONFIG 0xf169007e |
| 420 | #define F0900_DATA73_XOR 0xf1690001 | 480 | #define F0900_DATA73_XOR 0xf1690001 |
| 481 | |||
| 482 | /*STRSTATUS1*/ | ||
| 483 | #define R0900_STRSTATUS1 0xf16a | ||
| 484 | #define F0900_STRSTATUS_SEL2 0xf16a00f0 | ||
| 485 | #define F0900_STRSTATUS_SEL1 0xf16a000f | ||
| 486 | |||
| 487 | /*STRSTATUS2*/ | ||
| 488 | #define R0900_STRSTATUS2 0xf16b | ||
| 489 | #define F0900_STRSTATUS_SEL4 0xf16b00f0 | ||
| 490 | #define F0900_STRSTATUS_SEL3 0xf16b000f | ||
| 491 | |||
| 492 | /*STRSTATUS3*/ | ||
| 493 | #define R0900_STRSTATUS3 0xf16c | ||
| 494 | #define F0900_STRSTATUS_SEL6 0xf16c00f0 | ||
| 495 | #define F0900_STRSTATUS_SEL5 0xf16c000f | ||
| 421 | 496 | ||
| 422 | /*FSKTFC2*/ | 497 | /*FSKTFC2*/ |
| 423 | #define R0900_FSKTFC2 0xf170 | 498 | #define R0900_FSKTFC2 0xf170 |
| 424 | #define F0900_FSKT_KMOD 0xf17000fc | 499 | #define F0900_FSKT_KMOD 0xf17000fc |
| 425 | #define F0900_FSKT_CAR2 0xf1700003 | 500 | #define F0900_FSKT_CAR2 0xf1700003 |
| 426 | 501 | ||
| 427 | /*FSKTFC1*/ | 502 | /*FSKTFC1*/ |
| 428 | #define R0900_FSKTFC1 0xf171 | 503 | #define R0900_FSKTFC1 0xf171 |
| 429 | #define F0900_FSKT_CAR1 0xf17100ff | 504 | #define F0900_FSKT_CAR1 0xf17100ff |
| 430 | 505 | ||
| 431 | /*FSKTFC0*/ | 506 | /*FSKTFC0*/ |
| 432 | #define R0900_FSKTFC0 0xf172 | 507 | #define R0900_FSKTFC0 0xf172 |
| 433 | #define F0900_FSKT_CAR0 0xf17200ff | 508 | #define F0900_FSKT_CAR0 0xf17200ff |
| 434 | 509 | ||
| 435 | /*FSKTDELTAF1*/ | 510 | /*FSKTDELTAF1*/ |
| 436 | #define R0900_FSKTDELTAF1 0xf173 | 511 | #define R0900_FSKTDELTAF1 0xf173 |
| 437 | #define F0900_FSKT_DELTAF1 0xf173000f | 512 | #define F0900_FSKT_DELTAF1 0xf173000f |
| 438 | 513 | ||
| 439 | /*FSKTDELTAF0*/ | 514 | /*FSKTDELTAF0*/ |
| 440 | #define R0900_FSKTDELTAF0 0xf174 | 515 | #define R0900_FSKTDELTAF0 0xf174 |
| 441 | #define F0900_FSKT_DELTAF0 0xf17400ff | 516 | #define F0900_FSKT_DELTAF0 0xf17400ff |
| 442 | 517 | ||
| 443 | /*FSKTCTRL*/ | 518 | /*FSKTCTRL*/ |
| 444 | #define R0900_FSKTCTRL 0xf175 | 519 | #define R0900_FSKTCTRL 0xf175 |
| 445 | #define F0900_FSKT_EN_SGN 0xf1750040 | 520 | #define F0900_FSKT_EN_SGN 0xf1750040 |
| 446 | #define F0900_FSKT_MOD_SGN 0xf1750020 | 521 | #define F0900_FSKT_MOD_SGN 0xf1750020 |
| 447 | #define F0900_FSKT_MOD_EN 0xf175001c | 522 | #define F0900_FSKT_MOD_EN 0xf175001c |
| 448 | #define F0900_FSKT_DACMODE 0xf1750003 | 523 | #define F0900_FSKT_DACMODE 0xf1750003 |
| 449 | 524 | ||
| 450 | /*FSKRFC2*/ | 525 | /*FSKRFC2*/ |
| 451 | #define R0900_FSKRFC2 0xf176 | 526 | #define R0900_FSKRFC2 0xf176 |
| 452 | #define F0900_FSKR_DETSGN 0xf1760040 | 527 | #define F0900_FSKR_DETSGN 0xf1760040 |
| 453 | #define F0900_FSKR_OUTSGN 0xf1760020 | 528 | #define F0900_FSKR_OUTSGN 0xf1760020 |
| 454 | #define F0900_FSKR_KAGC 0xf176001c | 529 | #define F0900_FSKR_KAGC 0xf176001c |
| 455 | #define F0900_FSKR_CAR2 0xf1760003 | 530 | #define F0900_FSKR_CAR2 0xf1760003 |
| 456 | 531 | ||
| 457 | /*FSKRFC1*/ | 532 | /*FSKRFC1*/ |
| 458 | #define R0900_FSKRFC1 0xf177 | 533 | #define R0900_FSKRFC1 0xf177 |
| 459 | #define F0900_FSKR_CAR1 0xf17700ff | 534 | #define F0900_FSKR_CAR1 0xf17700ff |
| 460 | 535 | ||
| 461 | /*FSKRFC0*/ | 536 | /*FSKRFC0*/ |
| 462 | #define R0900_FSKRFC0 0xf178 | 537 | #define R0900_FSKRFC0 0xf178 |
| 463 | #define F0900_FSKR_CAR0 0xf17800ff | 538 | #define F0900_FSKR_CAR0 0xf17800ff |
| 464 | 539 | ||
| 465 | /*FSKRK1*/ | 540 | /*FSKRK1*/ |
| 466 | #define R0900_FSKRK1 0xf179 | 541 | #define R0900_FSKRK1 0xf179 |
| 467 | #define F0900_FSKR_K1_EXP 0xf17900e0 | 542 | #define F0900_FSKR_K1_EXP 0xf17900e0 |
| 468 | #define F0900_FSKR_K1_MANT 0xf179001f | 543 | #define F0900_FSKR_K1_MANT 0xf179001f |
| 469 | 544 | ||
| 470 | /*FSKRK2*/ | 545 | /*FSKRK2*/ |
| 471 | #define R0900_FSKRK2 0xf17a | 546 | #define R0900_FSKRK2 0xf17a |
| 472 | #define F0900_FSKR_K2_EXP 0xf17a00e0 | 547 | #define F0900_FSKR_K2_EXP 0xf17a00e0 |
| 473 | #define F0900_FSKR_K2_MANT 0xf17a001f | 548 | #define F0900_FSKR_K2_MANT 0xf17a001f |
| 474 | 549 | ||
| 475 | /*FSKRAGCR*/ | 550 | /*FSKRAGCR*/ |
| 476 | #define R0900_FSKRAGCR 0xf17b | 551 | #define R0900_FSKRAGCR 0xf17b |
| 477 | #define F0900_FSKR_OUTCTL 0xf17b00c0 | 552 | #define F0900_FSKR_OUTCTL 0xf17b00c0 |
| 478 | #define F0900_FSKR_AGC_REF 0xf17b003f | 553 | #define F0900_FSKR_AGC_REF 0xf17b003f |
| 479 | 554 | ||
| 480 | /*FSKRAGC*/ | 555 | /*FSKRAGC*/ |
| 481 | #define R0900_FSKRAGC 0xf17c | 556 | #define R0900_FSKRAGC 0xf17c |
| 482 | #define F0900_FSKR_AGC_ACCU 0xf17c00ff | 557 | #define F0900_FSKR_AGC_ACCU 0xf17c00ff |
| 483 | 558 | ||
| 484 | /*FSKRALPHA*/ | 559 | /*FSKRALPHA*/ |
| 485 | #define R0900_FSKRALPHA 0xf17d | 560 | #define R0900_FSKRALPHA 0xf17d |
| 486 | #define F0900_FSKR_ALPHA_EXP 0xf17d001c | 561 | #define F0900_FSKR_ALPHA_EXP 0xf17d001c |
| 487 | #define F0900_FSKR_ALPHA_M 0xf17d0003 | 562 | #define F0900_FSKR_ALPHA_M 0xf17d0003 |
| 488 | 563 | ||
| 489 | /*FSKRPLTH1*/ | 564 | /*FSKRPLTH1*/ |
| 490 | #define R0900_FSKRPLTH1 0xf17e | 565 | #define R0900_FSKRPLTH1 0xf17e |
| 491 | #define F0900_FSKR_BETA 0xf17e00f0 | 566 | #define F0900_FSKR_BETA 0xf17e00f0 |
| 492 | #define F0900_FSKR_PLL_TRESH1 0xf17e000f | 567 | #define F0900_FSKR_PLL_TRESH1 0xf17e000f |
| 493 | 568 | ||
| 494 | /*FSKRPLTH0*/ | 569 | /*FSKRPLTH0*/ |
| 495 | #define R0900_FSKRPLTH0 0xf17f | 570 | #define R0900_FSKRPLTH0 0xf17f |
| 496 | #define F0900_FSKR_PLL_TRESH0 0xf17f00ff | 571 | #define F0900_FSKR_PLL_TRESH0 0xf17f00ff |
| 497 | 572 | ||
| 498 | /*FSKRDF1*/ | 573 | /*FSKRDF1*/ |
| 499 | #define R0900_FSKRDF1 0xf180 | 574 | #define R0900_FSKRDF1 0xf180 |
| 500 | #define F0900_FSKR_OUT 0xf1800080 | 575 | #define F0900_FSKR_OUT 0xf1800080 |
| 501 | #define F0900_FSKR_DELTAF1 0xf180001f | 576 | #define F0900_FSKR_DELTAF1 0xf180001f |
| 502 | 577 | ||
| 503 | /*FSKRDF0*/ | 578 | /*FSKRDF0*/ |
| 504 | #define R0900_FSKRDF0 0xf181 | 579 | #define R0900_FSKRDF0 0xf181 |
| 505 | #define F0900_FSKR_DELTAF0 0xf18100ff | 580 | #define F0900_FSKR_DELTAF0 0xf18100ff |
| 506 | 581 | ||
| 507 | /*FSKRSTEPP*/ | 582 | /*FSKRSTEPP*/ |
| 508 | #define R0900_FSKRSTEPP 0xf182 | 583 | #define R0900_FSKRSTEPP 0xf182 |
| 509 | #define F0900_FSKR_STEP_PLUS 0xf18200ff | 584 | #define F0900_FSKR_STEP_PLUS 0xf18200ff |
| 510 | 585 | ||
| 511 | /*FSKRSTEPM*/ | 586 | /*FSKRSTEPM*/ |
| 512 | #define R0900_FSKRSTEPM 0xf183 | 587 | #define R0900_FSKRSTEPM 0xf183 |
| 513 | #define F0900_FSKR_STEP_MINUS 0xf18300ff | 588 | #define F0900_FSKR_STEP_MINUS 0xf18300ff |
| 514 | 589 | ||
| 515 | /*FSKRDET1*/ | 590 | /*FSKRDET1*/ |
| 516 | #define R0900_FSKRDET1 0xf184 | 591 | #define R0900_FSKRDET1 0xf184 |
| 517 | #define F0900_FSKR_DETECT 0xf1840080 | 592 | #define F0900_FSKR_DETECT 0xf1840080 |
| 518 | #define F0900_FSKR_CARDET_ACCU1 0xf184000f | 593 | #define F0900_FSKR_CARDET_ACCU1 0xf184000f |
| 519 | 594 | ||
| 520 | /*FSKRDET0*/ | 595 | /*FSKRDET0*/ |
| 521 | #define R0900_FSKRDET0 0xf185 | 596 | #define R0900_FSKRDET0 0xf185 |
| 522 | #define F0900_FSKR_CARDET_ACCU0 0xf18500ff | 597 | #define F0900_FSKR_CARDET_ACCU0 0xf18500ff |
| 523 | 598 | ||
| 524 | /*FSKRDTH1*/ | 599 | /*FSKRDTH1*/ |
| 525 | #define R0900_FSKRDTH1 0xf186 | 600 | #define R0900_FSKRDTH1 0xf186 |
| 526 | #define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0 | 601 | #define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0 |
| 527 | #define F0900_FSKR_CARDET_THRESH1 0xf186000f | 602 | #define F0900_FSKR_CARDET_THRESH1 0xf186000f |
| 528 | 603 | ||
| 529 | /*FSKRDTH0*/ | 604 | /*FSKRDTH0*/ |
| 530 | #define R0900_FSKRDTH0 0xf187 | 605 | #define R0900_FSKRDTH0 0xf187 |
| 531 | #define F0900_FSKR_CARDET_THRESH0 0xf18700ff | 606 | #define F0900_FSKR_CARDET_THRESH0 0xf18700ff |
| 532 | 607 | ||
| 533 | /*FSKRLOSS*/ | 608 | /*FSKRLOSS*/ |
| 534 | #define R0900_FSKRLOSS 0xf188 | 609 | #define R0900_FSKRLOSS 0xf188 |
| 535 | #define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff | 610 | #define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff |
| 536 | 611 | ||
| 537 | /*P2_DISTXCTL*/ | 612 | /*P2_DISTXCTL*/ |
| 538 | #define R0900_P2_DISTXCTL 0xf190 | 613 | #define R0900_P2_DISTXCTL 0xf190 |
| 539 | #define F0900_P2_TIM_OFF 0xf1900080 | 614 | #define F0900_P2_TIM_OFF 0xf1900080 |
| 540 | #define F0900_P2_DISEQC_RESET 0xf1900040 | 615 | #define F0900_P2_DISEQC_RESET 0xf1900040 |
| 541 | #define F0900_P2_TIM_CMD 0xf1900030 | 616 | #define F0900_P2_TIM_CMD 0xf1900030 |
| 542 | #define F0900_P2_DIS_PRECHARGE 0xf1900008 | 617 | #define F0900_P2_DIS_PRECHARGE 0xf1900008 |
| 543 | #define F0900_P2_DISTX_MODE 0xf1900007 | 618 | #define F0900_P2_DISTX_MODE 0xf1900007 |
| 544 | 619 | ||
| 545 | /*P2_DISRXCTL*/ | 620 | /*P2_DISRXCTL*/ |
| 546 | #define R0900_P2_DISRXCTL 0xf191 | 621 | #define R0900_P2_DISRXCTL 0xf191 |
| 547 | #define F0900_P2_RECEIVER_ON 0xf1910080 | 622 | #define F0900_P2_RECEIVER_ON 0xf1910080 |
| 548 | #define F0900_P2_IGNO_SHORT22K 0xf1910040 | 623 | #define F0900_P2_IGNO_SHORT22K 0xf1910040 |
| 549 | #define F0900_P2_ONECHIP_TRX 0xf1910020 | 624 | #define F0900_P2_ONECHIP_TRX 0xf1910020 |
| 550 | #define F0900_P2_EXT_ENVELOP 0xf1910010 | 625 | #define F0900_P2_EXT_ENVELOP 0xf1910010 |
| 551 | #define F0900_P2_PIN_SELECT 0xf191000c | 626 | #define F0900_P2_PIN_SELECT0 0xf191000c |
| 552 | #define F0900_P2_IRQ_RXEND 0xf1910002 | 627 | #define F0900_P2_IRQ_RXEND 0xf1910002 |
| 553 | #define F0900_P2_IRQ_4NBYTES 0xf1910001 | 628 | #define F0900_P2_IRQ_4NBYTES 0xf1910001 |
| 554 | 629 | ||
| 555 | /*P2_DISRX_ST0*/ | 630 | /*P2_DISRX_ST0*/ |
| 556 | #define R0900_P2_DISRX_ST0 0xf194 | 631 | #define R0900_P2_DISRX_ST0 0xf194 |
| 557 | #define F0900_P2_RX_END 0xf1940080 | 632 | #define F0900_P2_RX_END 0xf1940080 |
| 558 | #define F0900_P2_RX_ACTIVE 0xf1940040 | 633 | #define F0900_P2_RX_ACTIVE 0xf1940040 |
| 559 | #define F0900_P2_SHORT_22KHZ 0xf1940020 | 634 | #define F0900_P2_SHORT_22KHZ 0xf1940020 |
| 560 | #define F0900_P2_CONT_TONE 0xf1940010 | 635 | #define F0900_P2_CONT_TONE 0xf1940010 |
| 561 | #define F0900_P2_FIFO_4BREADY 0xf1940008 | 636 | #define F0900_P2_FIFO_4BREADY 0xf1940008 |
| 562 | #define F0900_P2_FIFO_EMPTY 0xf1940004 | 637 | #define F0900_P2_FIFO_EMPTY 0xf1940004 |
| 563 | #define F0900_P2_ABORT_DISRX 0xf1940001 | 638 | #define F0900_P2_ABORT_DISRX 0xf1940001 |
| 564 | 639 | ||
| 565 | /*P2_DISRX_ST1*/ | 640 | /*P2_DISRX_ST1*/ |
| 566 | #define R0900_P2_DISRX_ST1 0xf195 | 641 | #define R0900_P2_DISRX_ST1 0xf195 |
| 567 | #define F0900_P2_RX_FAIL 0xf1950080 | 642 | #define F0900_P2_RX_FAIL 0xf1950080 |
| 568 | #define F0900_P2_FIFO_PARITYFAIL 0xf1950040 | 643 | #define F0900_P2_FIFO_PARITYFAIL 0xf1950040 |
| 569 | #define F0900_P2_RX_NONBYTE 0xf1950020 | 644 | #define F0900_P2_RX_NONBYTE 0xf1950020 |
| 570 | #define F0900_P2_FIFO_OVERFLOW 0xf1950010 | 645 | #define F0900_P2_FIFO_OVERFLOW 0xf1950010 |
| 571 | #define F0900_P2_FIFO_BYTENBR 0xf195000f | 646 | #define F0900_P2_FIFO_BYTENBR 0xf195000f |
| 572 | 647 | ||
| 573 | /*P2_DISRXDATA*/ | 648 | /*P2_DISRXDATA*/ |
| 574 | #define R0900_P2_DISRXDATA 0xf196 | 649 | #define R0900_P2_DISRXDATA 0xf196 |
| 575 | #define F0900_P2_DISRX_DATA 0xf19600ff | 650 | #define F0900_P2_DISRX_DATA 0xf19600ff |
| 576 | 651 | ||
| 577 | /*P2_DISTXDATA*/ | 652 | /*P2_DISTXDATA*/ |
| 578 | #define R0900_P2_DISTXDATA 0xf197 | 653 | #define R0900_P2_DISTXDATA 0xf197 |
| 579 | #define F0900_P2_DISEQC_FIFO 0xf19700ff | 654 | #define F0900_P2_DISEQC_FIFO 0xf19700ff |
| 580 | 655 | ||
| 581 | /*P2_DISTXSTATUS*/ | 656 | /*P2_DISTXSTATUS*/ |
| 582 | #define R0900_P2_DISTXSTATUS 0xf198 | 657 | #define R0900_P2_DISTXSTATUS 0xf198 |
| 583 | #define F0900_P2_TX_FAIL 0xf1980080 | 658 | #define F0900_P2_TX_FAIL 0xf1980080 |
| 584 | #define F0900_P2_FIFO_FULL 0xf1980040 | 659 | #define F0900_P2_FIFO_FULL 0xf1980040 |
| 585 | #define F0900_P2_TX_IDLE 0xf1980020 | 660 | #define F0900_P2_TX_IDLE 0xf1980020 |
| 586 | #define F0900_P2_GAP_BURST 0xf1980010 | 661 | #define F0900_P2_GAP_BURST 0xf1980010 |
| 587 | #define F0900_P2_TXFIFO_BYTES 0xf198000f | 662 | #define F0900_P2_TXFIFO_BYTES 0xf198000f |
| 588 | 663 | ||
| 589 | /*P2_F22TX*/ | 664 | /*P2_F22TX*/ |
| 590 | #define R0900_P2_F22TX 0xf199 | 665 | #define R0900_P2_F22TX 0xf199 |
| 591 | #define F0900_P2_F22_REG 0xf19900ff | 666 | #define F0900_P2_F22_REG 0xf19900ff |
| 592 | 667 | ||
| 593 | /*P2_F22RX*/ | 668 | /*P2_F22RX*/ |
| 594 | #define R0900_P2_F22RX 0xf19a | 669 | #define R0900_P2_F22RX 0xf19a |
| 595 | #define F0900_P2_F22RX_REG 0xf19a00ff | 670 | #define F0900_P2_F22RX_REG 0xf19a00ff |
| 596 | 671 | ||
| 597 | /*P2_ACRPRESC*/ | 672 | /*P2_ACRPRESC*/ |
| 598 | #define R0900_P2_ACRPRESC 0xf19c | 673 | #define R0900_P2_ACRPRESC 0xf19c |
| 599 | #define F0900_P2_ACR_CODFRDY 0xf19c0008 | 674 | #define F0900_P2_ACR_PRESC 0xf19c0007 |
| 600 | #define F0900_P2_ACR_PRESC 0xf19c0007 | ||
| 601 | 675 | ||
| 602 | /*P2_ACRDIV*/ | 676 | /*P2_ACRDIV*/ |
| 603 | #define R0900_P2_ACRDIV 0xf19d | 677 | #define R0900_P2_ACRDIV 0xf19d |
| 604 | #define F0900_P2_ACR_DIV 0xf19d00ff | 678 | #define F0900_P2_ACR_DIV 0xf19d00ff |
| 605 | 679 | ||
| 606 | /*P1_DISTXCTL*/ | 680 | /*P1_DISTXCTL*/ |
| 607 | #define R0900_P1_DISTXCTL 0xf1a0 | 681 | #define R0900_P1_DISTXCTL 0xf1a0 |
| 608 | #define F0900_P1_TIM_OFF 0xf1a00080 | 682 | #define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10) |
| 609 | #define F0900_P1_DISEQC_RESET 0xf1a00040 | 683 | #define F0900_P1_TIM_OFF 0xf1a00080 |
| 610 | #define F0900_P1_TIM_CMD 0xf1a00030 | 684 | #define F0900_P1_DISEQC_RESET 0xf1a00040 |
| 611 | #define F0900_P1_DIS_PRECHARGE 0xf1a00008 | 685 | #define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000) |
| 612 | #define F0900_P1_DISTX_MODE 0xf1a00007 | 686 | #define F0900_P1_TIM_CMD 0xf1a00030 |
| 687 | #define F0900_P1_DIS_PRECHARGE 0xf1a00008 | ||
| 688 | #define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000) | ||
| 689 | #define F0900_P1_DISTX_MODE 0xf1a00007 | ||
| 690 | #define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000) | ||
| 613 | 691 | ||
| 614 | /*P1_DISRXCTL*/ | 692 | /*P1_DISRXCTL*/ |
| 615 | #define R0900_P1_DISRXCTL 0xf1a1 | 693 | #define R0900_P1_DISRXCTL 0xf1a1 |
| 616 | #define F0900_P1_RECEIVER_ON 0xf1a10080 | 694 | #define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10) |
| 617 | #define F0900_P1_IGNO_SHORT22K 0xf1a10040 | 695 | #define F0900_P1_RECEIVER_ON 0xf1a10080 |
| 618 | #define F0900_P1_ONECHIP_TRX 0xf1a10020 | 696 | #define F0900_P1_IGNO_SHORT22K 0xf1a10040 |
| 619 | #define F0900_P1_EXT_ENVELOP 0xf1a10010 | 697 | #define F0900_P1_ONECHIP_TRX 0xf1a10020 |
| 620 | #define F0900_P1_PIN_SELECT 0xf1a1000c | 698 | #define F0900_P1_EXT_ENVELOP 0xf1a10010 |
| 621 | #define F0900_P1_IRQ_RXEND 0xf1a10002 | 699 | #define F0900_P1_PIN_SELECT0 0xf1a1000c |
| 622 | #define F0900_P1_IRQ_4NBYTES 0xf1a10001 | 700 | #define F0900_P1_IRQ_RXEND 0xf1a10002 |
| 701 | #define F0900_P1_IRQ_4NBYTES 0xf1a10001 | ||
| 623 | 702 | ||
| 624 | /*P1_DISRX_ST0*/ | 703 | /*P1_DISRX_ST0*/ |
| 625 | #define R0900_P1_DISRX_ST0 0xf1a4 | 704 | #define R0900_P1_DISRX_ST0 0xf1a4 |
| 626 | #define F0900_P1_RX_END 0xf1a40080 | 705 | #define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10) |
| 627 | #define F0900_P1_RX_ACTIVE 0xf1a40040 | 706 | #define F0900_P1_RX_END 0xf1a40080 |
| 628 | #define F0900_P1_SHORT_22KHZ 0xf1a40020 | 707 | #define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000) |
| 629 | #define F0900_P1_CONT_TONE 0xf1a40010 | 708 | #define F0900_P1_RX_ACTIVE 0xf1a40040 |
| 630 | #define F0900_P1_FIFO_4BREADY 0xf1a40008 | 709 | #define F0900_P1_SHORT_22KHZ 0xf1a40020 |
| 631 | #define F0900_P1_FIFO_EMPTY 0xf1a40004 | 710 | #define F0900_P1_CONT_TONE 0xf1a40010 |
| 632 | #define F0900_P1_ABORT_DISRX 0xf1a40001 | 711 | #define F0900_P1_FIFO_4BREADY 0xf1a40008 |
| 712 | #define F0900_P1_FIFO_EMPTY 0xf1a40004 | ||
| 713 | #define F0900_P1_ABORT_DISRX 0xf1a40001 | ||
| 633 | 714 | ||
| 634 | /*P1_DISRX_ST1*/ | 715 | /*P1_DISRX_ST1*/ |
| 635 | #define R0900_P1_DISRX_ST1 0xf1a5 | 716 | #define R0900_P1_DISRX_ST1 0xf1a5 |
| 636 | #define F0900_P1_RX_FAIL 0xf1a50080 | 717 | #define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10) |
| 637 | #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040 | 718 | #define F0900_P1_RX_FAIL 0xf1a50080 |
| 638 | #define F0900_P1_RX_NONBYTE 0xf1a50020 | 719 | #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040 |
| 639 | #define F0900_P1_FIFO_OVERFLOW 0xf1a50010 | 720 | #define F0900_P1_RX_NONBYTE 0xf1a50020 |
| 640 | #define F0900_P1_FIFO_BYTENBR 0xf1a5000f | 721 | #define F0900_P1_FIFO_OVERFLOW 0xf1a50010 |
| 722 | #define F0900_P1_FIFO_BYTENBR 0xf1a5000f | ||
| 723 | #define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000) | ||
| 641 | 724 | ||
| 642 | /*P1_DISRXDATA*/ | 725 | /*P1_DISRXDATA*/ |
| 643 | #define R0900_P1_DISRXDATA 0xf1a6 | 726 | #define R0900_P1_DISRXDATA 0xf1a6 |
| 644 | #define F0900_P1_DISRX_DATA 0xf1a600ff | 727 | #define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10) |
| 728 | #define F0900_P1_DISRX_DATA 0xf1a600ff | ||
| 645 | 729 | ||
| 646 | /*P1_DISTXDATA*/ | 730 | /*P1_DISTXDATA*/ |
| 647 | #define R0900_P1_DISTXDATA 0xf1a7 | 731 | #define R0900_P1_DISTXDATA 0xf1a7 |
| 648 | #define F0900_P1_DISEQC_FIFO 0xf1a700ff | 732 | #define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10) |
| 733 | #define F0900_P1_DISEQC_FIFO 0xf1a700ff | ||
| 649 | 734 | ||
| 650 | /*P1_DISTXSTATUS*/ | 735 | /*P1_DISTXSTATUS*/ |
| 651 | #define R0900_P1_DISTXSTATUS 0xf1a8 | 736 | #define R0900_P1_DISTXSTATUS 0xf1a8 |
| 652 | #define F0900_P1_TX_FAIL 0xf1a80080 | 737 | #define F0900_P1_TX_FAIL 0xf1a80080 |
| 653 | #define F0900_P1_FIFO_FULL 0xf1a80040 | 738 | #define F0900_P1_FIFO_FULL 0xf1a80040 |
| 654 | #define F0900_P1_TX_IDLE 0xf1a80020 | 739 | #define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000) |
| 655 | #define F0900_P1_GAP_BURST 0xf1a80010 | 740 | #define F0900_P1_TX_IDLE 0xf1a80020 |
| 656 | #define F0900_P1_TXFIFO_BYTES 0xf1a8000f | 741 | #define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000) |
| 742 | #define F0900_P1_GAP_BURST 0xf1a80010 | ||
| 743 | #define F0900_P1_TXFIFO_BYTES 0xf1a8000f | ||
| 657 | 744 | ||
| 658 | /*P1_F22TX*/ | 745 | /*P1_F22TX*/ |
| 659 | #define R0900_P1_F22TX 0xf1a9 | 746 | #define R0900_P1_F22TX 0xf1a9 |
| 660 | #define F0900_P1_F22_REG 0xf1a900ff | 747 | #define F22TX shiftx(R0900_P1_F22TX, demod, 0x10) |
| 748 | #define F0900_P1_F22_REG 0xf1a900ff | ||
| 661 | 749 | ||
| 662 | /*P1_F22RX*/ | 750 | /*P1_F22RX*/ |
| 663 | #define R0900_P1_F22RX 0xf1aa | 751 | #define R0900_P1_F22RX 0xf1aa |
| 664 | #define F0900_P1_F22RX_REG 0xf1aa00ff | 752 | #define F22RX shiftx(R0900_P1_F22RX, demod, 0x10) |
| 753 | #define F0900_P1_F22RX_REG 0xf1aa00ff | ||
| 665 | 754 | ||
| 666 | /*P1_ACRPRESC*/ | 755 | /*P1_ACRPRESC*/ |
| 667 | #define R0900_P1_ACRPRESC 0xf1ac | 756 | #define R0900_P1_ACRPRESC 0xf1ac |
| 668 | #define F0900_P1_ACR_CODFRDY 0xf1ac0008 | 757 | #define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10) |
| 669 | #define F0900_P1_ACR_PRESC 0xf1ac0007 | 758 | #define F0900_P1_ACR_PRESC 0xf1ac0007 |
| 670 | 759 | ||
| 671 | /*P1_ACRDIV*/ | 760 | /*P1_ACRDIV*/ |
| 672 | #define R0900_P1_ACRDIV 0xf1ad | 761 | #define R0900_P1_ACRDIV 0xf1ad |
| 673 | #define F0900_P1_ACR_DIV 0xf1ad00ff | 762 | #define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10) |
| 763 | #define F0900_P1_ACR_DIV 0xf1ad00ff | ||
| 674 | 764 | ||
| 675 | /*NCOARSE*/ | 765 | /*NCOARSE*/ |
| 676 | #define R0900_NCOARSE 0xf1b3 | 766 | #define R0900_NCOARSE 0xf1b3 |
| 677 | #define F0900_M_DIV 0xf1b300ff | 767 | #define F0900_M_DIV 0xf1b300ff |
| 678 | 768 | ||
| 679 | /*SYNTCTRL*/ | 769 | /*SYNTCTRL*/ |
| 680 | #define R0900_SYNTCTRL 0xf1b6 | 770 | #define R0900_SYNTCTRL 0xf1b6 |
| 681 | #define F0900_STANDBY 0xf1b60080 | 771 | #define F0900_STANDBY 0xf1b60080 |
| 682 | #define F0900_BYPASSPLLCORE 0xf1b60040 | 772 | #define F0900_BYPASSPLLCORE 0xf1b60040 |
| 683 | #define F0900_SELX1RATIO 0xf1b60020 | 773 | #define F0900_SELX1RATIO 0xf1b60020 |
| 684 | #define F0900_I2C_TUD 0xf1b60010 | 774 | #define F0900_STOP_PLL 0xf1b60008 |
| 685 | #define F0900_STOP_PLL 0xf1b60008 | 775 | #define F0900_BYPASSPLLFSK 0xf1b60004 |
| 686 | #define F0900_BYPASSPLLFSK 0xf1b60004 | 776 | #define F0900_SELOSCI 0xf1b60002 |
| 687 | #define F0900_SELOSCI 0xf1b60002 | 777 | #define F0900_BYPASSPLLADC 0xf1b60001 |
| 688 | #define F0900_BYPASSPLLADC 0xf1b60001 | ||
| 689 | 778 | ||
| 690 | /*FILTCTRL*/ | 779 | /*FILTCTRL*/ |
| 691 | #define R0900_FILTCTRL 0xf1b7 | 780 | #define R0900_FILTCTRL 0xf1b7 |
| 692 | #define F0900_INV_CLK135 0xf1b70080 | 781 | #define F0900_INV_CLK135 0xf1b70080 |
| 693 | #define F0900_PERM_BYPDIS 0xf1b70040 | 782 | #define F0900_SEL_FSKCKDIV 0xf1b70004 |
| 694 | #define F0900_SEL_FSKCKDIV 0xf1b70004 | 783 | #define F0900_INV_CLKFSK 0xf1b70002 |
| 695 | #define F0900_INV_CLKFSK 0xf1b70002 | 784 | #define F0900_BYPASS_APPLI 0xf1b70001 |
| 696 | #define F0900_BYPASS_APPLI 0xf1b70001 | ||
| 697 | 785 | ||
| 698 | /*PLLSTAT*/ | 786 | /*PLLSTAT*/ |
| 699 | #define R0900_PLLSTAT 0xf1b8 | 787 | #define R0900_PLLSTAT 0xf1b8 |
| 700 | #define F0900_ACM_SEL 0xf1b80080 | 788 | #define F0900_PLLLOCK 0xf1b80001 |
| 701 | #define F0900_DTV_SEL 0xf1b80040 | ||
| 702 | #define F0900_PLLLOCK 0xf1b80001 | ||
| 703 | 789 | ||
| 704 | /*STOPCLK1*/ | 790 | /*STOPCLK1*/ |
| 705 | #define R0900_STOPCLK1 0xf1c2 | 791 | #define R0900_STOPCLK1 0xf1c2 |
| 706 | #define F0900_STOP_CLKPKDT2 0xf1c20040 | 792 | #define F0900_STOP_CLKPKDT2 0xf1c20040 |
| 707 | #define F0900_STOP_CLKPKDT1 0xf1c20020 | 793 | #define F0900_STOP_CLKPKDT1 0xf1c20020 |
| 708 | #define F0900_STOP_CLKFEC 0xf1c20010 | 794 | #define F0900_STOP_CLKFEC 0xf1c20010 |
| 709 | #define F0900_STOP_CLKADCI2 0xf1c20008 | 795 | #define F0900_STOP_CLKADCI2 0xf1c20008 |
| 710 | #define F0900_INV_CLKADCI2 0xf1c20004 | 796 | #define F0900_INV_CLKADCI2 0xf1c20004 |
| 711 | #define F0900_STOP_CLKADCI1 0xf1c20002 | 797 | #define F0900_STOP_CLKADCI1 0xf1c20002 |
| 712 | #define F0900_INV_CLKADCI1 0xf1c20001 | 798 | #define F0900_INV_CLKADCI1 0xf1c20001 |
| 713 | 799 | ||
| 714 | /*STOPCLK2*/ | 800 | /*STOPCLK2*/ |
| 715 | #define R0900_STOPCLK2 0xf1c3 | 801 | #define R0900_STOPCLK2 0xf1c3 |
| 716 | #define F0900_STOP_CLKSAMP2 0xf1c30010 | 802 | #define F0900_STOP_CLKSAMP2 0xf1c30010 |
| 717 | #define F0900_STOP_CLKSAMP1 0xf1c30008 | 803 | #define F0900_STOP_CLKSAMP1 0xf1c30008 |
| 718 | #define F0900_STOP_CLKVIT2 0xf1c30004 | 804 | #define F0900_STOP_CLKVIT2 0xf1c30004 |
| 719 | #define F0900_STOP_CLKVIT1 0xf1c30002 | 805 | #define F0900_STOP_CLKVIT1 0xf1c30002 |
| 720 | #define F0900_STOP_CLKTS 0xf1c30001 | 806 | #define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2) |
| 807 | #define F0900_STOP_CLKTS 0xf1c30001 | ||
| 721 | 808 | ||
| 722 | /*TSTTNR0*/ | 809 | /*TSTTNR0*/ |
| 723 | #define R0900_TSTTNR0 0xf1df | 810 | #define R0900_TSTTNR0 0xf1df |
| 724 | #define F0900_SEL_FSK 0xf1df0080 | 811 | #define F0900_SEL_FSK 0xf1df0080 |
| 725 | #define F0900_FSK_PON 0xf1df0004 | 812 | #define F0900_FSK_PON 0xf1df0004 |
| 726 | #define F0900_FSK_OPENLOOP 0xf1df0002 | ||
| 727 | 813 | ||
| 728 | /*TSTTNR1*/ | 814 | /*TSTTNR1*/ |
| 729 | #define R0900_TSTTNR1 0xf1e0 | 815 | #define R0900_TSTTNR1 0xf1e0 |
| 730 | #define F0900_BYPASS_ADC1 0xf1e00080 | 816 | #define F0900_ADC1_PON 0xf1e00002 |
| 731 | #define F0900_INVADC1_CKOUT 0xf1e00040 | 817 | #define F0900_ADC1_INMODE 0xf1e00001 |
| 732 | #define F0900_SELIQSRC1 0xf1e00030 | ||
| 733 | #define F0900_ADC1_PON 0xf1e00002 | ||
| 734 | #define F0900_ADC1_INMODE 0xf1e00001 | ||
| 735 | 818 | ||
| 736 | /*TSTTNR2*/ | 819 | /*TSTTNR2*/ |
| 737 | #define R0900_TSTTNR2 0xf1e1 | 820 | #define R0900_TSTTNR2 0xf1e1 |
| 738 | #define F0900_DISEQC1_PON 0xf1e10020 | 821 | #define F0900_DISEQC1_PON 0xf1e10020 |
| 739 | #define F0900_DISEQC1_TEST 0xf1e1001f | ||
| 740 | 822 | ||
| 741 | /*TSTTNR3*/ | 823 | /*TSTTNR3*/ |
| 742 | #define R0900_TSTTNR3 0xf1e2 | 824 | #define R0900_TSTTNR3 0xf1e2 |
| 743 | #define F0900_BYPASS_ADC2 0xf1e20080 | 825 | #define F0900_ADC2_PON 0xf1e20002 |
| 744 | #define F0900_INVADC2_CKOUT 0xf1e20040 | 826 | #define F0900_ADC2_INMODE 0xf1e20001 |
| 745 | #define F0900_SELIQSRC2 0xf1e20030 | ||
| 746 | #define F0900_ADC2_PON 0xf1e20002 | ||
| 747 | #define F0900_ADC2_INMODE 0xf1e20001 | ||
| 748 | 827 | ||
| 749 | /*TSTTNR4*/ | 828 | /*TSTTNR4*/ |
| 750 | #define R0900_TSTTNR4 0xf1e3 | 829 | #define R0900_TSTTNR4 0xf1e3 |
| 751 | #define F0900_DISEQC2_PON 0xf1e30020 | 830 | #define F0900_DISEQC2_PON 0xf1e30020 |
| 752 | #define F0900_DISEQC2_TEST 0xf1e3001f | ||
| 753 | 831 | ||
| 754 | /*P2_IQCONST*/ | 832 | /*P2_IQCONST*/ |
| 755 | #define R0900_P2_IQCONST 0xf200 | 833 | #define R0900_P2_IQCONST 0xf200 |
| 756 | #define F0900_P2_CONSTEL_SELECT 0xf2000060 | 834 | #define F0900_P2_CONSTEL_SELECT 0xf2000060 |
| 757 | #define F0900_P2_IQSYMB_SEL 0xf200001f | 835 | #define F0900_P2_IQSYMB_SEL 0xf200001f |
| 758 | 836 | ||
| 759 | /*P2_NOSCFG*/ | 837 | /*P2_NOSCFG*/ |
| 760 | #define R0900_P2_NOSCFG 0xf201 | 838 | #define R0900_P2_NOSCFG 0xf201 |
| 761 | #define F0900_P2_DUMMYPL_NOSDATA 0xf2010020 | 839 | #define F0900_P2_DUMMYPL_NOSDATA 0xf2010020 |
| 762 | #define F0900_P2_NOSPLH_BETA 0xf2010018 | 840 | #define F0900_P2_NOSPLH_BETA 0xf2010018 |
| 763 | #define F0900_P2_NOSDATA_BETA 0xf2010007 | 841 | #define F0900_P2_NOSDATA_BETA 0xf2010007 |
| 764 | 842 | ||
| 765 | /*P2_ISYMB*/ | 843 | /*P2_ISYMB*/ |
| 766 | #define R0900_P2_ISYMB 0xf202 | 844 | #define R0900_P2_ISYMB 0xf202 |
| 767 | #define F0900_P2_I_SYMBOL 0xf20201ff | 845 | #define F0900_P2_I_SYMBOL 0xf20201ff |
| 768 | 846 | ||
| 769 | /*P2_QSYMB*/ | 847 | /*P2_QSYMB*/ |
| 770 | #define R0900_P2_QSYMB 0xf203 | 848 | #define R0900_P2_QSYMB 0xf203 |
| 771 | #define F0900_P2_Q_SYMBOL 0xf20301ff | 849 | #define F0900_P2_Q_SYMBOL 0xf20301ff |
| 772 | 850 | ||
| 773 | /*P2_AGC1CFG*/ | 851 | /*P2_AGC1CFG*/ |
| 774 | #define R0900_P2_AGC1CFG 0xf204 | 852 | #define R0900_P2_AGC1CFG 0xf204 |
| 775 | #define F0900_P2_DC_FROZEN 0xf2040080 | 853 | #define F0900_P2_DC_FROZEN 0xf2040080 |
| 776 | #define F0900_P2_DC_CORRECT 0xf2040040 | 854 | #define F0900_P2_DC_CORRECT 0xf2040040 |
| 777 | #define F0900_P2_AMM_FROZEN 0xf2040020 | 855 | #define F0900_P2_AMM_FROZEN 0xf2040020 |
| 778 | #define F0900_P2_AMM_CORRECT 0xf2040010 | 856 | #define F0900_P2_AMM_CORRECT 0xf2040010 |
| 779 | #define F0900_P2_QUAD_FROZEN 0xf2040008 | 857 | #define F0900_P2_QUAD_FROZEN 0xf2040008 |
| 780 | #define F0900_P2_QUAD_CORRECT 0xf2040004 | 858 | #define F0900_P2_QUAD_CORRECT 0xf2040004 |
| 781 | #define F0900_P2_DCCOMP_SLOW 0xf2040002 | ||
| 782 | #define F0900_P2_IQMISM_SLOW 0xf2040001 | ||
| 783 | 859 | ||
| 784 | /*P2_AGC1CN*/ | 860 | /*P2_AGC1CN*/ |
| 785 | #define R0900_P2_AGC1CN 0xf206 | 861 | #define R0900_P2_AGC1CN 0xf206 |
| 786 | #define F0900_P2_AGC1_LOCKED 0xf2060080 | 862 | #define F0900_P2_AGC1_LOCKED 0xf2060080 |
| 787 | #define F0900_P2_AGC1_OVERFLOW 0xf2060040 | 863 | #define F0900_P2_AGC1_MINPOWER 0xf2060010 |
| 788 | #define F0900_P2_AGC1_NOSLOWLK 0xf2060020 | 864 | #define F0900_P2_AGCOUT_FAST 0xf2060008 |
| 789 | #define F0900_P2_AGC1_MINPOWER 0xf2060010 | 865 | #define F0900_P2_AGCIQ_BETA 0xf2060007 |
| 790 | #define F0900_P2_AGCOUT_FAST 0xf2060008 | ||
| 791 | #define F0900_P2_AGCIQ_BETA 0xf2060007 | ||
| 792 | 866 | ||
| 793 | /*P2_AGC1REF*/ | 867 | /*P2_AGC1REF*/ |
| 794 | #define R0900_P2_AGC1REF 0xf207 | 868 | #define R0900_P2_AGC1REF 0xf207 |
| 795 | #define F0900_P2_AGCIQ_REF 0xf20700ff | 869 | #define F0900_P2_AGCIQ_REF 0xf20700ff |
| 796 | 870 | ||
| 797 | /*P2_IDCCOMP*/ | 871 | /*P2_IDCCOMP*/ |
| 798 | #define R0900_P2_IDCCOMP 0xf208 | 872 | #define R0900_P2_IDCCOMP 0xf208 |
| 799 | #define F0900_P2_IAVERAGE_ADJ 0xf20801ff | 873 | #define F0900_P2_IAVERAGE_ADJ 0xf20801ff |
| 800 | 874 | ||
| 801 | /*P2_QDCCOMP*/ | 875 | /*P2_QDCCOMP*/ |
| 802 | #define R0900_P2_QDCCOMP 0xf209 | 876 | #define R0900_P2_QDCCOMP 0xf209 |
| 803 | #define F0900_P2_QAVERAGE_ADJ 0xf20901ff | 877 | #define F0900_P2_QAVERAGE_ADJ 0xf20901ff |
| 804 | 878 | ||
| 805 | /*P2_POWERI*/ | 879 | /*P2_POWERI*/ |
| 806 | #define R0900_P2_POWERI 0xf20a | 880 | #define R0900_P2_POWERI 0xf20a |
| 807 | #define F0900_P2_POWER_I 0xf20a00ff | 881 | #define F0900_P2_POWER_I 0xf20a00ff |
| 808 | 882 | ||
| 809 | /*P2_POWERQ*/ | 883 | /*P2_POWERQ*/ |
| 810 | #define R0900_P2_POWERQ 0xf20b | 884 | #define R0900_P2_POWERQ 0xf20b |
| 811 | #define F0900_P2_POWER_Q 0xf20b00ff | 885 | #define F0900_P2_POWER_Q 0xf20b00ff |
| 812 | 886 | ||
| 813 | /*P2_AGC1AMM*/ | 887 | /*P2_AGC1AMM*/ |
| 814 | #define R0900_P2_AGC1AMM 0xf20c | 888 | #define R0900_P2_AGC1AMM 0xf20c |
| 815 | #define F0900_P2_AMM_VALUE 0xf20c00ff | 889 | #define F0900_P2_AMM_VALUE 0xf20c00ff |
| 816 | 890 | ||
| 817 | /*P2_AGC1QUAD*/ | 891 | /*P2_AGC1QUAD*/ |
| 818 | #define R0900_P2_AGC1QUAD 0xf20d | 892 | #define R0900_P2_AGC1QUAD 0xf20d |
| 819 | #define F0900_P2_QUAD_VALUE 0xf20d01ff | 893 | #define F0900_P2_QUAD_VALUE 0xf20d01ff |
| 820 | 894 | ||
| 821 | /*P2_AGCIQIN1*/ | 895 | /*P2_AGCIQIN1*/ |
| 822 | #define R0900_P2_AGCIQIN1 0xf20e | 896 | #define R0900_P2_AGCIQIN1 0xf20e |
| 823 | #define F0900_P2_AGCIQ_VALUE1 0xf20e00ff | 897 | #define F0900_P2_AGCIQ_VALUE1 0xf20e00ff |
| 824 | 898 | ||
| 825 | /*P2_AGCIQIN0*/ | 899 | /*P2_AGCIQIN0*/ |
| 826 | #define R0900_P2_AGCIQIN0 0xf20f | 900 | #define R0900_P2_AGCIQIN0 0xf20f |
| 827 | #define F0900_P2_AGCIQ_VALUE0 0xf20f00ff | 901 | #define F0900_P2_AGCIQ_VALUE0 0xf20f00ff |
| 828 | 902 | ||
| 829 | /*P2_DEMOD*/ | 903 | /*P2_DEMOD*/ |
| 830 | #define R0900_P2_DEMOD 0xf210 | 904 | #define R0900_P2_DEMOD 0xf210 |
| 831 | #define F0900_P2_DEMOD_STOP 0xf2100040 | 905 | #define F0900_P2_MANUALS2_ROLLOFF 0xf2100080 |
| 832 | #define F0900_P2_SPECINV_CONTROL 0xf2100030 | 906 | #define F0900_P2_SPECINV_CONTROL 0xf2100030 |
| 833 | #define F0900_P2_FORCE_ENASAMP 0xf2100008 | 907 | #define F0900_P2_FORCE_ENASAMP 0xf2100008 |
| 834 | #define F0900_P2_MANUAL_ROLLOFF 0xf2100004 | 908 | #define F0900_P2_MANUALSX_ROLLOFF 0xf2100004 |
| 835 | #define F0900_P2_ROLLOFF_CONTROL 0xf2100003 | 909 | #define F0900_P2_ROLLOFF_CONTROL 0xf2100003 |
| 836 | 910 | ||
| 837 | /*P2_DMDMODCOD*/ | 911 | /*P2_DMDMODCOD*/ |
| 838 | #define R0900_P2_DMDMODCOD 0xf211 | 912 | #define R0900_P2_DMDMODCOD 0xf211 |
| 839 | #define F0900_P2_MANUAL_MODCOD 0xf2110080 | 913 | #define F0900_P2_MANUAL_MODCOD 0xf2110080 |
| 840 | #define F0900_P2_DEMOD_MODCOD 0xf211007c | 914 | #define F0900_P2_DEMOD_MODCOD 0xf211007c |
| 841 | #define F0900_P2_DEMOD_TYPE 0xf2110003 | 915 | #define F0900_P2_DEMOD_TYPE 0xf2110003 |
| 842 | 916 | ||
| 843 | /*P2_DSTATUS*/ | 917 | /*P2_DSTATUS*/ |
| 844 | #define R0900_P2_DSTATUS 0xf212 | 918 | #define R0900_P2_DSTATUS 0xf212 |
| 845 | #define F0900_P2_CAR_LOCK 0xf2120080 | 919 | #define F0900_P2_CAR_LOCK 0xf2120080 |
| 846 | #define F0900_P2_TMGLOCK_QUALITY 0xf2120060 | 920 | #define F0900_P2_TMGLOCK_QUALITY 0xf2120060 |
| 847 | #define F0900_P2_SDVBS1_ENABLE 0xf2120010 | 921 | #define F0900_P2_LOCK_DEFINITIF 0xf2120008 |
| 848 | #define F0900_P2_LOCK_DEFINITIF 0xf2120008 | 922 | #define F0900_P2_OVADC_DETECT 0xf2120001 |
| 849 | #define F0900_P2_TIMING_IS_LOCKED 0xf2120004 | ||
| 850 | #define F0900_P2_COARSE_TMGLOCK 0xf2120002 | ||
| 851 | #define F0900_P2_COARSE_CARLOCK 0xf2120001 | ||
| 852 | 923 | ||
| 853 | /*P2_DSTATUS2*/ | 924 | /*P2_DSTATUS2*/ |
| 854 | #define R0900_P2_DSTATUS2 0xf213 | 925 | #define R0900_P2_DSTATUS2 0xf213 |
| 855 | #define F0900_P2_DEMOD_DELOCK 0xf2130080 | 926 | #define F0900_P2_DEMOD_DELOCK 0xf2130080 |
| 856 | #define F0900_P2_DEMOD_TIMEOUT 0xf2130040 | 927 | #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008 |
| 857 | #define F0900_P2_MODCODRQ_SYNCTAG 0xf2130020 | 928 | #define F0900_P2_AGC2_OVERFLOW 0xf2130004 |
| 858 | #define F0900_P2_POLYPH_SATEVENT 0xf2130010 | 929 | #define F0900_P2_CFR_OVERFLOW 0xf2130002 |
| 859 | #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008 | 930 | #define F0900_P2_GAMMA_OVERUNDER 0xf2130001 |
| 860 | #define F0900_P2_AGC2_OVERFLOW 0xf2130004 | ||
| 861 | #define F0900_P2_CFR_OVERFLOW 0xf2130002 | ||
| 862 | #define F0900_P2_GAMMA_OVERUNDER 0xf2130001 | ||
| 863 | 931 | ||
| 864 | /*P2_DMDCFGMD*/ | 932 | /*P2_DMDCFGMD*/ |
| 865 | #define R0900_P2_DMDCFGMD 0xf214 | 933 | #define R0900_P2_DMDCFGMD 0xf214 |
| 866 | #define F0900_P2_DVBS2_ENABLE 0xf2140080 | 934 | #define F0900_P2_DVBS2_ENABLE 0xf2140080 |
| 867 | #define F0900_P2_DVBS1_ENABLE 0xf2140040 | 935 | #define F0900_P2_DVBS1_ENABLE 0xf2140040 |
| 868 | #define F0900_P2_CFR_AUTOSCAN 0xf2140020 | 936 | #define F0900_P2_SCAN_ENABLE 0xf2140010 |
| 869 | #define F0900_P2_SCAN_ENABLE 0xf2140010 | 937 | #define F0900_P2_CFR_AUTOSCAN 0xf2140008 |
| 870 | #define F0900_P2_TUN_AUTOSCAN 0xf2140008 | 938 | #define F0900_P2_TUN_RNG 0xf2140003 |
| 871 | #define F0900_P2_NOFORCE_RELOCK 0xf2140004 | ||
| 872 | #define F0900_P2_TUN_RNG 0xf2140003 | ||
| 873 | 939 | ||
| 874 | /*P2_DMDCFG2*/ | 940 | /*P2_DMDCFG2*/ |
| 875 | #define R0900_P2_DMDCFG2 0xf215 | 941 | #define R0900_P2_DMDCFG2 0xf215 |
| 876 | #define F0900_P2_AGC1_WAITLOCK 0xf2150080 | 942 | #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040 |
| 877 | #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040 | 943 | #define F0900_P2_INFINITE_RELOCK 0xf2150010 |
| 878 | #define F0900_P2_OVERFLOW_TIMEOUT 0xf2150020 | ||
| 879 | #define F0900_P2_SCANFAIL_TIMEOUT 0xf2150010 | ||
| 880 | #define F0900_P2_DMDTOUT_BACK 0xf2150008 | ||
| 881 | #define F0900_P2_CARLOCK_S1ENABLE 0xf2150004 | ||
| 882 | #define F0900_P2_COARSE_LK3MODE 0xf2150002 | ||
| 883 | #define F0900_P2_COARSE_LK2MODE 0xf2150001 | ||
| 884 | 944 | ||
| 885 | /*P2_DMDISTATE*/ | 945 | /*P2_DMDISTATE*/ |
| 886 | #define R0900_P2_DMDISTATE 0xf216 | 946 | #define R0900_P2_DMDISTATE 0xf216 |
| 887 | #define F0900_P2_I2C_NORESETDMODE 0xf2160080 | 947 | #define F0900_P2_I2C_DEMOD_MODE 0xf216001f |
| 888 | #define F0900_P2_FORCE_ETAPED 0xf2160040 | ||
| 889 | #define F0900_P2_SDMDRST_DIRCLK 0xf2160020 | ||
| 890 | #define F0900_P2_I2C_DEMOD_MODE 0xf216001f | ||
| 891 | 948 | ||
| 892 | /*P2_DMDT0M*/ | 949 | /*P2_DMDT0M*/ |
| 893 | #define R0900_P2_DMDT0M 0xf217 | 950 | #define R0900_P2_DMDT0M 0xf217 |
| 894 | #define F0900_P2_DMDT0_MIN 0xf21700ff | 951 | #define F0900_P2_DMDT0_MIN 0xf21700ff |
| 895 | 952 | ||
| 896 | /*P2_DMDSTATE*/ | 953 | /*P2_DMDSTATE*/ |
| 897 | #define R0900_P2_DMDSTATE 0xf21b | 954 | #define R0900_P2_DMDSTATE 0xf21b |
| 898 | #define F0900_P2_DEMOD_LOCKED 0xf21b0080 | 955 | #define F0900_P2_HEADER_MODE 0xf21b0060 |
| 899 | #define F0900_P2_HEADER_MODE 0xf21b0060 | ||
| 900 | #define F0900_P2_DEMOD_MODE 0xf21b001f | ||
| 901 | 956 | ||
| 902 | /*P2_DMDFLYW*/ | 957 | /*P2_DMDFLYW*/ |
| 903 | #define R0900_P2_DMDFLYW 0xf21c | 958 | #define R0900_P2_DMDFLYW 0xf21c |
| 904 | #define F0900_P2_I2C_IRQVAL 0xf21c00f0 | 959 | #define F0900_P2_I2C_IRQVAL 0xf21c00f0 |
| 905 | #define F0900_P2_FLYWHEEL_CPT 0xf21c000f | 960 | #define F0900_P2_FLYWHEEL_CPT 0xf21c000f |
| 906 | 961 | ||
| 907 | /*P2_DSTATUS3*/ | 962 | /*P2_DSTATUS3*/ |
| 908 | #define R0900_P2_DSTATUS3 0xf21d | 963 | #define R0900_P2_DSTATUS3 0xf21d |
| 909 | #define F0900_P2_CFR_ZIGZAG 0xf21d0080 | 964 | #define F0900_P2_DEMOD_CFGMODE 0xf21d0060 |
| 910 | #define F0900_P2_DEMOD_CFGMODE 0xf21d0060 | ||
| 911 | #define F0900_P2_GAMMA_LOWBAUDRATE 0xf21d0010 | ||
| 912 | #define F0900_P2_RELOCK_MODE 0xf21d0008 | ||
| 913 | #define F0900_P2_DEMOD_FAIL 0xf21d0004 | ||
| 914 | #define F0900_P2_ETAPE1A_DVBXMEM 0xf21d0003 | ||
| 915 | 965 | ||
| 916 | /*P2_DMDCFG3*/ | 966 | /*P2_DMDCFG3*/ |
| 917 | #define R0900_P2_DMDCFG3 0xf21e | 967 | #define R0900_P2_DMDCFG3 0xf21e |
| 918 | #define F0900_P2_DVBS1_TMGWAIT 0xf21e0080 | 968 | #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008 |
| 919 | #define F0900_P2_NO_BWCENTERING 0xf21e0040 | ||
| 920 | #define F0900_P2_INV_SEQSRCH 0xf21e0020 | ||
| 921 | #define F0900_P2_DIS_SFRUPLOW_TRK 0xf21e0010 | ||
| 922 | #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008 | ||
| 923 | #define F0900_P2_LOCKTIME_MODE 0xf21e0007 | ||
| 924 | 969 | ||
| 925 | /*P2_DMDCFG4*/ | 970 | /*P2_DMDCFG4*/ |
| 926 | #define R0900_P2_DMDCFG4 0xf21f | 971 | #define R0900_P2_DMDCFG4 0xf21f |
| 927 | #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008 | 972 | #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008 |
| 928 | #define F0900_P2_DIS_CLKENABLE 0xf21f0004 | ||
| 929 | #define F0900_P2_DIS_HDRDIVLOCK 0xf21f0002 | ||
| 930 | #define F0900_P2_NO_TNRWBINIT 0xf21f0001 | ||
| 931 | 973 | ||
| 932 | /*P2_CORRELMANT*/ | 974 | /*P2_CORRELMANT*/ |
| 933 | #define R0900_P2_CORRELMANT 0xf220 | 975 | #define R0900_P2_CORRELMANT 0xf220 |
| 934 | #define F0900_P2_CORREL_MANT 0xf22000ff | 976 | #define F0900_P2_CORREL_MANT 0xf22000ff |
| 935 | 977 | ||
| 936 | /*P2_CORRELABS*/ | 978 | /*P2_CORRELABS*/ |
| 937 | #define R0900_P2_CORRELABS 0xf221 | 979 | #define R0900_P2_CORRELABS 0xf221 |
| 938 | #define F0900_P2_CORREL_ABS 0xf22100ff | 980 | #define F0900_P2_CORREL_ABS 0xf22100ff |
| 939 | 981 | ||
| 940 | /*P2_CORRELEXP*/ | 982 | /*P2_CORRELEXP*/ |
| 941 | #define R0900_P2_CORRELEXP 0xf222 | 983 | #define R0900_P2_CORRELEXP 0xf222 |
| 942 | #define F0900_P2_CORREL_ABSEXP 0xf22200f0 | 984 | #define F0900_P2_CORREL_ABSEXP 0xf22200f0 |
| 943 | #define F0900_P2_CORREL_EXP 0xf222000f | 985 | #define F0900_P2_CORREL_EXP 0xf222000f |
| 944 | 986 | ||
| 945 | /*P2_PLHMODCOD*/ | 987 | /*P2_PLHMODCOD*/ |
| 946 | #define R0900_P2_PLHMODCOD 0xf224 | 988 | #define R0900_P2_PLHMODCOD 0xf224 |
| 947 | #define F0900_P2_SPECINV_DEMOD 0xf2240080 | 989 | #define F0900_P2_SPECINV_DEMOD 0xf2240080 |
| 948 | #define F0900_P2_PLH_MODCOD 0xf224007c | 990 | #define F0900_P2_PLH_MODCOD 0xf224007c |
| 949 | #define F0900_P2_PLH_TYPE 0xf2240003 | 991 | #define F0900_P2_PLH_TYPE 0xf2240003 |
| 950 | 992 | ||
| 951 | /*P2_AGCK32*/ | 993 | /*P2_DMDREG*/ |
| 952 | #define R0900_P2_AGCK32 0xf22b | 994 | #define R0900_P2_DMDREG 0xf225 |
| 953 | #define F0900_P2_R3ADJOFF_32APSK 0xf22b0080 | 995 | #define F0900_P2_DECIM_PLFRAMES 0xf2250001 |
| 954 | #define F0900_P2_R2ADJOFF_32APSK 0xf22b0040 | ||
| 955 | #define F0900_P2_R1ADJOFF_32APSK 0xf22b0020 | ||
| 956 | #define F0900_P2_RADJ_32APSK 0xf22b001f | ||
| 957 | 996 | ||
| 958 | /*P2_AGC2O*/ | 997 | /*P2_AGC2O*/ |
| 959 | #define R0900_P2_AGC2O 0xf22c | 998 | #define R0900_P2_AGC2O 0xf22c |
| 960 | #define F0900_P2_AGC2REF_ADJUSTING 0xf22c0080 | 999 | #define F0900_P2_AGC2_COEF 0xf22c0007 |
| 961 | #define F0900_P2_AGC2_COARSEFAST 0xf22c0040 | ||
| 962 | #define F0900_P2_AGC2_LKSQRT 0xf22c0020 | ||
| 963 | #define F0900_P2_AGC2_LKMODE 0xf22c0010 | ||
| 964 | #define F0900_P2_AGC2_LKEQUA 0xf22c0008 | ||
| 965 | #define F0900_P2_AGC2_COEF 0xf22c0007 | ||
| 966 | 1000 | ||
| 967 | /*P2_AGC2REF*/ | 1001 | /*P2_AGC2REF*/ |
| 968 | #define R0900_P2_AGC2REF 0xf22d | 1002 | #define R0900_P2_AGC2REF 0xf22d |
| 969 | #define F0900_P2_AGC2_REF 0xf22d00ff | 1003 | #define F0900_P2_AGC2_REF 0xf22d00ff |
| 970 | 1004 | ||
| 971 | /*P2_AGC1ADJ*/ | 1005 | /*P2_AGC1ADJ*/ |
| 972 | #define R0900_P2_AGC1ADJ 0xf22e | 1006 | #define R0900_P2_AGC1ADJ 0xf22e |
| 973 | #define F0900_P2_AGC1ADJ_MANUAL 0xf22e0080 | 1007 | #define F0900_P2_AGC1_ADJUSTED 0xf22e007f |
| 974 | #define F0900_P2_AGC1_ADJUSTED 0xf22e017f | ||
| 975 | 1008 | ||
| 976 | /*P2_AGC2I1*/ | 1009 | /*P2_AGC2I1*/ |
| 977 | #define R0900_P2_AGC2I1 0xf236 | 1010 | #define R0900_P2_AGC2I1 0xf236 |
| 978 | #define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff | 1011 | #define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff |
| 979 | 1012 | ||
| 980 | /*P2_AGC2I0*/ | 1013 | /*P2_AGC2I0*/ |
| 981 | #define R0900_P2_AGC2I0 0xf237 | 1014 | #define R0900_P2_AGC2I0 0xf237 |
| 982 | #define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff | 1015 | #define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff |
| 983 | 1016 | ||
| 984 | /*P2_CARCFG*/ | 1017 | /*P2_CARCFG*/ |
| 985 | #define R0900_P2_CARCFG 0xf238 | 1018 | #define R0900_P2_CARCFG 0xf238 |
| 986 | #define F0900_P2_CFRUPLOW_AUTO 0xf2380080 | 1019 | #define F0900_P2_CFRUPLOW_AUTO 0xf2380080 |
| 987 | #define F0900_P2_CFRUPLOW_TEST 0xf2380040 | 1020 | #define F0900_P2_CFRUPLOW_TEST 0xf2380040 |
| 988 | #define F0900_P2_EN_CAR2CENTER 0xf2380020 | 1021 | #define F0900_P2_ROTAON 0xf2380004 |
| 989 | #define F0900_P2_CARHDR_NODIV8 0xf2380010 | 1022 | #define F0900_P2_PH_DET_ALGO 0xf2380003 |
| 990 | #define F0900_P2_I2C_ROTA 0xf2380008 | ||
| 991 | #define F0900_P2_ROTAON 0xf2380004 | ||
| 992 | #define F0900_P2_PH_DET_ALGO 0xf2380003 | ||
| 993 | 1023 | ||
| 994 | /*P2_ACLC*/ | 1024 | /*P2_ACLC*/ |
| 995 | #define R0900_P2_ACLC 0xf239 | 1025 | #define R0900_P2_ACLC 0xf239 |
| 996 | #define F0900_P2_STOP_S2ALPHA 0xf23900c0 | 1026 | #define F0900_P2_CAR_ALPHA_MANT 0xf2390030 |
| 997 | #define F0900_P2_CAR_ALPHA_MANT 0xf2390030 | 1027 | #define F0900_P2_CAR_ALPHA_EXP 0xf239000f |
| 998 | #define F0900_P2_CAR_ALPHA_EXP 0xf239000f | ||
| 999 | 1028 | ||
| 1000 | /*P2_BCLC*/ | 1029 | /*P2_BCLC*/ |
| 1001 | #define R0900_P2_BCLC 0xf23a | 1030 | #define R0900_P2_BCLC 0xf23a |
| 1002 | #define F0900_P2_STOP_S2BETA 0xf23a00c0 | 1031 | #define F0900_P2_CAR_BETA_MANT 0xf23a0030 |
| 1003 | #define F0900_P2_CAR_BETA_MANT 0xf23a0030 | 1032 | #define F0900_P2_CAR_BETA_EXP 0xf23a000f |
| 1004 | #define F0900_P2_CAR_BETA_EXP 0xf23a000f | ||
| 1005 | 1033 | ||
| 1006 | /*P2_CARFREQ*/ | 1034 | /*P2_CARFREQ*/ |
| 1007 | #define R0900_P2_CARFREQ 0xf23d | 1035 | #define R0900_P2_CARFREQ 0xf23d |
| 1008 | #define F0900_P2_KC_COARSE_EXP 0xf23d00f0 | 1036 | #define F0900_P2_KC_COARSE_EXP 0xf23d00f0 |
| 1009 | #define F0900_P2_BETA_FREQ 0xf23d000f | 1037 | #define F0900_P2_BETA_FREQ 0xf23d000f |
| 1010 | 1038 | ||
| 1011 | /*P2_CARHDR*/ | 1039 | /*P2_CARHDR*/ |
| 1012 | #define R0900_P2_CARHDR 0xf23e | 1040 | #define R0900_P2_CARHDR 0xf23e |
| 1013 | #define F0900_P2_K_FREQ_HDR 0xf23e00ff | 1041 | #define F0900_P2_K_FREQ_HDR 0xf23e00ff |
| 1014 | 1042 | ||
| 1015 | /*P2_LDT*/ | 1043 | /*P2_LDT*/ |
| 1016 | #define R0900_P2_LDT 0xf23f | 1044 | #define R0900_P2_LDT 0xf23f |
| 1017 | #define F0900_P2_CARLOCK_THRES 0xf23f01ff | 1045 | #define F0900_P2_CARLOCK_THRES 0xf23f01ff |
| 1018 | 1046 | ||
| 1019 | /*P2_LDT2*/ | 1047 | /*P2_LDT2*/ |
| 1020 | #define R0900_P2_LDT2 0xf240 | 1048 | #define R0900_P2_LDT2 0xf240 |
| 1021 | #define F0900_P2_CARLOCK_THRES2 0xf24001ff | 1049 | #define F0900_P2_CARLOCK_THRES2 0xf24001ff |
| 1022 | 1050 | ||
| 1023 | /*P2_CFRICFG*/ | 1051 | /*P2_CFRICFG*/ |
| 1024 | #define R0900_P2_CFRICFG 0xf241 | 1052 | #define R0900_P2_CFRICFG 0xf241 |
| 1025 | #define F0900_P2_CFRINIT_UNVALRNG 0xf2410080 | 1053 | #define F0900_P2_NEG_CFRSTEP 0xf2410001 |
| 1026 | #define F0900_P2_CFRINIT_LUNVALCPT 0xf2410040 | ||
| 1027 | #define F0900_P2_CFRINIT_ABORTDBL 0xf2410020 | ||
| 1028 | #define F0900_P2_CFRINIT_ABORTPRED 0xf2410010 | ||
| 1029 | #define F0900_P2_CFRINIT_UNVALSKIP 0xf2410008 | ||
| 1030 | #define F0900_P2_CFRINIT_CSTINC 0xf2410004 | ||
| 1031 | #define F0900_P2_NEG_CFRSTEP 0xf2410001 | ||
| 1032 | 1054 | ||
| 1033 | /*P2_CFRUP1*/ | 1055 | /*P2_CFRUP1*/ |
| 1034 | #define R0900_P2_CFRUP1 0xf242 | 1056 | #define R0900_P2_CFRUP1 0xf242 |
| 1035 | #define F0900_P2_CFR_UP1 0xf24201ff | 1057 | #define F0900_P2_CFR_UP1 0xf24201ff |
| 1036 | 1058 | ||
| 1037 | /*P2_CFRUP0*/ | 1059 | /*P2_CFRUP0*/ |
| 1038 | #define R0900_P2_CFRUP0 0xf243 | 1060 | #define R0900_P2_CFRUP0 0xf243 |
| 1039 | #define F0900_P2_CFR_UP0 0xf24300ff | 1061 | #define F0900_P2_CFR_UP0 0xf24300ff |
| 1040 | 1062 | ||
| 1041 | /*P2_CFRLOW1*/ | 1063 | /*P2_CFRLOW1*/ |
| 1042 | #define R0900_P2_CFRLOW1 0xf246 | 1064 | #define R0900_P2_CFRLOW1 0xf246 |
| 1043 | #define F0900_P2_CFR_LOW1 0xf24601ff | 1065 | #define F0900_P2_CFR_LOW1 0xf24601ff |
| 1044 | 1066 | ||
| 1045 | /*P2_CFRLOW0*/ | 1067 | /*P2_CFRLOW0*/ |
| 1046 | #define R0900_P2_CFRLOW0 0xf247 | 1068 | #define R0900_P2_CFRLOW0 0xf247 |
| 1047 | #define F0900_P2_CFR_LOW0 0xf24700ff | 1069 | #define F0900_P2_CFR_LOW0 0xf24700ff |
| 1048 | 1070 | ||
| 1049 | /*P2_CFRINIT1*/ | 1071 | /*P2_CFRINIT1*/ |
| 1050 | #define R0900_P2_CFRINIT1 0xf248 | 1072 | #define R0900_P2_CFRINIT1 0xf248 |
| 1051 | #define F0900_P2_CFR_INIT1 0xf24801ff | 1073 | #define F0900_P2_CFR_INIT1 0xf24801ff |
| 1052 | 1074 | ||
| 1053 | /*P2_CFRINIT0*/ | 1075 | /*P2_CFRINIT0*/ |
| 1054 | #define R0900_P2_CFRINIT0 0xf249 | 1076 | #define R0900_P2_CFRINIT0 0xf249 |
| 1055 | #define F0900_P2_CFR_INIT0 0xf24900ff | 1077 | #define F0900_P2_CFR_INIT0 0xf24900ff |
| 1056 | 1078 | ||
| 1057 | /*P2_CFRINC1*/ | 1079 | /*P2_CFRINC1*/ |
| 1058 | #define R0900_P2_CFRINC1 0xf24a | 1080 | #define R0900_P2_CFRINC1 0xf24a |
| 1059 | #define F0900_P2_MANUAL_CFRINC 0xf24a0080 | 1081 | #define F0900_P2_MANUAL_CFRINC 0xf24a0080 |
| 1060 | #define F0900_P2_CFR_INC1 0xf24a017f | 1082 | #define F0900_P2_CFR_INC1 0xf24a003f |
| 1061 | 1083 | ||
| 1062 | /*P2_CFRINC0*/ | 1084 | /*P2_CFRINC0*/ |
| 1063 | #define R0900_P2_CFRINC0 0xf24b | 1085 | #define R0900_P2_CFRINC0 0xf24b |
| 1064 | #define F0900_P2_CFR_INC0 0xf24b00f0 | 1086 | #define F0900_P2_CFR_INC0 0xf24b00f8 |
| 1065 | 1087 | ||
| 1066 | /*P2_CFR2*/ | 1088 | /*P2_CFR2*/ |
| 1067 | #define R0900_P2_CFR2 0xf24c | 1089 | #define R0900_P2_CFR2 0xf24c |
| 1068 | #define F0900_P2_CAR_FREQ2 0xf24c01ff | 1090 | #define F0900_P2_CAR_FREQ2 0xf24c01ff |
| 1069 | 1091 | ||
| 1070 | /*P2_CFR1*/ | 1092 | /*P2_CFR1*/ |
| 1071 | #define R0900_P2_CFR1 0xf24d | 1093 | #define R0900_P2_CFR1 0xf24d |
| 1072 | #define F0900_P2_CAR_FREQ1 0xf24d00ff | 1094 | #define F0900_P2_CAR_FREQ1 0xf24d00ff |
| 1073 | 1095 | ||
| 1074 | /*P2_CFR0*/ | 1096 | /*P2_CFR0*/ |
| 1075 | #define R0900_P2_CFR0 0xf24e | 1097 | #define R0900_P2_CFR0 0xf24e |
| 1076 | #define F0900_P2_CAR_FREQ0 0xf24e00ff | 1098 | #define F0900_P2_CAR_FREQ0 0xf24e00ff |
| 1077 | 1099 | ||
| 1078 | /*P2_LDI*/ | 1100 | /*P2_LDI*/ |
| 1079 | #define R0900_P2_LDI 0xf24f | 1101 | #define R0900_P2_LDI 0xf24f |
| 1080 | #define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff | 1102 | #define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff |
| 1081 | 1103 | ||
| 1082 | /*P2_TMGCFG*/ | 1104 | /*P2_TMGCFG*/ |
| 1083 | #define R0900_P2_TMGCFG 0xf250 | 1105 | #define R0900_P2_TMGCFG 0xf250 |
| 1084 | #define F0900_P2_TMGLOCK_BETA 0xf25000c0 | 1106 | #define F0900_P2_TMGLOCK_BETA 0xf25000c0 |
| 1085 | #define F0900_P2_NOTMG_GROUPDELAY 0xf2500020 | 1107 | #define F0900_P2_DO_TIMING_CORR 0xf2500010 |
| 1086 | #define F0900_P2_DO_TIMING_CORR 0xf2500010 | 1108 | #define F0900_P2_TMG_MINFREQ 0xf2500003 |
| 1087 | #define F0900_P2_MANUAL_SCAN 0xf250000c | ||
| 1088 | #define F0900_P2_TMG_MINFREQ 0xf2500003 | ||
| 1089 | 1109 | ||
| 1090 | /*P2_RTC*/ | 1110 | /*P2_RTC*/ |
| 1091 | #define R0900_P2_RTC 0xf251 | 1111 | #define R0900_P2_RTC 0xf251 |
| 1092 | #define F0900_P2_TMGALPHA_EXP 0xf25100f0 | 1112 | #define F0900_P2_TMGALPHA_EXP 0xf25100f0 |
| 1093 | #define F0900_P2_TMGBETA_EXP 0xf251000f | 1113 | #define F0900_P2_TMGBETA_EXP 0xf251000f |
| 1094 | 1114 | ||
| 1095 | /*P2_RTCS2*/ | 1115 | /*P2_RTCS2*/ |
| 1096 | #define R0900_P2_RTCS2 0xf252 | 1116 | #define R0900_P2_RTCS2 0xf252 |
| 1097 | #define F0900_P2_TMGALPHAS2_EXP 0xf25200f0 | 1117 | #define F0900_P2_TMGALPHAS2_EXP 0xf25200f0 |
| 1098 | #define F0900_P2_TMGBETAS2_EXP 0xf252000f | 1118 | #define F0900_P2_TMGBETAS2_EXP 0xf252000f |
| 1099 | 1119 | ||
| 1100 | /*P2_TMGTHRISE*/ | 1120 | /*P2_TMGTHRISE*/ |
| 1101 | #define R0900_P2_TMGTHRISE 0xf253 | 1121 | #define R0900_P2_TMGTHRISE 0xf253 |
| 1102 | #define F0900_P2_TMGLOCK_THRISE 0xf25300ff | 1122 | #define F0900_P2_TMGLOCK_THRISE 0xf25300ff |
| 1103 | 1123 | ||
| 1104 | /*P2_TMGTHFALL*/ | 1124 | /*P2_TMGTHFALL*/ |
| 1105 | #define R0900_P2_TMGTHFALL 0xf254 | 1125 | #define R0900_P2_TMGTHFALL 0xf254 |
| 1106 | #define F0900_P2_TMGLOCK_THFALL 0xf25400ff | 1126 | #define F0900_P2_TMGLOCK_THFALL 0xf25400ff |
| 1107 | 1127 | ||
| 1108 | /*P2_SFRUPRATIO*/ | 1128 | /*P2_SFRUPRATIO*/ |
| 1109 | #define R0900_P2_SFRUPRATIO 0xf255 | 1129 | #define R0900_P2_SFRUPRATIO 0xf255 |
| 1110 | #define F0900_P2_SFR_UPRATIO 0xf25500ff | 1130 | #define F0900_P2_SFR_UPRATIO 0xf25500ff |
| 1111 | 1131 | ||
| 1112 | /*P2_SFRLOWRATIO*/ | 1132 | /*P2_SFRLOWRATIO*/ |
| 1113 | #define R0900_P2_SFRLOWRATIO 0xf256 | 1133 | #define R0900_P2_SFRLOWRATIO 0xf256 |
| 1114 | #define F0900_P2_SFR_LOWRATIO 0xf25600ff | 1134 | #define F0900_P2_SFR_LOWRATIO 0xf25600ff |
| 1115 | 1135 | ||
| 1116 | /*P2_KREFTMG*/ | 1136 | /*P2_KREFTMG*/ |
| 1117 | #define R0900_P2_KREFTMG 0xf258 | 1137 | #define R0900_P2_KREFTMG 0xf258 |
| 1118 | #define F0900_P2_KREF_TMG 0xf25800ff | 1138 | #define F0900_P2_KREF_TMG 0xf25800ff |
| 1119 | 1139 | ||
| 1120 | /*P2_SFRSTEP*/ | 1140 | /*P2_SFRSTEP*/ |
| 1121 | #define R0900_P2_SFRSTEP 0xf259 | 1141 | #define R0900_P2_SFRSTEP 0xf259 |
| 1122 | #define F0900_P2_SFR_SCANSTEP 0xf25900f0 | 1142 | #define F0900_P2_SFR_SCANSTEP 0xf25900f0 |
| 1123 | #define F0900_P2_SFR_CENTERSTEP 0xf259000f | 1143 | #define F0900_P2_SFR_CENTERSTEP 0xf259000f |
| 1124 | 1144 | ||
| 1125 | /*P2_TMGCFG2*/ | 1145 | /*P2_TMGCFG2*/ |
| 1126 | #define R0900_P2_TMGCFG2 0xf25a | 1146 | #define R0900_P2_TMGCFG2 0xf25a |
| 1127 | #define F0900_P2_DIS_AUTOSAMP 0xf25a0008 | 1147 | #define F0900_P2_SFRRATIO_FINE 0xf25a0001 |
| 1128 | #define F0900_P2_SCANINIT_QUART 0xf25a0004 | 1148 | |
| 1129 | #define F0900_P2_NOTMG_DVBS1DERAT 0xf25a0002 | 1149 | /*P2_KREFTMG2*/ |
| 1130 | #define F0900_P2_SFRRATIO_FINE 0xf25a0001 | 1150 | #define R0900_P2_KREFTMG2 0xf25b |
| 1151 | #define F0900_P2_KREF_TMG2 0xf25b00ff | ||
| 1131 | 1152 | ||
| 1132 | /*P2_SFRINIT1*/ | 1153 | /*P2_SFRINIT1*/ |
| 1133 | #define R0900_P2_SFRINIT1 0xf25e | 1154 | #define R0900_P2_SFRINIT1 0xf25e |
| 1134 | #define F0900_P2_SFR_INIT1 0xf25e00ff | 1155 | #define F0900_P2_SFR_INIT1 0xf25e007f |
| 1135 | 1156 | ||
| 1136 | /*P2_SFRINIT0*/ | 1157 | /*P2_SFRINIT0*/ |
| 1137 | #define R0900_P2_SFRINIT0 0xf25f | 1158 | #define R0900_P2_SFRINIT0 0xf25f |
| 1138 | #define F0900_P2_SFR_INIT0 0xf25f00ff | 1159 | #define F0900_P2_SFR_INIT0 0xf25f00ff |
| 1139 | 1160 | ||
| 1140 | /*P2_SFRUP1*/ | 1161 | /*P2_SFRUP1*/ |
| 1141 | #define R0900_P2_SFRUP1 0xf260 | 1162 | #define R0900_P2_SFRUP1 0xf260 |
| 1142 | #define F0900_P2_AUTO_GUP 0xf2600080 | 1163 | #define F0900_P2_AUTO_GUP 0xf2600080 |
| 1143 | #define F0900_P2_SYMB_FREQ_UP1 0xf260007f | 1164 | #define F0900_P2_SYMB_FREQ_UP1 0xf260007f |
| 1144 | 1165 | ||
| 1145 | /*P2_SFRUP0*/ | 1166 | /*P2_SFRUP0*/ |
| 1146 | #define R0900_P2_SFRUP0 0xf261 | 1167 | #define R0900_P2_SFRUP0 0xf261 |
| 1147 | #define F0900_P2_SYMB_FREQ_UP0 0xf26100ff | 1168 | #define F0900_P2_SYMB_FREQ_UP0 0xf26100ff |
| 1148 | 1169 | ||
| 1149 | /*P2_SFRLOW1*/ | 1170 | /*P2_SFRLOW1*/ |
| 1150 | #define R0900_P2_SFRLOW1 0xf262 | 1171 | #define R0900_P2_SFRLOW1 0xf262 |
| 1151 | #define F0900_P2_AUTO_GLOW 0xf2620080 | 1172 | #define F0900_P2_AUTO_GLOW 0xf2620080 |
| 1152 | #define F0900_P2_SYMB_FREQ_LOW1 0xf262007f | 1173 | #define F0900_P2_SYMB_FREQ_LOW1 0xf262007f |
| 1153 | 1174 | ||
| 1154 | /*P2_SFRLOW0*/ | 1175 | /*P2_SFRLOW0*/ |
| 1155 | #define R0900_P2_SFRLOW0 0xf263 | 1176 | #define R0900_P2_SFRLOW0 0xf263 |
| 1156 | #define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff | 1177 | #define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff |
| 1157 | 1178 | ||
| 1158 | /*P2_SFR3*/ | 1179 | /*P2_SFR3*/ |
| 1159 | #define R0900_P2_SFR3 0xf264 | 1180 | #define R0900_P2_SFR3 0xf264 |
| 1160 | #define F0900_P2_SYMB_FREQ3 0xf26400ff | 1181 | #define F0900_P2_SYMB_FREQ3 0xf26400ff |
| 1161 | 1182 | ||
| 1162 | /*P2_SFR2*/ | 1183 | /*P2_SFR2*/ |
| 1163 | #define R0900_P2_SFR2 0xf265 | 1184 | #define R0900_P2_SFR2 0xf265 |
| 1164 | #define F0900_P2_SYMB_FREQ2 0xf26500ff | 1185 | #define F0900_P2_SYMB_FREQ2 0xf26500ff |
| 1165 | 1186 | ||
| 1166 | /*P2_SFR1*/ | 1187 | /*P2_SFR1*/ |
| 1167 | #define R0900_P2_SFR1 0xf266 | 1188 | #define R0900_P2_SFR1 0xf266 |
| 1168 | #define F0900_P2_SYMB_FREQ1 0xf26600ff | 1189 | #define F0900_P2_SYMB_FREQ1 0xf26600ff |
| 1169 | 1190 | ||
| 1170 | /*P2_SFR0*/ | 1191 | /*P2_SFR0*/ |
| 1171 | #define R0900_P2_SFR0 0xf267 | 1192 | #define R0900_P2_SFR0 0xf267 |
| 1172 | #define F0900_P2_SYMB_FREQ0 0xf26700ff | 1193 | #define F0900_P2_SYMB_FREQ0 0xf26700ff |
| 1173 | 1194 | ||
| 1174 | /*P2_TMGREG2*/ | 1195 | /*P2_TMGREG2*/ |
| 1175 | #define R0900_P2_TMGREG2 0xf268 | 1196 | #define R0900_P2_TMGREG2 0xf268 |
| 1176 | #define F0900_P2_TMGREG2 0xf26800ff | 1197 | #define F0900_P2_TMGREG2 0xf26800ff |
| 1177 | 1198 | ||
| 1178 | /*P2_TMGREG1*/ | 1199 | /*P2_TMGREG1*/ |
| 1179 | #define R0900_P2_TMGREG1 0xf269 | 1200 | #define R0900_P2_TMGREG1 0xf269 |
| 1180 | #define F0900_P2_TMGREG1 0xf26900ff | 1201 | #define F0900_P2_TMGREG1 0xf26900ff |
| 1181 | 1202 | ||
| 1182 | /*P2_TMGREG0*/ | 1203 | /*P2_TMGREG0*/ |
| 1183 | #define R0900_P2_TMGREG0 0xf26a | 1204 | #define R0900_P2_TMGREG0 0xf26a |
| 1184 | #define F0900_P2_TMGREG0 0xf26a00ff | 1205 | #define F0900_P2_TMGREG0 0xf26a00ff |
| 1185 | 1206 | ||
| 1186 | /*P2_TMGLOCK1*/ | 1207 | /*P2_TMGLOCK1*/ |
| 1187 | #define R0900_P2_TMGLOCK1 0xf26b | 1208 | #define R0900_P2_TMGLOCK1 0xf26b |
| 1188 | #define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff | 1209 | #define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff |
| 1189 | 1210 | ||
| 1190 | /*P2_TMGLOCK0*/ | 1211 | /*P2_TMGLOCK0*/ |
| 1191 | #define R0900_P2_TMGLOCK0 0xf26c | 1212 | #define R0900_P2_TMGLOCK0 0xf26c |
| 1192 | #define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff | 1213 | #define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff |
| 1193 | 1214 | ||
| 1194 | /*P2_TMGOBS*/ | 1215 | /*P2_TMGOBS*/ |
| 1195 | #define R0900_P2_TMGOBS 0xf26d | 1216 | #define R0900_P2_TMGOBS 0xf26d |
| 1196 | #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0 | 1217 | #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0 |
| 1197 | #define F0900_P2_SCAN_SIGN 0xf26d0030 | ||
| 1198 | #define F0900_P2_TMG_SCANNING 0xf26d0008 | ||
| 1199 | #define F0900_P2_CHCENTERING_MODE 0xf26d0004 | ||
| 1200 | #define F0900_P2_TMG_SCANFAIL 0xf26d0002 | ||
| 1201 | 1218 | ||
| 1202 | /*P2_EQUALCFG*/ | 1219 | /*P2_EQUALCFG*/ |
| 1203 | #define R0900_P2_EQUALCFG 0xf26f | 1220 | #define R0900_P2_EQUALCFG 0xf26f |
| 1204 | #define F0900_P2_NOTMG_NEGALWAIT 0xf26f0080 | 1221 | #define F0900_P2_EQUAL_ON 0xf26f0040 |
| 1205 | #define F0900_P2_EQUAL_ON 0xf26f0040 | 1222 | #define F0900_P2_MU_EQUALDFE 0xf26f0007 |
| 1206 | #define F0900_P2_SEL_EQUALCOR 0xf26f0038 | ||
| 1207 | #define F0900_P2_MU_EQUALDFE 0xf26f0007 | ||
| 1208 | 1223 | ||
| 1209 | /*P2_EQUAI1*/ | 1224 | /*P2_EQUAI1*/ |
| 1210 | #define R0900_P2_EQUAI1 0xf270 | 1225 | #define R0900_P2_EQUAI1 0xf270 |
| 1211 | #define F0900_P2_EQUA_ACCI1 0xf27001ff | 1226 | #define F0900_P2_EQUA_ACCI1 0xf27001ff |
| 1212 | 1227 | ||
| 1213 | /*P2_EQUAQ1*/ | 1228 | /*P2_EQUAQ1*/ |
| 1214 | #define R0900_P2_EQUAQ1 0xf271 | 1229 | #define R0900_P2_EQUAQ1 0xf271 |
| 1215 | #define F0900_P2_EQUA_ACCQ1 0xf27101ff | 1230 | #define F0900_P2_EQUA_ACCQ1 0xf27101ff |
| 1216 | 1231 | ||
| 1217 | /*P2_EQUAI2*/ | 1232 | /*P2_EQUAI2*/ |
| 1218 | #define R0900_P2_EQUAI2 0xf272 | 1233 | #define R0900_P2_EQUAI2 0xf272 |
| 1219 | #define F0900_P2_EQUA_ACCI2 0xf27201ff | 1234 | #define F0900_P2_EQUA_ACCI2 0xf27201ff |
| 1220 | 1235 | ||
| 1221 | /*P2_EQUAQ2*/ | 1236 | /*P2_EQUAQ2*/ |
| 1222 | #define R0900_P2_EQUAQ2 0xf273 | 1237 | #define R0900_P2_EQUAQ2 0xf273 |
| 1223 | #define F0900_P2_EQUA_ACCQ2 0xf27301ff | 1238 | #define F0900_P2_EQUA_ACCQ2 0xf27301ff |
| 1224 | 1239 | ||
| 1225 | /*P2_EQUAI3*/ | 1240 | /*P2_EQUAI3*/ |
| 1226 | #define R0900_P2_EQUAI3 0xf274 | 1241 | #define R0900_P2_EQUAI3 0xf274 |
| 1227 | #define F0900_P2_EQUA_ACCI3 0xf27401ff | 1242 | #define F0900_P2_EQUA_ACCI3 0xf27401ff |
| 1228 | 1243 | ||
| 1229 | /*P2_EQUAQ3*/ | 1244 | /*P2_EQUAQ3*/ |
| 1230 | #define R0900_P2_EQUAQ3 0xf275 | 1245 | #define R0900_P2_EQUAQ3 0xf275 |
| 1231 | #define F0900_P2_EQUA_ACCQ3 0xf27501ff | 1246 | #define F0900_P2_EQUA_ACCQ3 0xf27501ff |
| 1232 | 1247 | ||
| 1233 | /*P2_EQUAI4*/ | 1248 | /*P2_EQUAI4*/ |
| 1234 | #define R0900_P2_EQUAI4 0xf276 | 1249 | #define R0900_P2_EQUAI4 0xf276 |
| 1235 | #define F0900_P2_EQUA_ACCI4 0xf27601ff | 1250 | #define F0900_P2_EQUA_ACCI4 0xf27601ff |
| 1236 | 1251 | ||
| 1237 | /*P2_EQUAQ4*/ | 1252 | /*P2_EQUAQ4*/ |
| 1238 | #define R0900_P2_EQUAQ4 0xf277 | 1253 | #define R0900_P2_EQUAQ4 0xf277 |
| 1239 | #define F0900_P2_EQUA_ACCQ4 0xf27701ff | 1254 | #define F0900_P2_EQUA_ACCQ4 0xf27701ff |
| 1240 | 1255 | ||
| 1241 | /*P2_EQUAI5*/ | 1256 | /*P2_EQUAI5*/ |
| 1242 | #define R0900_P2_EQUAI5 0xf278 | 1257 | #define R0900_P2_EQUAI5 0xf278 |
| 1243 | #define F0900_P2_EQUA_ACCI5 0xf27801ff | 1258 | #define F0900_P2_EQUA_ACCI5 0xf27801ff |
| 1244 | 1259 | ||
| 1245 | /*P2_EQUAQ5*/ | 1260 | /*P2_EQUAQ5*/ |
| 1246 | #define R0900_P2_EQUAQ5 0xf279 | 1261 | #define R0900_P2_EQUAQ5 0xf279 |
| 1247 | #define F0900_P2_EQUA_ACCQ5 0xf27901ff | 1262 | #define F0900_P2_EQUA_ACCQ5 0xf27901ff |
| 1248 | 1263 | ||
| 1249 | /*P2_EQUAI6*/ | 1264 | /*P2_EQUAI6*/ |
| 1250 | #define R0900_P2_EQUAI6 0xf27a | 1265 | #define R0900_P2_EQUAI6 0xf27a |
| 1251 | #define F0900_P2_EQUA_ACCI6 0xf27a01ff | 1266 | #define F0900_P2_EQUA_ACCI6 0xf27a01ff |
| 1252 | 1267 | ||
| 1253 | /*P2_EQUAQ6*/ | 1268 | /*P2_EQUAQ6*/ |
| 1254 | #define R0900_P2_EQUAQ6 0xf27b | 1269 | #define R0900_P2_EQUAQ6 0xf27b |
| 1255 | #define F0900_P2_EQUA_ACCQ6 0xf27b01ff | 1270 | #define F0900_P2_EQUA_ACCQ6 0xf27b01ff |
| 1256 | 1271 | ||
| 1257 | /*P2_EQUAI7*/ | 1272 | /*P2_EQUAI7*/ |
| 1258 | #define R0900_P2_EQUAI7 0xf27c | 1273 | #define R0900_P2_EQUAI7 0xf27c |
| 1259 | #define F0900_P2_EQUA_ACCI7 0xf27c01ff | 1274 | #define F0900_P2_EQUA_ACCI7 0xf27c01ff |
| 1260 | 1275 | ||
| 1261 | /*P2_EQUAQ7*/ | 1276 | /*P2_EQUAQ7*/ |
| 1262 | #define R0900_P2_EQUAQ7 0xf27d | 1277 | #define R0900_P2_EQUAQ7 0xf27d |
| 1263 | #define F0900_P2_EQUA_ACCQ7 0xf27d01ff | 1278 | #define F0900_P2_EQUA_ACCQ7 0xf27d01ff |
| 1264 | 1279 | ||
| 1265 | /*P2_EQUAI8*/ | 1280 | /*P2_EQUAI8*/ |
| 1266 | #define R0900_P2_EQUAI8 0xf27e | 1281 | #define R0900_P2_EQUAI8 0xf27e |
| 1267 | #define F0900_P2_EQUA_ACCI8 0xf27e01ff | 1282 | #define F0900_P2_EQUA_ACCI8 0xf27e01ff |
| 1268 | 1283 | ||
| 1269 | /*P2_EQUAQ8*/ | 1284 | /*P2_EQUAQ8*/ |
| 1270 | #define R0900_P2_EQUAQ8 0xf27f | 1285 | #define R0900_P2_EQUAQ8 0xf27f |
| 1271 | #define F0900_P2_EQUA_ACCQ8 0xf27f01ff | 1286 | #define F0900_P2_EQUA_ACCQ8 0xf27f01ff |
| 1272 | 1287 | ||
| 1273 | /*P2_NNOSDATAT1*/ | 1288 | /*P2_NNOSDATAT1*/ |
| 1274 | #define R0900_P2_NNOSDATAT1 0xf280 | 1289 | #define R0900_P2_NNOSDATAT1 0xf280 |
| 1275 | #define F0900_P2_NOSDATAT_NORMED1 0xf28000ff | 1290 | #define F0900_P2_NOSDATAT_NORMED1 0xf28000ff |
| 1276 | 1291 | ||
| 1277 | /*P2_NNOSDATAT0*/ | 1292 | /*P2_NNOSDATAT0*/ |
| 1278 | #define R0900_P2_NNOSDATAT0 0xf281 | 1293 | #define R0900_P2_NNOSDATAT0 0xf281 |
| 1279 | #define F0900_P2_NOSDATAT_NORMED0 0xf28100ff | 1294 | #define F0900_P2_NOSDATAT_NORMED0 0xf28100ff |
| 1280 | 1295 | ||
| 1281 | /*P2_NNOSDATA1*/ | 1296 | /*P2_NNOSDATA1*/ |
| 1282 | #define R0900_P2_NNOSDATA1 0xf282 | 1297 | #define R0900_P2_NNOSDATA1 0xf282 |
| 1283 | #define F0900_P2_NOSDATA_NORMED1 0xf28200ff | 1298 | #define F0900_P2_NOSDATA_NORMED1 0xf28200ff |
| 1284 | 1299 | ||
| 1285 | /*P2_NNOSDATA0*/ | 1300 | /*P2_NNOSDATA0*/ |
| 1286 | #define R0900_P2_NNOSDATA0 0xf283 | 1301 | #define R0900_P2_NNOSDATA0 0xf283 |
| 1287 | #define F0900_P2_NOSDATA_NORMED0 0xf28300ff | 1302 | #define F0900_P2_NOSDATA_NORMED0 0xf28300ff |
| 1288 | 1303 | ||
| 1289 | /*P2_NNOSPLHT1*/ | 1304 | /*P2_NNOSPLHT1*/ |
| 1290 | #define R0900_P2_NNOSPLHT1 0xf284 | 1305 | #define R0900_P2_NNOSPLHT1 0xf284 |
| 1291 | #define F0900_P2_NOSPLHT_NORMED1 0xf28400ff | 1306 | #define F0900_P2_NOSPLHT_NORMED1 0xf28400ff |
| 1292 | 1307 | ||
| 1293 | /*P2_NNOSPLHT0*/ | 1308 | /*P2_NNOSPLHT0*/ |
| 1294 | #define R0900_P2_NNOSPLHT0 0xf285 | 1309 | #define R0900_P2_NNOSPLHT0 0xf285 |
| 1295 | #define F0900_P2_NOSPLHT_NORMED0 0xf28500ff | 1310 | #define F0900_P2_NOSPLHT_NORMED0 0xf28500ff |
| 1296 | 1311 | ||
| 1297 | /*P2_NNOSPLH1*/ | 1312 | /*P2_NNOSPLH1*/ |
| 1298 | #define R0900_P2_NNOSPLH1 0xf286 | 1313 | #define R0900_P2_NNOSPLH1 0xf286 |
| 1299 | #define F0900_P2_NOSPLH_NORMED1 0xf28600ff | 1314 | #define F0900_P2_NOSPLH_NORMED1 0xf28600ff |
| 1300 | 1315 | ||
| 1301 | /*P2_NNOSPLH0*/ | 1316 | /*P2_NNOSPLH0*/ |
| 1302 | #define R0900_P2_NNOSPLH0 0xf287 | 1317 | #define R0900_P2_NNOSPLH0 0xf287 |
| 1303 | #define F0900_P2_NOSPLH_NORMED0 0xf28700ff | 1318 | #define F0900_P2_NOSPLH_NORMED0 0xf28700ff |
| 1304 | 1319 | ||
| 1305 | /*P2_NOSDATAT1*/ | 1320 | /*P2_NOSDATAT1*/ |
| 1306 | #define R0900_P2_NOSDATAT1 0xf288 | 1321 | #define R0900_P2_NOSDATAT1 0xf288 |
| 1307 | #define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff | 1322 | #define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff |
| 1308 | 1323 | ||
| 1309 | /*P2_NOSDATAT0*/ | 1324 | /*P2_NOSDATAT0*/ |
| 1310 | #define R0900_P2_NOSDATAT0 0xf289 | 1325 | #define R0900_P2_NOSDATAT0 0xf289 |
| 1311 | #define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff | 1326 | #define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff |
| 1312 | 1327 | ||
| 1313 | /*P2_NOSDATA1*/ | 1328 | /*P2_NOSDATA1*/ |
| 1314 | #define R0900_P2_NOSDATA1 0xf28a | 1329 | #define R0900_P2_NOSDATA1 0xf28a |
| 1315 | #define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff | 1330 | #define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff |
| 1316 | 1331 | ||
| 1317 | /*P2_NOSDATA0*/ | 1332 | /*P2_NOSDATA0*/ |
| 1318 | #define R0900_P2_NOSDATA0 0xf28b | 1333 | #define R0900_P2_NOSDATA0 0xf28b |
| 1319 | #define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff | 1334 | #define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff |
| 1320 | 1335 | ||
| 1321 | /*P2_NOSPLHT1*/ | 1336 | /*P2_NOSPLHT1*/ |
| 1322 | #define R0900_P2_NOSPLHT1 0xf28c | 1337 | #define R0900_P2_NOSPLHT1 0xf28c |
| 1323 | #define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff | 1338 | #define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff |
| 1324 | 1339 | ||
| 1325 | /*P2_NOSPLHT0*/ | 1340 | /*P2_NOSPLHT0*/ |
| 1326 | #define R0900_P2_NOSPLHT0 0xf28d | 1341 | #define R0900_P2_NOSPLHT0 0xf28d |
| 1327 | #define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff | 1342 | #define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff |
| 1328 | 1343 | ||
| 1329 | /*P2_NOSPLH1*/ | 1344 | /*P2_NOSPLH1*/ |
| 1330 | #define R0900_P2_NOSPLH1 0xf28e | 1345 | #define R0900_P2_NOSPLH1 0xf28e |
| 1331 | #define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff | 1346 | #define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff |
| 1332 | 1347 | ||
| 1333 | /*P2_NOSPLH0*/ | 1348 | /*P2_NOSPLH0*/ |
| 1334 | #define R0900_P2_NOSPLH0 0xf28f | 1349 | #define R0900_P2_NOSPLH0 0xf28f |
| 1335 | #define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff | 1350 | #define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff |
| 1336 | 1351 | ||
| 1337 | /*P2_CAR2CFG*/ | 1352 | /*P2_CAR2CFG*/ |
| 1338 | #define R0900_P2_CAR2CFG 0xf290 | 1353 | #define R0900_P2_CAR2CFG 0xf290 |
| 1339 | #define F0900_P2_DESCRAMB_OFF 0xf2900080 | 1354 | #define F0900_P2_CARRIER3_DISABLE 0xf2900040 |
| 1340 | #define F0900_P2_PN4_SELECT 0xf2900040 | 1355 | #define F0900_P2_ROTA2ON 0xf2900004 |
| 1341 | #define F0900_P2_CFR2_STOPDVBS1 0xf2900020 | 1356 | #define F0900_P2_PH_DET_ALGO2 0xf2900003 |
| 1342 | #define F0900_P2_STOP_CFR2UPDATE 0xf2900010 | 1357 | |
| 1343 | #define F0900_P2_STOP_NCO2UPDATE 0xf2900008 | 1358 | /*P2_CFR2CFR1*/ |
| 1344 | #define F0900_P2_ROTA2ON 0xf2900004 | 1359 | #define R0900_P2_CFR2CFR1 0xf291 |
| 1345 | #define F0900_P2_PH_DET_ALGO2 0xf2900003 | 1360 | #define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0 |
| 1346 | 1361 | #define F0900_P2_EN_S2CAR2CENTER 0xf2910020 | |
| 1347 | /*P2_ACLC2*/ | 1362 | #define F0900_P2_DIS_BCHERRCFR2 0xf2910010 |
| 1348 | #define R0900_P2_ACLC2 0xf291 | 1363 | #define F0900_P2_CFR2TOCFR1_BETA 0xf2910007 |
| 1349 | #define F0900_P2_CAR2_PUNCT_ADERAT 0xf2910040 | ||
| 1350 | #define F0900_P2_CAR2_ALPHA_MANT 0xf2910030 | ||
| 1351 | #define F0900_P2_CAR2_ALPHA_EXP 0xf291000f | ||
| 1352 | |||
| 1353 | /*P2_BCLC2*/ | ||
| 1354 | #define R0900_P2_BCLC2 0xf292 | ||
| 1355 | #define F0900_P2_DVBS2_NIP 0xf2920080 | ||
| 1356 | #define F0900_P2_CAR2_PUNCT_BDERAT 0xf2920040 | ||
| 1357 | #define F0900_P2_CAR2_BETA_MANT 0xf2920030 | ||
| 1358 | #define F0900_P2_CAR2_BETA_EXP 0xf292000f | ||
| 1359 | 1364 | ||
| 1360 | /*P2_CFR22*/ | 1365 | /*P2_CFR22*/ |
| 1361 | #define R0900_P2_CFR22 0xf293 | 1366 | #define R0900_P2_CFR22 0xf293 |
| 1362 | #define F0900_P2_CAR2_FREQ2 0xf29301ff | 1367 | #define F0900_P2_CAR2_FREQ2 0xf29301ff |
| 1363 | 1368 | ||
| 1364 | /*P2_CFR21*/ | 1369 | /*P2_CFR21*/ |
| 1365 | #define R0900_P2_CFR21 0xf294 | 1370 | #define R0900_P2_CFR21 0xf294 |
| 1366 | #define F0900_P2_CAR2_FREQ1 0xf29400ff | 1371 | #define F0900_P2_CAR2_FREQ1 0xf29400ff |
| 1367 | 1372 | ||
| 1368 | /*P2_CFR20*/ | 1373 | /*P2_CFR20*/ |
| 1369 | #define R0900_P2_CFR20 0xf295 | 1374 | #define R0900_P2_CFR20 0xf295 |
| 1370 | #define F0900_P2_CAR2_FREQ0 0xf29500ff | 1375 | #define F0900_P2_CAR2_FREQ0 0xf29500ff |
| 1371 | 1376 | ||
| 1372 | /*P2_ACLC2S2Q*/ | 1377 | /*P2_ACLC2S2Q*/ |
| 1373 | #define R0900_P2_ACLC2S2Q 0xf297 | 1378 | #define R0900_P2_ACLC2S2Q 0xf297 |
| 1374 | #define F0900_P2_ENAB_SPSKSYMB 0xf2970080 | 1379 | #define F0900_P2_ENAB_SPSKSYMB 0xf2970080 |
| 1375 | #define F0900_P2_CAR2S2_QADERAT 0xf2970040 | 1380 | #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030 |
| 1376 | #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030 | 1381 | #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f |
| 1377 | #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f | ||
| 1378 | 1382 | ||
| 1379 | /*P2_ACLC2S28*/ | 1383 | /*P2_ACLC2S28*/ |
| 1380 | #define R0900_P2_ACLC2S28 0xf298 | 1384 | #define R0900_P2_ACLC2S28 0xf298 |
| 1381 | #define F0900_P2_OLDI3Q_MODE 0xf2980080 | 1385 | #define F0900_P2_OLDI3Q_MODE 0xf2980080 |
| 1382 | #define F0900_P2_CAR2S2_8ADERAT 0xf2980040 | 1386 | #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030 |
| 1383 | #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030 | 1387 | #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f |
| 1384 | #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f | ||
| 1385 | 1388 | ||
| 1386 | /*P2_ACLC2S216A*/ | 1389 | /*P2_ACLC2S216A*/ |
| 1387 | #define R0900_P2_ACLC2S216A 0xf299 | 1390 | #define R0900_P2_ACLC2S216A 0xf299 |
| 1388 | #define F0900_P2_CAR2S2_16ADERAT 0xf2990040 | 1391 | #define F0900_P2_DIS_C3STOPA2 0xf2990080 |
| 1389 | #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030 | 1392 | #define F0900_P2_CAR2S2_16ADERAT 0xf2990040 |
| 1390 | #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f | 1393 | #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030 |
| 1394 | #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f | ||
| 1391 | 1395 | ||
| 1392 | /*P2_ACLC2S232A*/ | 1396 | /*P2_ACLC2S232A*/ |
| 1393 | #define R0900_P2_ACLC2S232A 0xf29a | 1397 | #define R0900_P2_ACLC2S232A 0xf29a |
| 1394 | #define F0900_P2_CAR2S2_32ADERAT 0xf29a0040 | 1398 | #define F0900_P2_CAR2S2_32ADERAT 0xf29a0040 |
| 1395 | #define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030 | 1399 | #define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030 |
| 1396 | #define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f | 1400 | #define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f |
| 1397 | 1401 | ||
| 1398 | /*P2_BCLC2S2Q*/ | 1402 | /*P2_BCLC2S2Q*/ |
| 1399 | #define R0900_P2_BCLC2S2Q 0xf29c | 1403 | #define R0900_P2_BCLC2S2Q 0xf29c |
| 1400 | #define F0900_P2_DVBS2S2Q_NIP 0xf29c0080 | 1404 | #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030 |
| 1401 | #define F0900_P2_CAR2S2_QBDERAT 0xf29c0040 | 1405 | #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f |
| 1402 | #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030 | ||
| 1403 | #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f | ||
| 1404 | 1406 | ||
| 1405 | /*P2_BCLC2S28*/ | 1407 | /*P2_BCLC2S28*/ |
| 1406 | #define R0900_P2_BCLC2S28 0xf29d | 1408 | #define R0900_P2_BCLC2S28 0xf29d |
| 1407 | #define F0900_P2_DVBS2S28_NIP 0xf29d0080 | 1409 | #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030 |
| 1408 | #define F0900_P2_CAR2S2_8BDERAT 0xf29d0040 | 1410 | #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f |
| 1409 | #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030 | ||
| 1410 | #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f | ||
| 1411 | 1411 | ||
| 1412 | /*P2_BCLC2S216A*/ | 1412 | /*P2_BCLC2S216A*/ |
| 1413 | #define R0900_P2_BCLC2S216A 0xf29e | 1413 | #define R0900_P2_BCLC2S216A 0xf29e |
| 1414 | #define F0900_P2_DVBS2S216A_NIP 0xf29e0080 | ||
| 1415 | #define F0900_P2_CAR2S2_16BDERAT 0xf29e0040 | ||
| 1416 | #define F0900_P2_CAR2S2_16A_BETA_M 0xf29e0030 | ||
| 1417 | #define F0900_P2_CAR2S2_16A_BETA_E 0xf29e000f | ||
| 1418 | 1414 | ||
| 1419 | /*P2_BCLC2S232A*/ | 1415 | /*P2_BCLC2S232A*/ |
| 1420 | #define R0900_P2_BCLC2S232A 0xf29f | 1416 | #define R0900_P2_BCLC2S232A 0xf29f |
| 1421 | #define F0900_P2_DVBS2S232A_NIP 0xf29f0080 | ||
| 1422 | #define F0900_P2_CAR2S2_32BDERAT 0xf29f0040 | ||
| 1423 | #define F0900_P2_CAR2S2_32A_BETA_M 0xf29f0030 | ||
| 1424 | #define F0900_P2_CAR2S2_32A_BETA_E 0xf29f000f | ||
| 1425 | 1417 | ||
| 1426 | /*P2_PLROOT2*/ | 1418 | /*P2_PLROOT2*/ |
| 1427 | #define R0900_P2_PLROOT2 0xf2ac | 1419 | #define R0900_P2_PLROOT2 0xf2ac |
| 1428 | #define F0900_P2_SHORTFR_DISABLE 0xf2ac0080 | 1420 | #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c |
| 1429 | #define F0900_P2_LONGFR_DISABLE 0xf2ac0040 | 1421 | #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003 |
| 1430 | #define F0900_P2_DUMMYPL_DISABLE 0xf2ac0020 | ||
| 1431 | #define F0900_P2_SHORTFR_AVOID 0xf2ac0010 | ||
| 1432 | #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c | ||
| 1433 | #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003 | ||
| 1434 | 1422 | ||
| 1435 | /*P2_PLROOT1*/ | 1423 | /*P2_PLROOT1*/ |
| 1436 | #define R0900_P2_PLROOT1 0xf2ad | 1424 | #define R0900_P2_PLROOT1 0xf2ad |
| 1437 | #define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff | 1425 | #define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff |
| 1438 | 1426 | ||
| 1439 | /*P2_PLROOT0*/ | 1427 | /*P2_PLROOT0*/ |
| 1440 | #define R0900_P2_PLROOT0 0xf2ae | 1428 | #define R0900_P2_PLROOT0 0xf2ae |
| 1441 | #define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff | 1429 | #define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff |
| 1442 | 1430 | ||
| 1443 | /*P2_MODCODLST0*/ | 1431 | /*P2_MODCODLST0*/ |
| 1444 | #define R0900_P2_MODCODLST0 0xf2b0 | 1432 | #define R0900_P2_MODCODLST0 0xf2b0 |
| 1445 | #define F0900_P2_EN_TOKEN31 0xf2b00080 | ||
| 1446 | #define F0900_P2_SYNCTAG_SELECT 0xf2b00040 | ||
| 1447 | #define F0900_P2_MODCODRQ_MODE 0xf2b00030 | ||
| 1448 | 1433 | ||
| 1449 | /*P2_MODCODLST1*/ | 1434 | /*P2_MODCODLST1*/ |
| 1450 | #define R0900_P2_MODCODLST1 0xf2b1 | 1435 | #define R0900_P2_MODCODLST1 0xf2b1 |
| 1451 | #define F0900_P2_DIS_MODCOD29 0xf2b100f0 | 1436 | #define F0900_P2_DIS_MODCOD29 0xf2b100f0 |
| 1452 | #define F0900_P2_DIS_32PSK_9_10 0xf2b1000f | 1437 | #define F0900_P2_DIS_32PSK_9_10 0xf2b1000f |
| 1453 | 1438 | ||
| 1454 | /*P2_MODCODLST2*/ | 1439 | /*P2_MODCODLST2*/ |
| 1455 | #define R0900_P2_MODCODLST2 0xf2b2 | 1440 | #define R0900_P2_MODCODLST2 0xf2b2 |
| 1456 | #define F0900_P2_DIS_32PSK_8_9 0xf2b200f0 | 1441 | #define F0900_P2_DIS_32PSK_8_9 0xf2b200f0 |
| 1457 | #define F0900_P2_DIS_32PSK_5_6 0xf2b2000f | 1442 | #define F0900_P2_DIS_32PSK_5_6 0xf2b2000f |
| 1458 | 1443 | ||
| 1459 | /*P2_MODCODLST3*/ | 1444 | /*P2_MODCODLST3*/ |
| 1460 | #define R0900_P2_MODCODLST3 0xf2b3 | 1445 | #define R0900_P2_MODCODLST3 0xf2b3 |
| 1461 | #define F0900_P2_DIS_32PSK_4_5 0xf2b300f0 | 1446 | #define F0900_P2_DIS_32PSK_4_5 0xf2b300f0 |
| 1462 | #define F0900_P2_DIS_32PSK_3_4 0xf2b3000f | 1447 | #define F0900_P2_DIS_32PSK_3_4 0xf2b3000f |
| 1463 | 1448 | ||
| 1464 | /*P2_MODCODLST4*/ | 1449 | /*P2_MODCODLST4*/ |
| 1465 | #define R0900_P2_MODCODLST4 0xf2b4 | 1450 | #define R0900_P2_MODCODLST4 0xf2b4 |
| 1466 | #define F0900_P2_DIS_16PSK_9_10 0xf2b400f0 | 1451 | #define F0900_P2_DIS_16PSK_9_10 0xf2b400f0 |
| 1467 | #define F0900_P2_DIS_16PSK_8_9 0xf2b4000f | 1452 | #define F0900_P2_DIS_16PSK_8_9 0xf2b4000f |
| 1468 | 1453 | ||
| 1469 | /*P2_MODCODLST5*/ | 1454 | /*P2_MODCODLST5*/ |
| 1470 | #define R0900_P2_MODCODLST5 0xf2b5 | 1455 | #define R0900_P2_MODCODLST5 0xf2b5 |
| 1471 | #define F0900_P2_DIS_16PSK_5_6 0xf2b500f0 | 1456 | #define F0900_P2_DIS_16PSK_5_6 0xf2b500f0 |
| 1472 | #define F0900_P2_DIS_16PSK_4_5 0xf2b5000f | 1457 | #define F0900_P2_DIS_16PSK_4_5 0xf2b5000f |
| 1473 | 1458 | ||
| 1474 | /*P2_MODCODLST6*/ | 1459 | /*P2_MODCODLST6*/ |
| 1475 | #define R0900_P2_MODCODLST6 0xf2b6 | 1460 | #define R0900_P2_MODCODLST6 0xf2b6 |
| 1476 | #define F0900_P2_DIS_16PSK_3_4 0xf2b600f0 | 1461 | #define F0900_P2_DIS_16PSK_3_4 0xf2b600f0 |
| 1477 | #define F0900_P2_DIS_16PSK_2_3 0xf2b6000f | 1462 | #define F0900_P2_DIS_16PSK_2_3 0xf2b6000f |
| 1478 | 1463 | ||
| 1479 | /*P2_MODCODLST7*/ | 1464 | /*P2_MODCODLST7*/ |
| 1480 | #define R0900_P2_MODCODLST7 0xf2b7 | 1465 | #define R0900_P2_MODCODLST7 0xf2b7 |
| 1481 | #define F0900_P2_DIS_8P_9_10 0xf2b700f0 | 1466 | #define F0900_P2_DIS_8P_9_10 0xf2b700f0 |
| 1482 | #define F0900_P2_DIS_8P_8_9 0xf2b7000f | 1467 | #define F0900_P2_DIS_8P_8_9 0xf2b7000f |
| 1483 | 1468 | ||
| 1484 | /*P2_MODCODLST8*/ | 1469 | /*P2_MODCODLST8*/ |
| 1485 | #define R0900_P2_MODCODLST8 0xf2b8 | 1470 | #define R0900_P2_MODCODLST8 0xf2b8 |
| 1486 | #define F0900_P2_DIS_8P_5_6 0xf2b800f0 | 1471 | #define F0900_P2_DIS_8P_5_6 0xf2b800f0 |
| 1487 | #define F0900_P2_DIS_8P_3_4 0xf2b8000f | 1472 | #define F0900_P2_DIS_8P_3_4 0xf2b8000f |
| 1488 | 1473 | ||
| 1489 | /*P2_MODCODLST9*/ | 1474 | /*P2_MODCODLST9*/ |
| 1490 | #define R0900_P2_MODCODLST9 0xf2b9 | 1475 | #define R0900_P2_MODCODLST9 0xf2b9 |
| 1491 | #define F0900_P2_DIS_8P_2_3 0xf2b900f0 | 1476 | #define F0900_P2_DIS_8P_2_3 0xf2b900f0 |
| 1492 | #define F0900_P2_DIS_8P_3_5 0xf2b9000f | 1477 | #define F0900_P2_DIS_8P_3_5 0xf2b9000f |
| 1493 | 1478 | ||
| 1494 | /*P2_MODCODLSTA*/ | 1479 | /*P2_MODCODLSTA*/ |
| 1495 | #define R0900_P2_MODCODLSTA 0xf2ba | 1480 | #define R0900_P2_MODCODLSTA 0xf2ba |
| 1496 | #define F0900_P2_DIS_QP_9_10 0xf2ba00f0 | 1481 | #define F0900_P2_DIS_QP_9_10 0xf2ba00f0 |
| 1497 | #define F0900_P2_DIS_QP_8_9 0xf2ba000f | 1482 | #define F0900_P2_DIS_QP_8_9 0xf2ba000f |
| 1498 | 1483 | ||
| 1499 | /*P2_MODCODLSTB*/ | 1484 | /*P2_MODCODLSTB*/ |
| 1500 | #define R0900_P2_MODCODLSTB 0xf2bb | 1485 | #define R0900_P2_MODCODLSTB 0xf2bb |
| 1501 | #define F0900_P2_DIS_QP_5_6 0xf2bb00f0 | 1486 | #define F0900_P2_DIS_QP_5_6 0xf2bb00f0 |
| 1502 | #define F0900_P2_DIS_QP_4_5 0xf2bb000f | 1487 | #define F0900_P2_DIS_QP_4_5 0xf2bb000f |
| 1503 | 1488 | ||
| 1504 | /*P2_MODCODLSTC*/ | 1489 | /*P2_MODCODLSTC*/ |
| 1505 | #define R0900_P2_MODCODLSTC 0xf2bc | 1490 | #define R0900_P2_MODCODLSTC 0xf2bc |
| 1506 | #define F0900_P2_DIS_QP_3_4 0xf2bc00f0 | 1491 | #define F0900_P2_DIS_QP_3_4 0xf2bc00f0 |
| 1507 | #define F0900_P2_DIS_QP_2_3 0xf2bc000f | 1492 | #define F0900_P2_DIS_QP_2_3 0xf2bc000f |
| 1508 | 1493 | ||
| 1509 | /*P2_MODCODLSTD*/ | 1494 | /*P2_MODCODLSTD*/ |
| 1510 | #define R0900_P2_MODCODLSTD 0xf2bd | 1495 | #define R0900_P2_MODCODLSTD 0xf2bd |
| 1511 | #define F0900_P2_DIS_QP_3_5 0xf2bd00f0 | 1496 | #define F0900_P2_DIS_QP_3_5 0xf2bd00f0 |
| 1512 | #define F0900_P2_DIS_QP_1_2 0xf2bd000f | 1497 | #define F0900_P2_DIS_QP_1_2 0xf2bd000f |
| 1513 | 1498 | ||
| 1514 | /*P2_MODCODLSTE*/ | 1499 | /*P2_MODCODLSTE*/ |
| 1515 | #define R0900_P2_MODCODLSTE 0xf2be | 1500 | #define R0900_P2_MODCODLSTE 0xf2be |
| 1516 | #define F0900_P2_DIS_QP_2_5 0xf2be00f0 | 1501 | #define F0900_P2_DIS_QP_2_5 0xf2be00f0 |
| 1517 | #define F0900_P2_DIS_QP_1_3 0xf2be000f | 1502 | #define F0900_P2_DIS_QP_1_3 0xf2be000f |
| 1518 | 1503 | ||
| 1519 | /*P2_MODCODLSTF*/ | 1504 | /*P2_MODCODLSTF*/ |
| 1520 | #define R0900_P2_MODCODLSTF 0xf2bf | 1505 | #define R0900_P2_MODCODLSTF 0xf2bf |
| 1521 | #define F0900_P2_DIS_QP_1_4 0xf2bf00f0 | 1506 | #define F0900_P2_DIS_QP_1_4 0xf2bf00f0 |
| 1522 | #define F0900_P2_DDEMOD_SET 0xf2bf0002 | 1507 | |
| 1523 | #define F0900_P2_DDEMOD_MASK 0xf2bf0001 | 1508 | /*P2_GAUSSR0*/ |
| 1509 | #define R0900_P2_GAUSSR0 0xf2c0 | ||
| 1510 | #define F0900_P2_EN_CCIMODE 0xf2c00080 | ||
| 1511 | #define F0900_P2_R0_GAUSSIEN 0xf2c0007f | ||
| 1512 | |||
| 1513 | /*P2_CCIR0*/ | ||
| 1514 | #define R0900_P2_CCIR0 0xf2c1 | ||
| 1515 | #define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080 | ||
| 1516 | #define F0900_P2_R0_CCI 0xf2c1007f | ||
| 1517 | |||
| 1518 | /*P2_CCIQUANT*/ | ||
| 1519 | #define R0900_P2_CCIQUANT 0xf2c2 | ||
| 1520 | #define F0900_P2_CCI_BETA 0xf2c200e0 | ||
| 1521 | #define F0900_P2_CCI_QUANT 0xf2c2001f | ||
| 1522 | |||
| 1523 | /*P2_CCITHRES*/ | ||
| 1524 | #define R0900_P2_CCITHRES 0xf2c3 | ||
| 1525 | #define F0900_P2_CCI_THRESHOLD 0xf2c300ff | ||
| 1526 | |||
| 1527 | /*P2_CCIACC*/ | ||
| 1528 | #define R0900_P2_CCIACC 0xf2c4 | ||
| 1529 | #define F0900_P2_CCI_VALUE 0xf2c400ff | ||
| 1524 | 1530 | ||
| 1525 | /*P2_DMDRESCFG*/ | 1531 | /*P2_DMDRESCFG*/ |
| 1526 | #define R0900_P2_DMDRESCFG 0xf2c6 | 1532 | #define R0900_P2_DMDRESCFG 0xf2c6 |
| 1527 | #define F0900_P2_DMDRES_RESET 0xf2c60080 | 1533 | #define F0900_P2_DMDRES_RESET 0xf2c60080 |
| 1528 | #define F0900_P2_DMDRES_NOISESQR 0xf2c60010 | 1534 | #define F0900_P2_DMDRES_STRALL 0xf2c60008 |
| 1529 | #define F0900_P2_DMDRES_STRALL 0xf2c60008 | 1535 | #define F0900_P2_DMDRES_NEWONLY 0xf2c60004 |
| 1530 | #define F0900_P2_DMDRES_NEWONLY 0xf2c60004 | 1536 | #define F0900_P2_DMDRES_NOSTORE 0xf2c60002 |
| 1531 | #define F0900_P2_DMDRES_NOSTORE 0xf2c60002 | ||
| 1532 | #define F0900_P2_DMDRES_AGC2MEM 0xf2c60001 | ||
| 1533 | 1537 | ||
| 1534 | /*P2_DMDRESADR*/ | 1538 | /*P2_DMDRESADR*/ |
| 1535 | #define R0900_P2_DMDRESADR 0xf2c7 | 1539 | #define R0900_P2_DMDRESADR 0xf2c7 |
| 1536 | #define F0900_P2_SUSP_PREDCANAL 0xf2c70080 | 1540 | #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040 |
| 1537 | #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040 | 1541 | #define F0900_P2_DMDRES_MEMFULL 0xf2c70030 |
| 1538 | #define F0900_P2_DMDRES_MEMFULL 0xf2c70030 | 1542 | #define F0900_P2_DMDRES_RESNBR 0xf2c7000f |
| 1539 | #define F0900_P2_DMDRES_RESNBR 0xf2c7000f | ||
| 1540 | 1543 | ||
| 1541 | /*P2_DMDRESDATA7*/ | 1544 | /*P2_DMDRESDATA7*/ |
| 1542 | #define R0900_P2_DMDRESDATA7 0xf2c8 | 1545 | #define R0900_P2_DMDRESDATA7 0xf2c8 |
| 1543 | #define F0900_P2_DMDRES_DATA7 0xf2c800ff | 1546 | #define F0900_P2_DMDRES_DATA7 0xf2c800ff |
| 1544 | 1547 | ||
| 1545 | /*P2_DMDRESDATA6*/ | 1548 | /*P2_DMDRESDATA6*/ |
| 1546 | #define R0900_P2_DMDRESDATA6 0xf2c9 | 1549 | #define R0900_P2_DMDRESDATA6 0xf2c9 |
| 1547 | #define F0900_P2_DMDRES_DATA6 0xf2c900ff | 1550 | #define F0900_P2_DMDRES_DATA6 0xf2c900ff |
| 1548 | 1551 | ||
| 1549 | /*P2_DMDRESDATA5*/ | 1552 | /*P2_DMDRESDATA5*/ |
| 1550 | #define R0900_P2_DMDRESDATA5 0xf2ca | 1553 | #define R0900_P2_DMDRESDATA5 0xf2ca |
| 1551 | #define F0900_P2_DMDRES_DATA5 0xf2ca00ff | 1554 | #define F0900_P2_DMDRES_DATA5 0xf2ca00ff |
| 1552 | 1555 | ||
| 1553 | /*P2_DMDRESDATA4*/ | 1556 | /*P2_DMDRESDATA4*/ |
| 1554 | #define R0900_P2_DMDRESDATA4 0xf2cb | 1557 | #define R0900_P2_DMDRESDATA4 0xf2cb |
| 1555 | #define F0900_P2_DMDRES_DATA4 0xf2cb00ff | 1558 | #define F0900_P2_DMDRES_DATA4 0xf2cb00ff |
| 1556 | 1559 | ||
| 1557 | /*P2_DMDRESDATA3*/ | 1560 | /*P2_DMDRESDATA3*/ |
| 1558 | #define R0900_P2_DMDRESDATA3 0xf2cc | 1561 | #define R0900_P2_DMDRESDATA3 0xf2cc |
| 1559 | #define F0900_P2_DMDRES_DATA3 0xf2cc00ff | 1562 | #define F0900_P2_DMDRES_DATA3 0xf2cc00ff |
| 1560 | 1563 | ||
| 1561 | /*P2_DMDRESDATA2*/ | 1564 | /*P2_DMDRESDATA2*/ |
| 1562 | #define R0900_P2_DMDRESDATA2 0xf2cd | 1565 | #define R0900_P2_DMDRESDATA2 0xf2cd |
| 1563 | #define F0900_P2_DMDRES_DATA2 0xf2cd00ff | 1566 | #define F0900_P2_DMDRES_DATA2 0xf2cd00ff |
| 1564 | 1567 | ||
| 1565 | /*P2_DMDRESDATA1*/ | 1568 | /*P2_DMDRESDATA1*/ |
| 1566 | #define R0900_P2_DMDRESDATA1 0xf2ce | 1569 | #define R0900_P2_DMDRESDATA1 0xf2ce |
| 1567 | #define F0900_P2_DMDRES_DATA1 0xf2ce00ff | 1570 | #define F0900_P2_DMDRES_DATA1 0xf2ce00ff |
| 1568 | 1571 | ||
| 1569 | /*P2_DMDRESDATA0*/ | 1572 | /*P2_DMDRESDATA0*/ |
| 1570 | #define R0900_P2_DMDRESDATA0 0xf2cf | 1573 | #define R0900_P2_DMDRESDATA0 0xf2cf |
| 1571 | #define F0900_P2_DMDRES_DATA0 0xf2cf00ff | 1574 | #define F0900_P2_DMDRES_DATA0 0xf2cf00ff |
| 1572 | 1575 | ||
| 1573 | /*P2_FFEI1*/ | 1576 | /*P2_FFEI1*/ |
| 1574 | #define R0900_P2_FFEI1 0xf2d0 | 1577 | #define R0900_P2_FFEI1 0xf2d0 |
| 1575 | #define F0900_P2_FFE_ACCI1 0xf2d001ff | 1578 | #define F0900_P2_FFE_ACCI1 0xf2d001ff |
| 1576 | 1579 | ||
| 1577 | /*P2_FFEQ1*/ | 1580 | /*P2_FFEQ1*/ |
| 1578 | #define R0900_P2_FFEQ1 0xf2d1 | 1581 | #define R0900_P2_FFEQ1 0xf2d1 |
| 1579 | #define F0900_P2_FFE_ACCQ1 0xf2d101ff | 1582 | #define F0900_P2_FFE_ACCQ1 0xf2d101ff |
| 1580 | 1583 | ||
| 1581 | /*P2_FFEI2*/ | 1584 | /*P2_FFEI2*/ |
| 1582 | #define R0900_P2_FFEI2 0xf2d2 | 1585 | #define R0900_P2_FFEI2 0xf2d2 |
| 1583 | #define F0900_P2_FFE_ACCI2 0xf2d201ff | 1586 | #define F0900_P2_FFE_ACCI2 0xf2d201ff |
| 1584 | 1587 | ||
| 1585 | /*P2_FFEQ2*/ | 1588 | /*P2_FFEQ2*/ |
| 1586 | #define R0900_P2_FFEQ2 0xf2d3 | 1589 | #define R0900_P2_FFEQ2 0xf2d3 |
| 1587 | #define F0900_P2_FFE_ACCQ2 0xf2d301ff | 1590 | #define F0900_P2_FFE_ACCQ2 0xf2d301ff |
| 1588 | 1591 | ||
| 1589 | /*P2_FFEI3*/ | 1592 | /*P2_FFEI3*/ |
| 1590 | #define R0900_P2_FFEI3 0xf2d4 | 1593 | #define R0900_P2_FFEI3 0xf2d4 |
| 1591 | #define F0900_P2_FFE_ACCI3 0xf2d401ff | 1594 | #define F0900_P2_FFE_ACCI3 0xf2d401ff |
| 1592 | 1595 | ||
| 1593 | /*P2_FFEQ3*/ | 1596 | /*P2_FFEQ3*/ |
| 1594 | #define R0900_P2_FFEQ3 0xf2d5 | 1597 | #define R0900_P2_FFEQ3 0xf2d5 |
| 1595 | #define F0900_P2_FFE_ACCQ3 0xf2d501ff | 1598 | #define F0900_P2_FFE_ACCQ3 0xf2d501ff |
| 1596 | 1599 | ||
| 1597 | /*P2_FFEI4*/ | 1600 | /*P2_FFEI4*/ |
| 1598 | #define R0900_P2_FFEI4 0xf2d6 | 1601 | #define R0900_P2_FFEI4 0xf2d6 |
| 1599 | #define F0900_P2_FFE_ACCI4 0xf2d601ff | 1602 | #define F0900_P2_FFE_ACCI4 0xf2d601ff |
| 1600 | 1603 | ||
| 1601 | /*P2_FFEQ4*/ | 1604 | /*P2_FFEQ4*/ |
| 1602 | #define R0900_P2_FFEQ4 0xf2d7 | 1605 | #define R0900_P2_FFEQ4 0xf2d7 |
| 1603 | #define F0900_P2_FFE_ACCQ4 0xf2d701ff | 1606 | #define F0900_P2_FFE_ACCQ4 0xf2d701ff |
| 1604 | 1607 | ||
| 1605 | /*P2_FFECFG*/ | 1608 | /*P2_FFECFG*/ |
| 1606 | #define R0900_P2_FFECFG 0xf2d8 | 1609 | #define R0900_P2_FFECFG 0xf2d8 |
| 1607 | #define F0900_P2_EQUALFFE_ON 0xf2d80040 | 1610 | #define F0900_P2_EQUALFFE_ON 0xf2d80040 |
| 1608 | #define F0900_P2_EQUAL_USEDSYMB 0xf2d80030 | 1611 | #define F0900_P2_MU_EQUALFFE 0xf2d80007 |
| 1609 | #define F0900_P2_MU_EQUALFFE 0xf2d80007 | ||
| 1610 | 1612 | ||
| 1611 | /*P2_TNRCFG*/ | 1613 | /*P2_TNRCFG*/ |
| 1612 | #define R0900_P2_TNRCFG 0xf2e0 | 1614 | #define R0900_P2_TNRCFG 0xf2e0 |
| 1613 | #define F0900_P2_TUN_ACKFAIL 0xf2e00080 | 1615 | #define F0900_P2_TUN_ACKFAIL 0xf2e00080 |
| 1614 | #define F0900_P2_TUN_TYPE 0xf2e00070 | 1616 | #define F0900_P2_TUN_TYPE 0xf2e00070 |
| 1615 | #define F0900_P2_TUN_SECSTOP 0xf2e00008 | 1617 | #define F0900_P2_TUN_SECSTOP 0xf2e00008 |
| 1616 | #define F0900_P2_TUN_VCOSRCH 0xf2e00004 | 1618 | #define F0900_P2_TUN_VCOSRCH 0xf2e00004 |
| 1617 | #define F0900_P2_TUN_MADDRESS 0xf2e00003 | 1619 | #define F0900_P2_TUN_MADDRESS 0xf2e00003 |
| 1618 | 1620 | ||
| 1619 | /*P2_TNRCFG2*/ | 1621 | /*P2_TNRCFG2*/ |
| 1620 | #define R0900_P2_TNRCFG2 0xf2e1 | 1622 | #define R0900_P2_TNRCFG2 0xf2e1 |
| 1621 | #define F0900_P2_TUN_IQSWAP 0xf2e10080 | 1623 | #define F0900_P2_TUN_IQSWAP 0xf2e10080 |
| 1622 | #define F0900_P2_STB6110_STEP2MHZ 0xf2e10040 | 1624 | #define F0900_P2_DIS_BWCALC 0xf2e10004 |
| 1623 | #define F0900_P2_STB6120_DBLI2C 0xf2e10020 | 1625 | #define F0900_P2_SHORT_WAITSTATES 0xf2e10002 |
| 1624 | #define F0900_P2_DIS_FCCK 0xf2e10010 | ||
| 1625 | #define F0900_P2_DIS_LPEN 0xf2e10008 | ||
| 1626 | #define F0900_P2_DIS_BWCALC 0xf2e10004 | ||
| 1627 | #define F0900_P2_SHORT_WAITSTATES 0xf2e10002 | ||
| 1628 | #define F0900_P2_DIS_2BWAGC1 0xf2e10001 | ||
| 1629 | 1626 | ||
| 1630 | /*P2_TNRXTAL*/ | 1627 | /*P2_TNRXTAL*/ |
| 1631 | #define R0900_P2_TNRXTAL 0xf2e4 | 1628 | #define R0900_P2_TNRXTAL 0xf2e4 |
| 1632 | #define F0900_P2_TUN_MCLKDECIMAL 0xf2e400e0 | 1629 | #define F0900_P2_TUN_XTALFREQ 0xf2e4001f |
| 1633 | #define F0900_P2_TUN_XTALFREQ 0xf2e4001f | ||
| 1634 | 1630 | ||
| 1635 | /*P2_TNRSTEPS*/ | 1631 | /*P2_TNRSTEPS*/ |
| 1636 | #define R0900_P2_TNRSTEPS 0xf2e7 | 1632 | #define R0900_P2_TNRSTEPS 0xf2e7 |
| 1637 | #define F0900_P2_TUNER_BW1P6 0xf2e70080 | 1633 | #define F0900_P2_TUNER_BW0P125 0xf2e70080 |
| 1638 | #define F0900_P2_BWINC_OFFSET 0xf2e70070 | 1634 | #define F0900_P2_BWINC_OFFSET 0xf2e70170 |
| 1639 | #define F0900_P2_SOFTSTEP_RNG 0xf2e70008 | 1635 | #define F0900_P2_SOFTSTEP_RNG 0xf2e70008 |
| 1640 | #define F0900_P2_TUN_BWOFFSET 0xf2e70107 | 1636 | #define F0900_P2_TUN_BWOFFSET 0xf2e70007 |
| 1641 | 1637 | ||
| 1642 | /*P2_TNRGAIN*/ | 1638 | /*P2_TNRGAIN*/ |
| 1643 | #define R0900_P2_TNRGAIN 0xf2e8 | 1639 | #define R0900_P2_TNRGAIN 0xf2e8 |
| 1644 | #define F0900_P2_TUN_KDIVEN 0xf2e800c0 | 1640 | #define F0900_P2_TUN_KDIVEN 0xf2e800c0 |
| 1645 | #define F0900_P2_STB6X00_OCK 0xf2e80030 | 1641 | #define F0900_P2_STB6X00_OCK 0xf2e80030 |
| 1646 | #define F0900_P2_TUN_GAIN 0xf2e8000f | 1642 | #define F0900_P2_TUN_GAIN 0xf2e8000f |
| 1647 | 1643 | ||
| 1648 | /*P2_TNRRF1*/ | 1644 | /*P2_TNRRF1*/ |
| 1649 | #define R0900_P2_TNRRF1 0xf2e9 | 1645 | #define R0900_P2_TNRRF1 0xf2e9 |
| 1650 | #define F0900_P2_TUN_RFFREQ2 0xf2e900ff | 1646 | #define F0900_P2_TUN_RFFREQ2 0xf2e900ff |
| 1651 | 1647 | ||
| 1652 | /*P2_TNRRF0*/ | 1648 | /*P2_TNRRF0*/ |
| 1653 | #define R0900_P2_TNRRF0 0xf2ea | 1649 | #define R0900_P2_TNRRF0 0xf2ea |
| 1654 | #define F0900_P2_TUN_RFFREQ1 0xf2ea00ff | 1650 | #define F0900_P2_TUN_RFFREQ1 0xf2ea00ff |
| 1655 | 1651 | ||
| 1656 | /*P2_TNRBW*/ | 1652 | /*P2_TNRBW*/ |
| 1657 | #define R0900_P2_TNRBW 0xf2eb | 1653 | #define R0900_P2_TNRBW 0xf2eb |
| 1658 | #define F0900_P2_TUN_RFFREQ0 0xf2eb00c0 | 1654 | #define F0900_P2_TUN_RFFREQ0 0xf2eb00c0 |
| 1659 | #define F0900_P2_TUN_BW 0xf2eb003f | 1655 | #define F0900_P2_TUN_BW 0xf2eb003f |
| 1660 | 1656 | ||
| 1661 | /*P2_TNRADJ*/ | 1657 | /*P2_TNRADJ*/ |
| 1662 | #define R0900_P2_TNRADJ 0xf2ec | 1658 | #define R0900_P2_TNRADJ 0xf2ec |
| 1663 | #define F0900_P2_STB61X0_RCLK 0xf2ec0080 | 1659 | #define F0900_P2_STB61X0_CALTIME 0xf2ec0040 |
| 1664 | #define F0900_P2_STB61X0_CALTIME 0xf2ec0040 | ||
| 1665 | #define F0900_P2_STB6X00_DLB 0xf2ec0038 | ||
| 1666 | #define F0900_P2_STB6000_FCL 0xf2ec0007 | ||
| 1667 | 1660 | ||
| 1668 | /*P2_TNRCTL2*/ | 1661 | /*P2_TNRCTL2*/ |
| 1669 | #define R0900_P2_TNRCTL2 0xf2ed | 1662 | #define R0900_P2_TNRCTL2 0xf2ed |
| 1670 | #define F0900_P2_STB61X0_LCP1_RCCKOFF 0xf2ed0080 | 1663 | #define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080 |
| 1671 | #define F0900_P2_STB61X0_LCP0 0xf2ed0040 | 1664 | #define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040 |
| 1672 | #define F0900_P2_STB61X0_XTOUT_RFOUTS 0xf2ed0020 | 1665 | #define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020 |
| 1673 | #define F0900_P2_STB61X0_XTON_MCKDV 0xf2ed0010 | 1666 | #define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010 |
| 1674 | #define F0900_P2_STB61X0_CALOFF_DCOFF 0xf2ed0008 | 1667 | #define F0900_P2_STB61X0_CALOFF 0xf2ed0008 |
| 1675 | #define F0900_P2_STB6110_LPT 0xf2ed0004 | 1668 | #define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004 |
| 1676 | #define F0900_P2_STB6110_RX 0xf2ed0002 | 1669 | #define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002 |
| 1677 | #define F0900_P2_STB6110_SYN 0xf2ed0001 | 1670 | #define F0900_P2_STB6XX0_SYN 0xf2ed0001 |
| 1678 | 1671 | ||
| 1679 | /*P2_TNRCFG3*/ | 1672 | /*P2_TNRCFG3*/ |
| 1680 | #define R0900_P2_TNRCFG3 0xf2ee | 1673 | #define R0900_P2_TNRCFG3 0xf2ee |
| 1681 | #define F0900_P2_STB6120_DISCTRL1 0xf2ee0080 | 1674 | #define F0900_P2_TUN_PLLFREQ 0xf2ee001c |
| 1682 | #define F0900_P2_STB6120_INVORDER 0xf2ee0040 | 1675 | #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003 |
| 1683 | #define F0900_P2_STB6120_ENCTRL6 0xf2ee0020 | ||
| 1684 | #define F0900_P2_TUN_PLLFREQ 0xf2ee001c | ||
| 1685 | #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003 | ||
| 1686 | 1676 | ||
| 1687 | /*P2_TNRLAUNCH*/ | 1677 | /*P2_TNRLAUNCH*/ |
| 1688 | #define R0900_P2_TNRLAUNCH 0xf2f0 | 1678 | #define R0900_P2_TNRLAUNCH 0xf2f0 |
| 1689 | 1679 | ||
| 1690 | /*P2_TNRLD*/ | 1680 | /*P2_TNRLD*/ |
| 1691 | #define R0900_P2_TNRLD 0xf2f0 | 1681 | #define R0900_P2_TNRLD 0xf2f0 |
| 1692 | #define F0900_P2_TUNLD_VCOING 0xf2f00080 | 1682 | #define F0900_P2_TUNLD_VCOING 0xf2f00080 |
| 1693 | #define F0900_P2_TUN_REG1FAIL 0xf2f00040 | 1683 | #define F0900_P2_TUN_REG1FAIL 0xf2f00040 |
| 1694 | #define F0900_P2_TUN_REG2FAIL 0xf2f00020 | 1684 | #define F0900_P2_TUN_REG2FAIL 0xf2f00020 |
| 1695 | #define F0900_P2_TUN_REG3FAIL 0xf2f00010 | 1685 | #define F0900_P2_TUN_REG3FAIL 0xf2f00010 |
| 1696 | #define F0900_P2_TUN_REG4FAIL 0xf2f00008 | 1686 | #define F0900_P2_TUN_REG4FAIL 0xf2f00008 |
| 1697 | #define F0900_P2_TUN_REG5FAIL 0xf2f00004 | 1687 | #define F0900_P2_TUN_REG5FAIL 0xf2f00004 |
| 1698 | #define F0900_P2_TUN_BWING 0xf2f00002 | 1688 | #define F0900_P2_TUN_BWING 0xf2f00002 |
| 1699 | #define F0900_P2_TUN_LOCKED 0xf2f00001 | 1689 | #define F0900_P2_TUN_LOCKED 0xf2f00001 |
| 1700 | 1690 | ||
| 1701 | /*P2_TNROBSL*/ | 1691 | /*P2_TNROBSL*/ |
| 1702 | #define R0900_P2_TNROBSL 0xf2f6 | 1692 | #define R0900_P2_TNROBSL 0xf2f6 |
| 1703 | #define F0900_P2_TUN_I2CABORTED 0xf2f60080 | 1693 | #define F0900_P2_TUN_I2CABORTED 0xf2f60080 |
| 1704 | #define F0900_P2_TUN_LPEN 0xf2f60040 | 1694 | #define F0900_P2_TUN_LPEN 0xf2f60040 |
| 1705 | #define F0900_P2_TUN_FCCK 0xf2f60020 | 1695 | #define F0900_P2_TUN_FCCK 0xf2f60020 |
| 1706 | #define F0900_P2_TUN_I2CLOCKED 0xf2f60010 | 1696 | #define F0900_P2_TUN_I2CLOCKED 0xf2f60010 |
| 1707 | #define F0900_P2_TUN_PROGDONE 0xf2f6000c | 1697 | #define F0900_P2_TUN_PROGDONE 0xf2f6000c |
| 1708 | #define F0900_P2_TUN_RFRESTE1 0xf2f60003 | 1698 | #define F0900_P2_TUN_RFRESTE1 0xf2f60003 |
| 1709 | 1699 | ||
| 1710 | /*P2_TNRRESTE*/ | 1700 | /*P2_TNRRESTE*/ |
| 1711 | #define R0900_P2_TNRRESTE 0xf2f7 | 1701 | #define R0900_P2_TNRRESTE 0xf2f7 |
| 1712 | #define F0900_P2_TUN_RFRESTE0 0xf2f700ff | 1702 | #define F0900_P2_TUN_RFRESTE0 0xf2f700ff |
| 1713 | 1703 | ||
| 1714 | /*P2_SMAPCOEF7*/ | 1704 | /*P2_SMAPCOEF7*/ |
| 1715 | #define R0900_P2_SMAPCOEF7 0xf300 | 1705 | #define R0900_P2_SMAPCOEF7 0xf300 |
| 1716 | #define F0900_P2_DIS_QSCALE 0xf3000080 | 1706 | #define F0900_P2_DIS_QSCALE 0xf3000080 |
| 1717 | #define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f | 1707 | #define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f |
| 1718 | 1708 | ||
| 1719 | /*P2_SMAPCOEF6*/ | 1709 | /*P2_SMAPCOEF6*/ |
| 1720 | #define R0900_P2_SMAPCOEF6 0xf301 | 1710 | #define R0900_P2_SMAPCOEF6 0xf301 |
| 1721 | #define F0900_P2_DIS_NEWSCALE 0xf3010008 | 1711 | #define F0900_P2_ADJ_8PSKLLR1 0xf3010004 |
| 1722 | #define F0900_P2_ADJ_8PSKLLR1 0xf3010004 | 1712 | #define F0900_P2_OLD_8PSKLLR1 0xf3010002 |
| 1723 | #define F0900_P2_OLD_8PSKLLR1 0xf3010002 | 1713 | #define F0900_P2_DIS_AB8PSK 0xf3010001 |
| 1724 | #define F0900_P2_DIS_AB8PSK 0xf3010001 | ||
| 1725 | 1714 | ||
| 1726 | /*P2_SMAPCOEF5*/ | 1715 | /*P2_SMAPCOEF5*/ |
| 1727 | #define R0900_P2_SMAPCOEF5 0xf302 | 1716 | #define R0900_P2_SMAPCOEF5 0xf302 |
| 1728 | #define F0900_P2_DIS_8SCALE 0xf3020080 | 1717 | #define F0900_P2_DIS_8SCALE 0xf3020080 |
| 1729 | #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f | 1718 | #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f |
| 1719 | |||
| 1720 | /*P2_NCO2MAX1*/ | ||
| 1721 | #define R0900_P2_NCO2MAX1 0xf314 | ||
| 1722 | #define F0900_P2_TETA2_MAXVABS1 0xf31400ff | ||
| 1723 | |||
| 1724 | /*P2_NCO2MAX0*/ | ||
| 1725 | #define R0900_P2_NCO2MAX0 0xf315 | ||
| 1726 | #define F0900_P2_TETA2_MAXVABS0 0xf31500ff | ||
| 1727 | |||
| 1728 | /*P2_NCO2FR1*/ | ||
| 1729 | #define R0900_P2_NCO2FR1 0xf316 | ||
| 1730 | #define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff | ||
| 1731 | |||
| 1732 | /*P2_NCO2FR0*/ | ||
| 1733 | #define R0900_P2_NCO2FR0 0xf317 | ||
| 1734 | #define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff | ||
| 1735 | |||
| 1736 | /*P2_CFR2AVRGE1*/ | ||
| 1737 | #define R0900_P2_CFR2AVRGE1 0xf318 | ||
| 1738 | #define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff | ||
| 1739 | |||
| 1740 | /*P2_CFR2AVRGE0*/ | ||
| 1741 | #define R0900_P2_CFR2AVRGE0 0xf319 | ||
| 1742 | #define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff | ||
| 1730 | 1743 | ||
| 1731 | /*P2_DMDPLHSTAT*/ | 1744 | /*P2_DMDPLHSTAT*/ |
| 1732 | #define R0900_P2_DMDPLHSTAT 0xf320 | 1745 | #define R0900_P2_DMDPLHSTAT 0xf320 |
| 1733 | #define F0900_P2_PLH_STATISTIC 0xf32000ff | 1746 | #define F0900_P2_PLH_STATISTIC 0xf32000ff |
| 1734 | 1747 | ||
| 1735 | /*P2_LOCKTIME3*/ | 1748 | /*P2_LOCKTIME3*/ |
| 1736 | #define R0900_P2_LOCKTIME3 0xf322 | 1749 | #define R0900_P2_LOCKTIME3 0xf322 |
| 1737 | #define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff | 1750 | #define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff |
| 1738 | 1751 | ||
| 1739 | /*P2_LOCKTIME2*/ | 1752 | /*P2_LOCKTIME2*/ |
| 1740 | #define R0900_P2_LOCKTIME2 0xf323 | 1753 | #define R0900_P2_LOCKTIME2 0xf323 |
| 1741 | #define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff | 1754 | #define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff |
| 1742 | 1755 | ||
| 1743 | /*P2_LOCKTIME1*/ | 1756 | /*P2_LOCKTIME1*/ |
| 1744 | #define R0900_P2_LOCKTIME1 0xf324 | 1757 | #define R0900_P2_LOCKTIME1 0xf324 |
| 1745 | #define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff | 1758 | #define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff |
| 1746 | 1759 | ||
| 1747 | /*P2_LOCKTIME0*/ | 1760 | /*P2_LOCKTIME0*/ |
| 1748 | #define R0900_P2_LOCKTIME0 0xf325 | 1761 | #define R0900_P2_LOCKTIME0 0xf325 |
| 1749 | #define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff | 1762 | #define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff |
| 1750 | 1763 | ||
| 1751 | /*P2_VITSCALE*/ | 1764 | /*P2_VITSCALE*/ |
| 1752 | #define R0900_P2_VITSCALE 0xf332 | 1765 | #define R0900_P2_VITSCALE 0xf332 |
| 1753 | #define F0900_P2_NVTH_NOSRANGE 0xf3320080 | 1766 | #define F0900_P2_NVTH_NOSRANGE 0xf3320080 |
| 1754 | #define F0900_P2_VERROR_MAXMODE 0xf3320040 | 1767 | #define F0900_P2_VERROR_MAXMODE 0xf3320040 |
| 1755 | #define F0900_P2_KDIV_MODE 0xf3320030 | 1768 | #define F0900_P2_NSLOWSN_LOCKED 0xf3320008 |
| 1756 | #define F0900_P2_NSLOWSN_LOCKED 0xf3320008 | 1769 | #define F0900_P2_DIS_RSFLOCK 0xf3320002 |
| 1757 | #define F0900_P2_DELOCK_PRFLOSS 0xf3320004 | ||
| 1758 | #define F0900_P2_DIS_RSFLOCK 0xf3320002 | ||
| 1759 | 1770 | ||
| 1760 | /*P2_FECM*/ | 1771 | /*P2_FECM*/ |
| 1761 | #define R0900_P2_FECM 0xf333 | 1772 | #define R0900_P2_FECM 0xf333 |
| 1762 | #define F0900_P2_DSS_DVB 0xf3330080 | 1773 | #define F0900_P2_DSS_DVB 0xf3330080 |
| 1763 | #define F0900_P2_DEMOD_BYPASS 0xf3330040 | 1774 | #define F0900_P2_DSS_SRCH 0xf3330010 |
| 1764 | #define F0900_P2_CMP_SLOWMODE 0xf3330020 | 1775 | #define F0900_P2_SYNCVIT 0xf3330002 |
| 1765 | #define F0900_P2_DSS_SRCH 0xf3330010 | 1776 | #define F0900_P2_IQINV 0xf3330001 |
| 1766 | #define F0900_P2_DIFF_MODEVIT 0xf3330004 | ||
| 1767 | #define F0900_P2_SYNCVIT 0xf3330002 | ||
| 1768 | #define F0900_P2_IQINV 0xf3330001 | ||
| 1769 | 1777 | ||
| 1770 | /*P2_VTH12*/ | 1778 | /*P2_VTH12*/ |
| 1771 | #define R0900_P2_VTH12 0xf334 | 1779 | #define R0900_P2_VTH12 0xf334 |
| 1772 | #define F0900_P2_VTH12 0xf33400ff | 1780 | #define F0900_P2_VTH12 0xf33400ff |
| 1773 | 1781 | ||
| 1774 | /*P2_VTH23*/ | 1782 | /*P2_VTH23*/ |
| 1775 | #define R0900_P2_VTH23 0xf335 | 1783 | #define R0900_P2_VTH23 0xf335 |
| 1776 | #define F0900_P2_VTH23 0xf33500ff | 1784 | #define F0900_P2_VTH23 0xf33500ff |
| 1777 | 1785 | ||
| 1778 | /*P2_VTH34*/ | 1786 | /*P2_VTH34*/ |
| 1779 | #define R0900_P2_VTH34 0xf336 | 1787 | #define R0900_P2_VTH34 0xf336 |
| 1780 | #define F0900_P2_VTH34 0xf33600ff | 1788 | #define F0900_P2_VTH34 0xf33600ff |
| 1781 | 1789 | ||
| 1782 | /*P2_VTH56*/ | 1790 | /*P2_VTH56*/ |
| 1783 | #define R0900_P2_VTH56 0xf337 | 1791 | #define R0900_P2_VTH56 0xf337 |
| 1784 | #define F0900_P2_VTH56 0xf33700ff | 1792 | #define F0900_P2_VTH56 0xf33700ff |
| 1785 | 1793 | ||
| 1786 | /*P2_VTH67*/ | 1794 | /*P2_VTH67*/ |
| 1787 | #define R0900_P2_VTH67 0xf338 | 1795 | #define R0900_P2_VTH67 0xf338 |
| 1788 | #define F0900_P2_VTH67 0xf33800ff | 1796 | #define F0900_P2_VTH67 0xf33800ff |
| 1789 | 1797 | ||
| 1790 | /*P2_VTH78*/ | 1798 | /*P2_VTH78*/ |
| 1791 | #define R0900_P2_VTH78 0xf339 | 1799 | #define R0900_P2_VTH78 0xf339 |
| 1792 | #define F0900_P2_VTH78 0xf33900ff | 1800 | #define F0900_P2_VTH78 0xf33900ff |
| 1793 | 1801 | ||
| 1794 | /*P2_VITCURPUN*/ | 1802 | /*P2_VITCURPUN*/ |
| 1795 | #define R0900_P2_VITCURPUN 0xf33a | 1803 | #define R0900_P2_VITCURPUN 0xf33a |
| 1796 | #define F0900_P2_VIT_MAPPING 0xf33a00e0 | 1804 | #define F0900_P2_VIT_CURPUN 0xf33a001f |
| 1797 | #define F0900_P2_VIT_CURPUN 0xf33a001f | ||
| 1798 | 1805 | ||
| 1799 | /*P2_VERROR*/ | 1806 | /*P2_VERROR*/ |
| 1800 | #define R0900_P2_VERROR 0xf33b | 1807 | #define R0900_P2_VERROR 0xf33b |
| 1801 | #define F0900_P2_REGERR_VIT 0xf33b00ff | 1808 | #define F0900_P2_REGERR_VIT 0xf33b00ff |
| 1802 | 1809 | ||
| 1803 | /*P2_PRVIT*/ | 1810 | /*P2_PRVIT*/ |
| 1804 | #define R0900_P2_PRVIT 0xf33c | 1811 | #define R0900_P2_PRVIT 0xf33c |
| 1805 | #define F0900_P2_DIS_VTHLOCK 0xf33c0040 | 1812 | #define F0900_P2_DIS_VTHLOCK 0xf33c0040 |
| 1806 | #define F0900_P2_E7_8VIT 0xf33c0020 | 1813 | #define F0900_P2_E7_8VIT 0xf33c0020 |
| 1807 | #define F0900_P2_E6_7VIT 0xf33c0010 | 1814 | #define F0900_P2_E6_7VIT 0xf33c0010 |
| 1808 | #define F0900_P2_E5_6VIT 0xf33c0008 | 1815 | #define F0900_P2_E5_6VIT 0xf33c0008 |
| 1809 | #define F0900_P2_E3_4VIT 0xf33c0004 | 1816 | #define F0900_P2_E3_4VIT 0xf33c0004 |
| 1810 | #define F0900_P2_E2_3VIT 0xf33c0002 | 1817 | #define F0900_P2_E2_3VIT 0xf33c0002 |
| 1811 | #define F0900_P2_E1_2VIT 0xf33c0001 | 1818 | #define F0900_P2_E1_2VIT 0xf33c0001 |
| 1812 | 1819 | ||
| 1813 | /*P2_VAVSRVIT*/ | 1820 | /*P2_VAVSRVIT*/ |
| 1814 | #define R0900_P2_VAVSRVIT 0xf33d | 1821 | #define R0900_P2_VAVSRVIT 0xf33d |
| 1815 | #define F0900_P2_AMVIT 0xf33d0080 | 1822 | #define F0900_P2_AMVIT 0xf33d0080 |
| 1816 | #define F0900_P2_FROZENVIT 0xf33d0040 | 1823 | #define F0900_P2_FROZENVIT 0xf33d0040 |
| 1817 | #define F0900_P2_SNVIT 0xf33d0030 | 1824 | #define F0900_P2_SNVIT 0xf33d0030 |
| 1818 | #define F0900_P2_TOVVIT 0xf33d000c | 1825 | #define F0900_P2_TOVVIT 0xf33d000c |
| 1819 | #define F0900_P2_HYPVIT 0xf33d0003 | 1826 | #define F0900_P2_HYPVIT 0xf33d0003 |
| 1820 | 1827 | ||
| 1821 | /*P2_VSTATUSVIT*/ | 1828 | /*P2_VSTATUSVIT*/ |
| 1822 | #define R0900_P2_VSTATUSVIT 0xf33e | 1829 | #define R0900_P2_VSTATUSVIT 0xf33e |
| 1823 | #define F0900_P2_VITERBI_ON 0xf33e0080 | 1830 | #define F0900_P2_PRFVIT 0xf33e0010 |
| 1824 | #define F0900_P2_END_LOOPVIT 0xf33e0040 | 1831 | #define F0900_P2_LOCKEDVIT 0xf33e0008 |
| 1825 | #define F0900_P2_VITERBI_DEPRF 0xf33e0020 | ||
| 1826 | #define F0900_P2_PRFVIT 0xf33e0010 | ||
| 1827 | #define F0900_P2_LOCKEDVIT 0xf33e0008 | ||
| 1828 | #define F0900_P2_VITERBI_DELOCK 0xf33e0004 | ||
| 1829 | #define F0900_P2_VIT_DEMODSEL 0xf33e0002 | ||
| 1830 | #define F0900_P2_VITERBI_COMPOUT 0xf33e0001 | ||
| 1831 | 1832 | ||
| 1832 | /*P2_VTHINUSE*/ | 1833 | /*P2_VTHINUSE*/ |
| 1833 | #define R0900_P2_VTHINUSE 0xf33f | 1834 | #define R0900_P2_VTHINUSE 0xf33f |
| 1834 | #define F0900_P2_VIT_INUSE 0xf33f00ff | 1835 | #define F0900_P2_VIT_INUSE 0xf33f00ff |
| 1835 | 1836 | ||
| 1836 | /*P2_KDIV12*/ | 1837 | /*P2_KDIV12*/ |
| 1837 | #define R0900_P2_KDIV12 0xf340 | 1838 | #define R0900_P2_KDIV12 0xf340 |
| 1838 | #define F0900_P2_KDIV12_MANUAL 0xf3400080 | 1839 | #define F0900_P2_K_DIVIDER_12 0xf340007f |
| 1839 | #define F0900_P2_K_DIVIDER_12 0xf340007f | ||
| 1840 | 1840 | ||
| 1841 | /*P2_KDIV23*/ | 1841 | /*P2_KDIV23*/ |
| 1842 | #define R0900_P2_KDIV23 0xf341 | 1842 | #define R0900_P2_KDIV23 0xf341 |
| 1843 | #define F0900_P2_KDIV23_MANUAL 0xf3410080 | 1843 | #define F0900_P2_K_DIVIDER_23 0xf341007f |
| 1844 | #define F0900_P2_K_DIVIDER_23 0xf341007f | ||
| 1845 | 1844 | ||
| 1846 | /*P2_KDIV34*/ | 1845 | /*P2_KDIV34*/ |
| 1847 | #define R0900_P2_KDIV34 0xf342 | 1846 | #define R0900_P2_KDIV34 0xf342 |
| 1848 | #define F0900_P2_KDIV34_MANUAL 0xf3420080 | 1847 | #define F0900_P2_K_DIVIDER_34 0xf342007f |
| 1849 | #define F0900_P2_K_DIVIDER_34 0xf342007f | ||
| 1850 | 1848 | ||
| 1851 | /*P2_KDIV56*/ | 1849 | /*P2_KDIV56*/ |
| 1852 | #define R0900_P2_KDIV56 0xf343 | 1850 | #define R0900_P2_KDIV56 0xf343 |
| 1853 | #define F0900_P2_KDIV56_MANUAL 0xf3430080 | 1851 | #define F0900_P2_K_DIVIDER_56 0xf343007f |
| 1854 | #define F0900_P2_K_DIVIDER_56 0xf343007f | ||
| 1855 | 1852 | ||
| 1856 | /*P2_KDIV67*/ | 1853 | /*P2_KDIV67*/ |
| 1857 | #define R0900_P2_KDIV67 0xf344 | 1854 | #define R0900_P2_KDIV67 0xf344 |
| 1858 | #define F0900_P2_KDIV67_MANUAL 0xf3440080 | 1855 | #define F0900_P2_K_DIVIDER_67 0xf344007f |
| 1859 | #define F0900_P2_K_DIVIDER_67 0xf344007f | ||
| 1860 | 1856 | ||
| 1861 | /*P2_KDIV78*/ | 1857 | /*P2_KDIV78*/ |
| 1862 | #define R0900_P2_KDIV78 0xf345 | 1858 | #define R0900_P2_KDIV78 0xf345 |
| 1863 | #define F0900_P2_KDIV78_MANUAL 0xf3450080 | 1859 | #define F0900_P2_K_DIVIDER_78 0xf345007f |
| 1864 | #define F0900_P2_K_DIVIDER_78 0xf345007f | ||
| 1865 | 1860 | ||
| 1866 | /*P2_PDELCTRL1*/ | 1861 | /*P2_PDELCTRL1*/ |
| 1867 | #define R0900_P2_PDELCTRL1 0xf350 | 1862 | #define R0900_P2_PDELCTRL1 0xf350 |
| 1868 | #define F0900_P2_INV_MISMASK 0xf3500080 | 1863 | #define F0900_P2_INV_MISMASK 0xf3500080 |
| 1869 | #define F0900_P2_FORCE_ACCEPTED 0xf3500040 | 1864 | #define F0900_P2_FILTER_EN 0xf3500020 |
| 1870 | #define F0900_P2_FILTER_EN 0xf3500020 | 1865 | #define F0900_P2_EN_MIS00 0xf3500002 |
| 1871 | #define F0900_P2_FORCE_PKTDELINUSE 0xf3500010 | 1866 | #define F0900_P2_ALGOSWRST 0xf3500001 |
| 1872 | #define F0900_P2_HYSTEN 0xf3500008 | ||
| 1873 | #define F0900_P2_HYSTSWRST 0xf3500004 | ||
| 1874 | #define F0900_P2_EN_MIS00 0xf3500002 | ||
| 1875 | #define F0900_P2_ALGOSWRST 0xf3500001 | ||
| 1876 | 1867 | ||
| 1877 | /*P2_PDELCTRL2*/ | 1868 | /*P2_PDELCTRL2*/ |
| 1878 | #define R0900_P2_PDELCTRL2 0xf351 | 1869 | #define R0900_P2_PDELCTRL2 0xf351 |
| 1879 | #define F0900_P2_FORCE_CONTINUOUS 0xf3510080 | 1870 | #define F0900_P2_RESET_UPKO_COUNT 0xf3510040 |
| 1880 | #define F0900_P2_RESET_UPKO_COUNT 0xf3510040 | 1871 | #define F0900_P2_FRAME_MODE 0xf3510002 |
| 1881 | #define F0900_P2_USER_PKTDELIN_NB 0xf3510020 | 1872 | #define F0900_P2_NOBCHERRFLG_USE 0xf3510001 |
| 1882 | #define F0900_P2_FORCE_LOCKED 0xf3510010 | ||
| 1883 | #define F0900_P2_DATA_UNBBSCRAM 0xf3510008 | ||
| 1884 | #define F0900_P2_FORCE_LONGPKT 0xf3510004 | ||
| 1885 | #define F0900_P2_FRAME_MODE 0xf3510002 | ||
| 1886 | 1873 | ||
| 1887 | /*P2_HYSTTHRESH*/ | 1874 | /*P2_HYSTTHRESH*/ |
| 1888 | #define R0900_P2_HYSTTHRESH 0xf354 | 1875 | #define R0900_P2_HYSTTHRESH 0xf354 |
| 1889 | #define F0900_P2_UNLCK_THRESH 0xf35400f0 | 1876 | #define F0900_P2_UNLCK_THRESH 0xf35400f0 |
| 1890 | #define F0900_P2_DELIN_LCK_THRESH 0xf354000f | 1877 | #define F0900_P2_DELIN_LCK_THRESH 0xf354000f |
| 1891 | 1878 | ||
| 1892 | /*P2_ISIENTRY*/ | 1879 | /*P2_ISIENTRY*/ |
| 1893 | #define R0900_P2_ISIENTRY 0xf35e | 1880 | #define R0900_P2_ISIENTRY 0xf35e |
| 1894 | #define F0900_P2_ISI_ENTRY 0xf35e00ff | 1881 | #define F0900_P2_ISI_ENTRY 0xf35e00ff |
| 1895 | 1882 | ||
| 1896 | /*P2_ISIBITENA*/ | 1883 | /*P2_ISIBITENA*/ |
| 1897 | #define R0900_P2_ISIBITENA 0xf35f | 1884 | #define R0900_P2_ISIBITENA 0xf35f |
| 1898 | #define F0900_P2_ISI_BIT_EN 0xf35f00ff | 1885 | #define F0900_P2_ISI_BIT_EN 0xf35f00ff |
| 1899 | 1886 | ||
| 1900 | /*P2_MATSTR1*/ | 1887 | /*P2_MATSTR1*/ |
| 1901 | #define R0900_P2_MATSTR1 0xf360 | 1888 | #define R0900_P2_MATSTR1 0xf360 |
| 1902 | #define F0900_P2_MATYPE_CURRENT1 0xf36000ff | 1889 | #define F0900_P2_MATYPE_CURRENT1 0xf36000ff |
| 1903 | 1890 | ||
| 1904 | /*P2_MATSTR0*/ | 1891 | /*P2_MATSTR0*/ |
| 1905 | #define R0900_P2_MATSTR0 0xf361 | 1892 | #define R0900_P2_MATSTR0 0xf361 |
| 1906 | #define F0900_P2_MATYPE_CURRENT0 0xf36100ff | 1893 | #define F0900_P2_MATYPE_CURRENT0 0xf36100ff |
| 1907 | 1894 | ||
| 1908 | /*P2_UPLSTR1*/ | 1895 | /*P2_UPLSTR1*/ |
| 1909 | #define R0900_P2_UPLSTR1 0xf362 | 1896 | #define R0900_P2_UPLSTR1 0xf362 |
| 1910 | #define F0900_P2_UPL_CURRENT1 0xf36200ff | 1897 | #define F0900_P2_UPL_CURRENT1 0xf36200ff |
| 1911 | 1898 | ||
| 1912 | /*P2_UPLSTR0*/ | 1899 | /*P2_UPLSTR0*/ |
| 1913 | #define R0900_P2_UPLSTR0 0xf363 | 1900 | #define R0900_P2_UPLSTR0 0xf363 |
| 1914 | #define F0900_P2_UPL_CURRENT0 0xf36300ff | 1901 | #define F0900_P2_UPL_CURRENT0 0xf36300ff |
| 1915 | 1902 | ||
| 1916 | /*P2_DFLSTR1*/ | 1903 | /*P2_DFLSTR1*/ |
| 1917 | #define R0900_P2_DFLSTR1 0xf364 | 1904 | #define R0900_P2_DFLSTR1 0xf364 |
| 1918 | #define F0900_P2_DFL_CURRENT1 0xf36400ff | 1905 | #define F0900_P2_DFL_CURRENT1 0xf36400ff |
| 1919 | 1906 | ||
| 1920 | /*P2_DFLSTR0*/ | 1907 | /*P2_DFLSTR0*/ |
| 1921 | #define R0900_P2_DFLSTR0 0xf365 | 1908 | #define R0900_P2_DFLSTR0 0xf365 |
| 1922 | #define F0900_P2_DFL_CURRENT0 0xf36500ff | 1909 | #define F0900_P2_DFL_CURRENT0 0xf36500ff |
| 1923 | 1910 | ||
| 1924 | /*P2_SYNCSTR*/ | 1911 | /*P2_SYNCSTR*/ |
| 1925 | #define R0900_P2_SYNCSTR 0xf366 | 1912 | #define R0900_P2_SYNCSTR 0xf366 |
| 1926 | #define F0900_P2_SYNC_CURRENT 0xf36600ff | 1913 | #define F0900_P2_SYNC_CURRENT 0xf36600ff |
| 1927 | 1914 | ||
| 1928 | /*P2_SYNCDSTR1*/ | 1915 | /*P2_SYNCDSTR1*/ |
| 1929 | #define R0900_P2_SYNCDSTR1 0xf367 | 1916 | #define R0900_P2_SYNCDSTR1 0xf367 |
| 1930 | #define F0900_P2_SYNCD_CURRENT1 0xf36700ff | 1917 | #define F0900_P2_SYNCD_CURRENT1 0xf36700ff |
| 1931 | 1918 | ||
| 1932 | /*P2_SYNCDSTR0*/ | 1919 | /*P2_SYNCDSTR0*/ |
| 1933 | #define R0900_P2_SYNCDSTR0 0xf368 | 1920 | #define R0900_P2_SYNCDSTR0 0xf368 |
| 1934 | #define F0900_P2_SYNCD_CURRENT0 0xf36800ff | 1921 | #define F0900_P2_SYNCD_CURRENT0 0xf36800ff |
| 1935 | 1922 | ||
| 1936 | /*P2_PDELSTATUS1*/ | 1923 | /*P2_PDELSTATUS1*/ |
| 1937 | #define R0900_P2_PDELSTATUS1 0xf369 | 1924 | #define R0900_P2_PDELSTATUS1 0xf369 |
| 1938 | #define F0900_P2_PKTDELIN_DELOCK 0xf3690080 | 1925 | #define F0900_P2_PKTDELIN_DELOCK 0xf3690080 |
| 1939 | #define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040 | 1926 | #define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040 |
| 1940 | #define F0900_P2_CONTINUOUS_STREAM 0xf3690020 | 1927 | #define F0900_P2_CONTINUOUS_STREAM 0xf3690020 |
| 1941 | #define F0900_P2_UNACCEPTED_STREAM 0xf3690010 | 1928 | #define F0900_P2_UNACCEPTED_STREAM 0xf3690010 |
| 1942 | #define F0900_P2_BCH_ERROR_FLAG 0xf3690008 | 1929 | #define F0900_P2_BCH_ERROR_FLAG 0xf3690008 |
| 1943 | #define F0900_P2_BBHCRCKO 0xf3690004 | 1930 | #define F0900_P2_PKTDELIN_LOCK 0xf3690002 |
| 1944 | #define F0900_P2_PKTDELIN_LOCK 0xf3690002 | 1931 | #define F0900_P2_FIRST_LOCK 0xf3690001 |
| 1945 | #define F0900_P2_FIRST_LOCK 0xf3690001 | ||
| 1946 | 1932 | ||
| 1947 | /*P2_PDELSTATUS2*/ | 1933 | /*P2_PDELSTATUS2*/ |
| 1948 | #define R0900_P2_PDELSTATUS2 0xf36a | 1934 | #define R0900_P2_PDELSTATUS2 0xf36a |
| 1949 | #define F0900_P2_PKTDEL_DEMODSEL 0xf36a0080 | 1935 | #define F0900_P2_FRAME_MODCOD 0xf36a007c |
| 1950 | #define F0900_P2_FRAME_MODCOD 0xf36a007c | 1936 | #define F0900_P2_FRAME_TYPE 0xf36a0003 |
| 1951 | #define F0900_P2_FRAME_TYPE 0xf36a0003 | ||
| 1952 | 1937 | ||
| 1953 | /*P2_BBFCRCKO1*/ | 1938 | /*P2_BBFCRCKO1*/ |
| 1954 | #define R0900_P2_BBFCRCKO1 0xf36b | 1939 | #define R0900_P2_BBFCRCKO1 0xf36b |
| 1955 | #define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff | 1940 | #define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff |
| 1956 | 1941 | ||
| 1957 | /*P2_BBFCRCKO0*/ | 1942 | /*P2_BBFCRCKO0*/ |
| 1958 | #define R0900_P2_BBFCRCKO0 0xf36c | 1943 | #define R0900_P2_BBFCRCKO0 0xf36c |
| 1959 | #define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff | 1944 | #define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff |
| 1960 | 1945 | ||
| 1961 | /*P2_UPCRCKO1*/ | 1946 | /*P2_UPCRCKO1*/ |
| 1962 | #define R0900_P2_UPCRCKO1 0xf36d | 1947 | #define R0900_P2_UPCRCKO1 0xf36d |
| 1963 | #define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff | 1948 | #define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff |
| 1964 | 1949 | ||
| 1965 | /*P2_UPCRCKO0*/ | 1950 | /*P2_UPCRCKO0*/ |
| 1966 | #define R0900_P2_UPCRCKO0 0xf36e | 1951 | #define R0900_P2_UPCRCKO0 0xf36e |
| 1967 | #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff | 1952 | #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff |
| 1953 | |||
| 1954 | /*P2_PDELCTRL3*/ | ||
| 1955 | #define R0900_P2_PDELCTRL3 0xf36f | ||
| 1956 | #define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080 | ||
| 1957 | #define F0900_P2_NOFIFO_BCHERR 0xf36f0020 | ||
| 1968 | 1958 | ||
| 1969 | /*P2_TSSTATEM*/ | 1959 | /*P2_TSSTATEM*/ |
| 1970 | #define R0900_P2_TSSTATEM 0xf370 | 1960 | #define R0900_P2_TSSTATEM 0xf370 |
| 1971 | #define F0900_P2_TSDIL_ON 0xf3700080 | 1961 | #define F0900_P2_TSDIL_ON 0xf3700080 |
| 1972 | #define F0900_P2_TSSKIPRS_ON 0xf3700040 | 1962 | #define F0900_P2_TSRS_ON 0xf3700020 |
| 1973 | #define F0900_P2_TSRS_ON 0xf3700020 | 1963 | #define F0900_P2_TSDESCRAMB_ON 0xf3700010 |
| 1974 | #define F0900_P2_TSDESCRAMB_ON 0xf3700010 | 1964 | #define F0900_P2_TSFRAME_MODE 0xf3700008 |
| 1975 | #define F0900_P2_TSFRAME_MODE 0xf3700008 | 1965 | #define F0900_P2_TS_DISABLE 0xf3700004 |
| 1976 | #define F0900_P2_TS_DISABLE 0xf3700004 | 1966 | #define F0900_P2_TSOUT_NOSYNC 0xf3700001 |
| 1977 | #define F0900_P2_TSACM_MODE 0xf3700002 | ||
| 1978 | #define F0900_P2_TSOUT_NOSYNC 0xf3700001 | ||
| 1979 | 1967 | ||
| 1980 | /*P2_TSCFGH*/ | 1968 | /*P2_TSCFGH*/ |
| 1981 | #define R0900_P2_TSCFGH 0xf372 | 1969 | #define R0900_P2_TSCFGH 0xf372 |
| 1982 | #define F0900_P2_TSFIFO_DVBCI 0xf3720080 | 1970 | #define F0900_P2_TSFIFO_DVBCI 0xf3720080 |
| 1983 | #define F0900_P2_TSFIFO_SERIAL 0xf3720040 | 1971 | #define F0900_P2_TSFIFO_SERIAL 0xf3720040 |
| 1984 | #define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020 | 1972 | #define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020 |
| 1985 | #define F0900_P2_TSFIFO_DUTY50 0xf3720010 | 1973 | #define F0900_P2_TSFIFO_DUTY50 0xf3720010 |
| 1986 | #define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008 | 1974 | #define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008 |
| 1987 | #define F0900_P2_TSFIFO_ERRMODE 0xf3720006 | 1975 | #define F0900_P2_TSFIFO_ERRMODE 0xf3720006 |
| 1988 | #define F0900_P2_RST_HWARE 0xf3720001 | 1976 | #define F0900_P2_RST_HWARE 0xf3720001 |
| 1989 | 1977 | ||
| 1990 | /*P2_TSCFGM*/ | 1978 | /*P2_TSCFGM*/ |
| 1991 | #define R0900_P2_TSCFGM 0xf373 | 1979 | #define R0900_P2_TSCFGM 0xf373 |
| 1992 | #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0 | 1980 | #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0 |
| 1993 | #define F0900_P2_TSFIFO_PERMDATA 0xf3730020 | 1981 | #define F0900_P2_TSFIFO_PERMDATA 0xf3730020 |
| 1994 | #define F0900_P2_TSFIFO_NONEWSGNL 0xf3730010 | 1982 | #define F0900_P2_TSFIFO_DPUNACT 0xf3730002 |
| 1995 | #define F0900_P2_TSFIFO_BITSPEED 0xf3730008 | 1983 | #define F0900_P2_TSFIFO_INVDATA 0xf3730001 |
| 1996 | #define F0900_P2_NPD_SPECDVBS2 0xf3730004 | ||
| 1997 | #define F0900_P2_TSFIFO_STOPCKDIS 0xf3730002 | ||
| 1998 | #define F0900_P2_TSFIFO_INVDATA 0xf3730001 | ||
| 1999 | 1984 | ||
| 2000 | /*P2_TSCFGL*/ | 1985 | /*P2_TSCFGL*/ |
| 2001 | #define R0900_P2_TSCFGL 0xf374 | 1986 | #define R0900_P2_TSCFGL 0xf374 |
| 2002 | #define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 | 1987 | #define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 |
| 2003 | #define F0900_P2_BCHERROR_MODE 0xf3740030 | 1988 | #define F0900_P2_BCHERROR_MODE 0xf3740030 |
| 2004 | #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008 | 1989 | #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008 |
| 2005 | #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004 | 1990 | #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004 |
| 2006 | #define F0900_P2_TSFIFO_DPUNACT 0xf3740002 | 1991 | #define F0900_P2_TSFIFO_BITSPEED 0xf3740003 |
| 2007 | #define F0900_P2_TSFIFO_NPDOFF 0xf3740001 | ||
| 2008 | 1992 | ||
| 2009 | /*P2_TSINSDELH*/ | 1993 | /*P2_TSINSDELH*/ |
| 2010 | #define R0900_P2_TSINSDELH 0xf376 | 1994 | #define R0900_P2_TSINSDELH 0xf376 |
| 2011 | #define F0900_P2_TSDEL_SYNCBYTE 0xf3760080 | 1995 | #define F0900_P2_TSDEL_SYNCBYTE 0xf3760080 |
| 2012 | #define F0900_P2_TSDEL_XXHEADER 0xf3760040 | 1996 | #define F0900_P2_TSDEL_XXHEADER 0xf3760040 |
| 2013 | #define F0900_P2_TSDEL_BBHEADER 0xf3760020 | 1997 | #define F0900_P2_TSDEL_BBHEADER 0xf3760020 |
| 2014 | #define F0900_P2_TSDEL_DATAFIELD 0xf3760010 | 1998 | #define F0900_P2_TSDEL_DATAFIELD 0xf3760010 |
| 2015 | #define F0900_P2_TSINSDEL_ISCR 0xf3760008 | 1999 | #define F0900_P2_TSINSDEL_ISCR 0xf3760008 |
| 2016 | #define F0900_P2_TSINSDEL_NPD 0xf3760004 | 2000 | #define F0900_P2_TSINSDEL_NPD 0xf3760004 |
| 2017 | #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002 | 2001 | #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002 |
| 2018 | #define F0900_P2_TSINSDEL_CRC8 0xf3760001 | 2002 | #define F0900_P2_TSINSDEL_CRC8 0xf3760001 |
| 2003 | |||
| 2004 | /*P2_TSDIVN*/ | ||
| 2005 | #define R0900_P2_TSDIVN 0xf379 | ||
| 2006 | #define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0 | ||
| 2007 | |||
| 2008 | /*P2_TSCFG4*/ | ||
| 2009 | #define R0900_P2_TSCFG4 0xf37a | ||
| 2010 | #define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 | ||
| 2019 | 2011 | ||
| 2020 | /*P2_TSSPEED*/ | 2012 | /*P2_TSSPEED*/ |
| 2021 | #define R0900_P2_TSSPEED 0xf380 | 2013 | #define R0900_P2_TSSPEED 0xf380 |
| 2022 | #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff | 2014 | #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff |
| 2023 | 2015 | ||
| 2024 | /*P2_TSSTATUS*/ | 2016 | /*P2_TSSTATUS*/ |
| 2025 | #define R0900_P2_TSSTATUS 0xf381 | 2017 | #define R0900_P2_TSSTATUS 0xf381 |
| 2026 | #define F0900_P2_TSFIFO_LINEOK 0xf3810080 | 2018 | #define F0900_P2_TSFIFO_LINEOK 0xf3810080 |
| 2027 | #define F0900_P2_TSFIFO_ERROR 0xf3810040 | 2019 | #define F0900_P2_TSFIFO_ERROR 0xf3810040 |
| 2028 | #define F0900_P2_TSFIFO_DATA7 0xf3810020 | 2020 | #define F0900_P2_DIL_READY 0xf3810001 |
| 2029 | #define F0900_P2_TSFIFO_NOSYNC 0xf3810010 | ||
| 2030 | #define F0900_P2_ISCR_INITIALIZED 0xf3810008 | ||
| 2031 | #define F0900_P2_ISCR_UPDATED 0xf3810004 | ||
| 2032 | #define F0900_P2_SOFFIFO_UNREGUL 0xf3810002 | ||
| 2033 | #define F0900_P2_DIL_READY 0xf3810001 | ||
| 2034 | 2021 | ||
| 2035 | /*P2_TSSTATUS2*/ | 2022 | /*P2_TSSTATUS2*/ |
| 2036 | #define R0900_P2_TSSTATUS2 0xf382 | 2023 | #define R0900_P2_TSSTATUS2 0xf382 |
| 2037 | #define F0900_P2_TSFIFO_DEMODSEL 0xf3820080 | 2024 | #define F0900_P2_TSFIFO_DEMODSEL 0xf3820080 |
| 2038 | #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040 | 2025 | #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040 |
| 2039 | #define F0900_P2_DILXX_RESET 0xf3820020 | 2026 | #define F0900_P2_DILXX_RESET 0xf3820020 |
| 2040 | #define F0900_P2_TSSERIAL_IMPOS 0xf3820010 | 2027 | #define F0900_P2_TSSERIAL_IMPOS 0xf3820010 |
| 2041 | #define F0900_P2_TSFIFO_LINENOK 0xf3820008 | 2028 | #define F0900_P2_SCRAMBDETECT 0xf3820002 |
| 2042 | #define F0900_P2_BITSPEED_EVENT 0xf3820004 | ||
| 2043 | #define F0900_P2_SCRAMBDETECT 0xf3820002 | ||
| 2044 | #define F0900_P2_ULDTV67_FALSELOCK 0xf3820001 | ||
| 2045 | 2029 | ||
| 2046 | /*P2_TSBITRATE1*/ | 2030 | /*P2_TSBITRATE1*/ |
| 2047 | #define R0900_P2_TSBITRATE1 0xf383 | 2031 | #define R0900_P2_TSBITRATE1 0xf383 |
| 2048 | #define F0900_P2_TSFIFO_BITRATE1 0xf38300ff | 2032 | #define F0900_P2_TSFIFO_BITRATE1 0xf38300ff |
| 2049 | 2033 | ||
| 2050 | /*P2_TSBITRATE0*/ | 2034 | /*P2_TSBITRATE0*/ |
| 2051 | #define R0900_P2_TSBITRATE0 0xf384 | 2035 | #define R0900_P2_TSBITRATE0 0xf384 |
| 2052 | #define F0900_P2_TSFIFO_BITRATE0 0xf38400ff | 2036 | #define F0900_P2_TSFIFO_BITRATE0 0xf38400ff |
| 2053 | 2037 | ||
| 2054 | /*P2_ERRCTRL1*/ | 2038 | /*P2_ERRCTRL1*/ |
| 2055 | #define R0900_P2_ERRCTRL1 0xf398 | 2039 | #define R0900_P2_ERRCTRL1 0xf398 |
| 2056 | #define F0900_P2_ERR_SOURCE1 0xf39800f0 | 2040 | #define F0900_P2_ERR_SOURCE1 0xf39800f0 |
| 2057 | #define F0900_P2_NUM_EVENT1 0xf3980007 | 2041 | #define F0900_P2_NUM_EVENT1 0xf3980007 |
| 2058 | 2042 | ||
| 2059 | /*P2_ERRCNT12*/ | 2043 | /*P2_ERRCNT12*/ |
| 2060 | #define R0900_P2_ERRCNT12 0xf399 | 2044 | #define R0900_P2_ERRCNT12 0xf399 |
| 2061 | #define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080 | 2045 | #define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080 |
| 2062 | #define F0900_P2_ERR_CNT12 0xf399007f | 2046 | #define F0900_P2_ERR_CNT12 0xf399007f |
| 2063 | 2047 | ||
| 2064 | /*P2_ERRCNT11*/ | 2048 | /*P2_ERRCNT11*/ |
| 2065 | #define R0900_P2_ERRCNT11 0xf39a | 2049 | #define R0900_P2_ERRCNT11 0xf39a |
| 2066 | #define F0900_P2_ERR_CNT11 0xf39a00ff | 2050 | #define F0900_P2_ERR_CNT11 0xf39a00ff |
| 2067 | 2051 | ||
| 2068 | /*P2_ERRCNT10*/ | 2052 | /*P2_ERRCNT10*/ |
| 2069 | #define R0900_P2_ERRCNT10 0xf39b | 2053 | #define R0900_P2_ERRCNT10 0xf39b |
| 2070 | #define F0900_P2_ERR_CNT10 0xf39b00ff | 2054 | #define F0900_P2_ERR_CNT10 0xf39b00ff |
| 2071 | 2055 | ||
| 2072 | /*P2_ERRCTRL2*/ | 2056 | /*P2_ERRCTRL2*/ |
| 2073 | #define R0900_P2_ERRCTRL2 0xf39c | 2057 | #define R0900_P2_ERRCTRL2 0xf39c |
| 2074 | #define F0900_P2_ERR_SOURCE2 0xf39c00f0 | 2058 | #define F0900_P2_ERR_SOURCE2 0xf39c00f0 |
| 2075 | #define F0900_P2_NUM_EVENT2 0xf39c0007 | 2059 | #define F0900_P2_NUM_EVENT2 0xf39c0007 |
| 2076 | 2060 | ||
| 2077 | /*P2_ERRCNT22*/ | 2061 | /*P2_ERRCNT22*/ |
| 2078 | #define R0900_P2_ERRCNT22 0xf39d | 2062 | #define R0900_P2_ERRCNT22 0xf39d |
| 2079 | #define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080 | 2063 | #define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080 |
| 2080 | #define F0900_P2_ERR_CNT22 0xf39d007f | 2064 | #define F0900_P2_ERR_CNT22 0xf39d007f |
| 2081 | 2065 | ||
| 2082 | /*P2_ERRCNT21*/ | 2066 | /*P2_ERRCNT21*/ |
| 2083 | #define R0900_P2_ERRCNT21 0xf39e | 2067 | #define R0900_P2_ERRCNT21 0xf39e |
| 2084 | #define F0900_P2_ERR_CNT21 0xf39e00ff | 2068 | #define F0900_P2_ERR_CNT21 0xf39e00ff |
| 2085 | 2069 | ||
| 2086 | /*P2_ERRCNT20*/ | 2070 | /*P2_ERRCNT20*/ |
| 2087 | #define R0900_P2_ERRCNT20 0xf39f | 2071 | #define R0900_P2_ERRCNT20 0xf39f |
| 2088 | #define F0900_P2_ERR_CNT20 0xf39f00ff | 2072 | #define F0900_P2_ERR_CNT20 0xf39f00ff |
| 2089 | 2073 | ||
| 2090 | /*P2_FECSPY*/ | 2074 | /*P2_FECSPY*/ |
| 2091 | #define R0900_P2_FECSPY 0xf3a0 | 2075 | #define R0900_P2_FECSPY 0xf3a0 |
| 2092 | #define F0900_P2_SPY_ENABLE 0xf3a00080 | 2076 | #define F0900_P2_SPY_ENABLE 0xf3a00080 |
| 2093 | #define F0900_P2_NO_SYNCBYTE 0xf3a00040 | 2077 | #define F0900_P2_NO_SYNCBYTE 0xf3a00040 |
| 2094 | #define F0900_P2_SERIAL_MODE 0xf3a00020 | 2078 | #define F0900_P2_SERIAL_MODE 0xf3a00020 |
| 2095 | #define F0900_P2_UNUSUAL_PACKET 0xf3a00010 | 2079 | #define F0900_P2_UNUSUAL_PACKET 0xf3a00010 |
| 2096 | #define F0900_P2_BER_PACKMODE 0xf3a00008 | 2080 | #define F0900_P2_BERMETER_DATAMODE 0xf3a00008 |
| 2097 | #define F0900_P2_BERMETER_LMODE 0xf3a00002 | 2081 | #define F0900_P2_BERMETER_LMODE 0xf3a00002 |
| 2098 | #define F0900_P2_BERMETER_RESET 0xf3a00001 | 2082 | #define F0900_P2_BERMETER_RESET 0xf3a00001 |
| 2099 | 2083 | ||
| 2100 | /*P2_FSPYCFG*/ | 2084 | /*P2_FSPYCFG*/ |
| 2101 | #define R0900_P2_FSPYCFG 0xf3a1 | 2085 | #define R0900_P2_FSPYCFG 0xf3a1 |
| 2102 | #define F0900_P2_FECSPY_INPUT 0xf3a100c0 | 2086 | #define F0900_P2_FECSPY_INPUT 0xf3a100c0 |
| 2103 | #define F0900_P2_RST_ON_ERROR 0xf3a10020 | 2087 | #define F0900_P2_RST_ON_ERROR 0xf3a10020 |
| 2104 | #define F0900_P2_ONE_SHOT 0xf3a10010 | 2088 | #define F0900_P2_ONE_SHOT 0xf3a10010 |
| 2105 | #define F0900_P2_I2C_MODE 0xf3a1000c | 2089 | #define F0900_P2_I2C_MODE 0xf3a1000c |
| 2106 | #define F0900_P2_SPY_HYSTERESIS 0xf3a10003 | 2090 | #define F0900_P2_SPY_HYSTERESIS 0xf3a10003 |
| 2107 | 2091 | ||
| 2108 | /*P2_FSPYDATA*/ | 2092 | /*P2_FSPYDATA*/ |
| 2109 | #define R0900_P2_FSPYDATA 0xf3a2 | 2093 | #define R0900_P2_FSPYDATA 0xf3a2 |
| 2110 | #define F0900_P2_SPY_STUFFING 0xf3a20080 | 2094 | #define F0900_P2_SPY_STUFFING 0xf3a20080 |
| 2111 | #define F0900_P2_NOERROR_PKTJITTER 0xf3a20040 | 2095 | #define F0900_P2_SPY_CNULLPKT 0xf3a20020 |
| 2112 | #define F0900_P2_SPY_CNULLPKT 0xf3a20020 | 2096 | #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f |
| 2113 | #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f | ||
| 2114 | 2097 | ||
| 2115 | /*P2_FSPYOUT*/ | 2098 | /*P2_FSPYOUT*/ |
| 2116 | #define R0900_P2_FSPYOUT 0xf3a3 | 2099 | #define R0900_P2_FSPYOUT 0xf3a3 |
| 2117 | #define F0900_P2_FSPY_DIRECT 0xf3a30080 | 2100 | #define F0900_P2_FSPY_DIRECT 0xf3a30080 |
| 2118 | #define F0900_P2_SPY_OUTDATA_BUS 0xf3a30038 | 2101 | #define F0900_P2_STUFF_MODE 0xf3a30007 |
| 2119 | #define F0900_P2_STUFF_MODE 0xf3a30007 | ||
| 2120 | 2102 | ||
| 2121 | /*P2_FSTATUS*/ | 2103 | /*P2_FSTATUS*/ |
| 2122 | #define R0900_P2_FSTATUS 0xf3a4 | 2104 | #define R0900_P2_FSTATUS 0xf3a4 |
| 2123 | #define F0900_P2_SPY_ENDSIM 0xf3a40080 | 2105 | #define F0900_P2_SPY_ENDSIM 0xf3a40080 |
| 2124 | #define F0900_P2_VALID_SIM 0xf3a40040 | 2106 | #define F0900_P2_VALID_SIM 0xf3a40040 |
| 2125 | #define F0900_P2_FOUND_SIGNAL 0xf3a40020 | 2107 | #define F0900_P2_FOUND_SIGNAL 0xf3a40020 |
| 2126 | #define F0900_P2_DSS_SYNCBYTE 0xf3a40010 | 2108 | #define F0900_P2_DSS_SYNCBYTE 0xf3a40010 |
| 2127 | #define F0900_P2_RESULT_STATE 0xf3a4000f | 2109 | #define F0900_P2_RESULT_STATE 0xf3a4000f |
| 2128 | 2110 | ||
| 2129 | /*P2_FBERCPT4*/ | 2111 | /*P2_FBERCPT4*/ |
| 2130 | #define R0900_P2_FBERCPT4 0xf3a8 | 2112 | #define R0900_P2_FBERCPT4 0xf3a8 |
| 2131 | #define F0900_P2_FBERMETER_CPT4 0xf3a800ff | 2113 | #define F0900_P2_FBERMETER_CPT4 0xf3a800ff |
| 2132 | 2114 | ||
| 2133 | /*P2_FBERCPT3*/ | 2115 | /*P2_FBERCPT3*/ |
| 2134 | #define R0900_P2_FBERCPT3 0xf3a9 | 2116 | #define R0900_P2_FBERCPT3 0xf3a9 |
| 2135 | #define F0900_P2_FBERMETER_CPT3 0xf3a900ff | 2117 | #define F0900_P2_FBERMETER_CPT3 0xf3a900ff |
| 2136 | 2118 | ||
| 2137 | /*P2_FBERCPT2*/ | 2119 | /*P2_FBERCPT2*/ |
| 2138 | #define R0900_P2_FBERCPT2 0xf3aa | 2120 | #define R0900_P2_FBERCPT2 0xf3aa |
| 2139 | #define F0900_P2_FBERMETER_CPT2 0xf3aa00ff | 2121 | #define F0900_P2_FBERMETER_CPT2 0xf3aa00ff |
| 2140 | 2122 | ||
| 2141 | /*P2_FBERCPT1*/ | 2123 | /*P2_FBERCPT1*/ |
| 2142 | #define R0900_P2_FBERCPT1 0xf3ab | 2124 | #define R0900_P2_FBERCPT1 0xf3ab |
| 2143 | #define F0900_P2_FBERMETER_CPT1 0xf3ab00ff | 2125 | #define F0900_P2_FBERMETER_CPT1 0xf3ab00ff |
| 2144 | 2126 | ||
| 2145 | /*P2_FBERCPT0*/ | 2127 | /*P2_FBERCPT0*/ |
| 2146 | #define R0900_P2_FBERCPT0 0xf3ac | 2128 | #define R0900_P2_FBERCPT0 0xf3ac |
| 2147 | #define F0900_P2_FBERMETER_CPT0 0xf3ac00ff | 2129 | #define F0900_P2_FBERMETER_CPT0 0xf3ac00ff |
| 2148 | 2130 | ||
| 2149 | /*P2_FBERERR2*/ | 2131 | /*P2_FBERERR2*/ |
| 2150 | #define R0900_P2_FBERERR2 0xf3ad | 2132 | #define R0900_P2_FBERERR2 0xf3ad |
| 2151 | #define F0900_P2_FBERMETER_ERR2 0xf3ad00ff | 2133 | #define F0900_P2_FBERMETER_ERR2 0xf3ad00ff |
| 2152 | 2134 | ||
| 2153 | /*P2_FBERERR1*/ | 2135 | /*P2_FBERERR1*/ |
| 2154 | #define R0900_P2_FBERERR1 0xf3ae | 2136 | #define R0900_P2_FBERERR1 0xf3ae |
| 2155 | #define F0900_P2_FBERMETER_ERR1 0xf3ae00ff | 2137 | #define F0900_P2_FBERMETER_ERR1 0xf3ae00ff |
| 2156 | 2138 | ||
| 2157 | /*P2_FBERERR0*/ | 2139 | /*P2_FBERERR0*/ |
| 2158 | #define R0900_P2_FBERERR0 0xf3af | 2140 | #define R0900_P2_FBERERR0 0xf3af |
| 2159 | #define F0900_P2_FBERMETER_ERR0 0xf3af00ff | 2141 | #define F0900_P2_FBERMETER_ERR0 0xf3af00ff |
| 2160 | 2142 | ||
| 2161 | /*P2_FSPYBER*/ | 2143 | /*P2_FSPYBER*/ |
| 2162 | #define R0900_P2_FSPYBER 0xf3b2 | 2144 | #define R0900_P2_FSPYBER 0xf3b2 |
| 2163 | #define F0900_P2_FSPYOBS_XORREAD 0xf3b20040 | 2145 | #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010 |
| 2164 | #define F0900_P2_FSPYBER_OBSMODE 0xf3b20020 | 2146 | #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008 |
| 2165 | #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010 | 2147 | #define F0900_P2_FSPYBER_CTIME 0xf3b20007 |
| 2166 | #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008 | ||
| 2167 | #define F0900_P2_FSPYBER_CTIME 0xf3b20007 | ||
| 2168 | 2148 | ||
| 2169 | /*P1_IQCONST*/ | 2149 | /*P1_IQCONST*/ |
| 2170 | #define R0900_P1_IQCONST 0xf400 | 2150 | #define R0900_P1_IQCONST 0xf400 |
| 2171 | #define F0900_P1_CONSTEL_SELECT 0xf4000060 | 2151 | #define IQCONST REGx(R0900_P1_IQCONST) |
| 2172 | #define F0900_P1_IQSYMB_SEL 0xf400001f | 2152 | #define F0900_P1_CONSTEL_SELECT 0xf4000060 |
| 2153 | #define F0900_P1_IQSYMB_SEL 0xf400001f | ||
| 2173 | 2154 | ||
| 2174 | /*P1_NOSCFG*/ | 2155 | /*P1_NOSCFG*/ |
| 2175 | #define R0900_P1_NOSCFG 0xf401 | 2156 | #define R0900_P1_NOSCFG 0xf401 |
| 2176 | #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020 | 2157 | #define NOSCFG REGx(R0900_P1_NOSCFG) |
| 2177 | #define F0900_P1_NOSPLH_BETA 0xf4010018 | 2158 | #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020 |
| 2178 | #define F0900_P1_NOSDATA_BETA 0xf4010007 | 2159 | #define F0900_P1_NOSPLH_BETA 0xf4010018 |
| 2160 | #define F0900_P1_NOSDATA_BETA 0xf4010007 | ||
| 2179 | 2161 | ||
| 2180 | /*P1_ISYMB*/ | 2162 | /*P1_ISYMB*/ |
| 2181 | #define R0900_P1_ISYMB 0xf402 | 2163 | #define R0900_P1_ISYMB 0xf402 |
| 2182 | #define F0900_P1_I_SYMBOL 0xf40201ff | 2164 | #define ISYMB REGx(R0900_P1_ISYMB) |
| 2165 | #define F0900_P1_I_SYMBOL 0xf40201ff | ||
| 2183 | 2166 | ||
| 2184 | /*P1_QSYMB*/ | 2167 | /*P1_QSYMB*/ |
| 2185 | #define R0900_P1_QSYMB 0xf403 | 2168 | #define R0900_P1_QSYMB 0xf403 |
| 2186 | #define F0900_P1_Q_SYMBOL 0xf40301ff | 2169 | #define QSYMB REGx(R0900_P1_QSYMB) |
| 2170 | #define F0900_P1_Q_SYMBOL 0xf40301ff | ||
| 2187 | 2171 | ||
| 2188 | /*P1_AGC1CFG*/ | 2172 | /*P1_AGC1CFG*/ |
| 2189 | #define R0900_P1_AGC1CFG 0xf404 | 2173 | #define R0900_P1_AGC1CFG 0xf404 |
| 2190 | #define F0900_P1_DC_FROZEN 0xf4040080 | 2174 | #define AGC1CFG REGx(R0900_P1_AGC1CFG) |
| 2191 | #define F0900_P1_DC_CORRECT 0xf4040040 | 2175 | #define F0900_P1_DC_FROZEN 0xf4040080 |
| 2192 | #define F0900_P1_AMM_FROZEN 0xf4040020 | 2176 | #define F0900_P1_DC_CORRECT 0xf4040040 |
| 2193 | #define F0900_P1_AMM_CORRECT 0xf4040010 | 2177 | #define F0900_P1_AMM_FROZEN 0xf4040020 |
| 2194 | #define F0900_P1_QUAD_FROZEN 0xf4040008 | 2178 | #define F0900_P1_AMM_CORRECT 0xf4040010 |
| 2195 | #define F0900_P1_QUAD_CORRECT 0xf4040004 | 2179 | #define F0900_P1_QUAD_FROZEN 0xf4040008 |
| 2196 | #define F0900_P1_DCCOMP_SLOW 0xf4040002 | 2180 | #define F0900_P1_QUAD_CORRECT 0xf4040004 |
| 2197 | #define F0900_P1_IQMISM_SLOW 0xf4040001 | ||
| 2198 | 2181 | ||
| 2199 | /*P1_AGC1CN*/ | 2182 | /*P1_AGC1CN*/ |
| 2200 | #define R0900_P1_AGC1CN 0xf406 | 2183 | #define R0900_P1_AGC1CN 0xf406 |
| 2201 | #define F0900_P1_AGC1_LOCKED 0xf4060080 | 2184 | #define AGC1CN REGx(R0900_P1_AGC1CN) |
| 2202 | #define F0900_P1_AGC1_OVERFLOW 0xf4060040 | 2185 | #define F0900_P1_AGC1_LOCKED 0xf4060080 |
| 2203 | #define F0900_P1_AGC1_NOSLOWLK 0xf4060020 | 2186 | #define F0900_P1_AGC1_MINPOWER 0xf4060010 |
| 2204 | #define F0900_P1_AGC1_MINPOWER 0xf4060010 | 2187 | #define F0900_P1_AGCOUT_FAST 0xf4060008 |
| 2205 | #define F0900_P1_AGCOUT_FAST 0xf4060008 | 2188 | #define F0900_P1_AGCIQ_BETA 0xf4060007 |
| 2206 | #define F0900_P1_AGCIQ_BETA 0xf4060007 | ||
| 2207 | 2189 | ||
| 2208 | /*P1_AGC1REF*/ | 2190 | /*P1_AGC1REF*/ |
| 2209 | #define R0900_P1_AGC1REF 0xf407 | 2191 | #define R0900_P1_AGC1REF 0xf407 |
| 2210 | #define F0900_P1_AGCIQ_REF 0xf40700ff | 2192 | #define AGC1REF REGx(R0900_P1_AGC1REF) |
| 2193 | #define F0900_P1_AGCIQ_REF 0xf40700ff | ||
| 2211 | 2194 | ||
| 2212 | /*P1_IDCCOMP*/ | 2195 | /*P1_IDCCOMP*/ |
| 2213 | #define R0900_P1_IDCCOMP 0xf408 | 2196 | #define R0900_P1_IDCCOMP 0xf408 |
| 2214 | #define F0900_P1_IAVERAGE_ADJ 0xf40801ff | 2197 | #define IDCCOMP REGx(R0900_P1_IDCCOMP) |
| 2198 | #define F0900_P1_IAVERAGE_ADJ 0xf40801ff | ||
| 2215 | 2199 | ||
| 2216 | /*P1_QDCCOMP*/ | 2200 | /*P1_QDCCOMP*/ |
| 2217 | #define R0900_P1_QDCCOMP 0xf409 | 2201 | #define R0900_P1_QDCCOMP 0xf409 |
| 2218 | #define F0900_P1_QAVERAGE_ADJ 0xf40901ff | 2202 | #define QDCCOMP REGx(R0900_P1_QDCCOMP) |
| 2203 | #define F0900_P1_QAVERAGE_ADJ 0xf40901ff | ||
| 2219 | 2204 | ||
| 2220 | /*P1_POWERI*/ | 2205 | /*P1_POWERI*/ |
| 2221 | #define R0900_P1_POWERI 0xf40a | 2206 | #define R0900_P1_POWERI 0xf40a |
| 2222 | #define F0900_P1_POWER_I 0xf40a00ff | 2207 | #define POWERI REGx(R0900_P1_POWERI) |
| 2208 | #define F0900_P1_POWER_I 0xf40a00ff | ||
| 2209 | #define POWER_I FLDx(F0900_P1_POWER_I) | ||
| 2223 | 2210 | ||
| 2224 | /*P1_POWERQ*/ | 2211 | /*P1_POWERQ*/ |
| 2225 | #define R0900_P1_POWERQ 0xf40b | 2212 | #define R0900_P1_POWERQ 0xf40b |
| 2226 | #define F0900_P1_POWER_Q 0xf40b00ff | 2213 | #define POWERQ REGx(R0900_P1_POWERQ) |
| 2214 | #define F0900_P1_POWER_Q 0xf40b00ff | ||
| 2215 | #define POWER_Q FLDx(F0900_P1_POWER_Q) | ||
| 2227 | 2216 | ||
| 2228 | /*P1_AGC1AMM*/ | 2217 | /*P1_AGC1AMM*/ |
| 2229 | #define R0900_P1_AGC1AMM 0xf40c | 2218 | #define R0900_P1_AGC1AMM 0xf40c |
| 2230 | #define F0900_P1_AMM_VALUE 0xf40c00ff | 2219 | #define AGC1AMM REGx(R0900_P1_AGC1AMM) |
| 2220 | #define F0900_P1_AMM_VALUE 0xf40c00ff | ||
| 2231 | 2221 | ||
| 2232 | /*P1_AGC1QUAD*/ | 2222 | /*P1_AGC1QUAD*/ |
| 2233 | #define R0900_P1_AGC1QUAD 0xf40d | 2223 | #define R0900_P1_AGC1QUAD 0xf40d |
| 2234 | #define F0900_P1_QUAD_VALUE 0xf40d01ff | 2224 | #define AGC1QUAD REGx(R0900_P1_AGC1QUAD) |
| 2225 | #define F0900_P1_QUAD_VALUE 0xf40d01ff | ||
| 2235 | 2226 | ||
| 2236 | /*P1_AGCIQIN1*/ | 2227 | /*P1_AGCIQIN1*/ |
| 2237 | #define R0900_P1_AGCIQIN1 0xf40e | 2228 | #define R0900_P1_AGCIQIN1 0xf40e |
| 2238 | #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff | 2229 | #define AGCIQIN1 REGx(R0900_P1_AGCIQIN1) |
| 2230 | #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff | ||
| 2231 | #define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1) | ||
| 2239 | 2232 | ||
| 2240 | /*P1_AGCIQIN0*/ | 2233 | /*P1_AGCIQIN0*/ |
| 2241 | #define R0900_P1_AGCIQIN0 0xf40f | 2234 | #define R0900_P1_AGCIQIN0 0xf40f |
| 2242 | #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff | 2235 | #define AGCIQIN0 REGx(R0900_P1_AGCIQIN0) |
| 2236 | #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff | ||
| 2237 | #define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0) | ||
| 2243 | 2238 | ||
| 2244 | /*P1_DEMOD*/ | 2239 | /*P1_DEMOD*/ |
| 2245 | #define R0900_P1_DEMOD 0xf410 | 2240 | #define R0900_P1_DEMOD 0xf410 |
| 2246 | #define F0900_P1_DEMOD_STOP 0xf4100040 | 2241 | #define DEMOD REGx(R0900_P1_DEMOD) |
| 2247 | #define F0900_P1_SPECINV_CONTROL 0xf4100030 | 2242 | #define F0900_P1_MANUALS2_ROLLOFF 0xf4100080 |
| 2248 | #define F0900_P1_FORCE_ENASAMP 0xf4100008 | 2243 | #define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF) |
| 2249 | #define F0900_P1_MANUAL_ROLLOFF 0xf4100004 | 2244 | |
| 2250 | #define F0900_P1_ROLLOFF_CONTROL 0xf4100003 | 2245 | #define F0900_P1_SPECINV_CONTROL 0xf4100030 |
| 2246 | #define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL) | ||
| 2247 | #define F0900_P1_FORCE_ENASAMP 0xf4100008 | ||
| 2248 | #define F0900_P1_MANUALSX_ROLLOFF 0xf4100004 | ||
| 2249 | #define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF) | ||
| 2250 | #define F0900_P1_ROLLOFF_CONTROL 0xf4100003 | ||
| 2251 | #define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL) | ||
| 2251 | 2252 | ||
| 2252 | /*P1_DMDMODCOD*/ | 2253 | /*P1_DMDMODCOD*/ |
| 2253 | #define R0900_P1_DMDMODCOD 0xf411 | 2254 | #define R0900_P1_DMDMODCOD 0xf411 |
| 2254 | #define F0900_P1_MANUAL_MODCOD 0xf4110080 | 2255 | #define DMDMODCOD REGx(R0900_P1_DMDMODCOD) |
| 2255 | #define F0900_P1_DEMOD_MODCOD 0xf411007c | 2256 | #define F0900_P1_MANUAL_MODCOD 0xf4110080 |
| 2256 | #define F0900_P1_DEMOD_TYPE 0xf4110003 | 2257 | #define F0900_P1_DEMOD_MODCOD 0xf411007c |
| 2258 | #define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD) | ||
| 2259 | #define F0900_P1_DEMOD_TYPE 0xf4110003 | ||
| 2260 | #define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE) | ||
| 2257 | 2261 | ||
| 2258 | /*P1_DSTATUS*/ | 2262 | /*P1_DSTATUS*/ |
| 2259 | #define R0900_P1_DSTATUS 0xf412 | 2263 | #define R0900_P1_DSTATUS 0xf412 |
| 2260 | #define F0900_P1_CAR_LOCK 0xf4120080 | 2264 | #define DSTATUS REGx(R0900_P1_DSTATUS) |
| 2261 | #define F0900_P1_TMGLOCK_QUALITY 0xf4120060 | 2265 | #define F0900_P1_CAR_LOCK 0xf4120080 |
| 2262 | #define F0900_P1_SDVBS1_ENABLE 0xf4120010 | 2266 | #define F0900_P1_TMGLOCK_QUALITY 0xf4120060 |
| 2263 | #define F0900_P1_LOCK_DEFINITIF 0xf4120008 | 2267 | #define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY) |
| 2264 | #define F0900_P1_TIMING_IS_LOCKED 0xf4120004 | 2268 | #define F0900_P1_LOCK_DEFINITIF 0xf4120008 |
| 2265 | #define F0900_P1_COARSE_TMGLOCK 0xf4120002 | 2269 | #define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF) |
| 2266 | #define F0900_P1_COARSE_CARLOCK 0xf4120001 | 2270 | #define F0900_P1_OVADC_DETECT 0xf4120001 |
| 2267 | 2271 | ||
| 2268 | /*P1_DSTATUS2*/ | 2272 | /*P1_DSTATUS2*/ |
| 2269 | #define R0900_P1_DSTATUS2 0xf413 | 2273 | #define R0900_P1_DSTATUS2 0xf413 |
| 2270 | #define F0900_P1_DEMOD_DELOCK 0xf4130080 | 2274 | #define DSTATUS2 REGx(R0900_P1_DSTATUS2) |
| 2271 | #define F0900_P1_DEMOD_TIMEOUT 0xf4130040 | 2275 | #define F0900_P1_DEMOD_DELOCK 0xf4130080 |
| 2272 | #define F0900_P1_MODCODRQ_SYNCTAG 0xf4130020 | 2276 | #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008 |
| 2273 | #define F0900_P1_POLYPH_SATEVENT 0xf4130010 | 2277 | #define F0900_P1_AGC2_OVERFLOW 0xf4130004 |
| 2274 | #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008 | 2278 | #define F0900_P1_CFR_OVERFLOW 0xf4130002 |
| 2275 | #define F0900_P1_AGC2_OVERFLOW 0xf4130004 | 2279 | #define F0900_P1_GAMMA_OVERUNDER 0xf4130001 |
| 2276 | #define F0900_P1_CFR_OVERFLOW 0xf4130002 | ||
| 2277 | #define F0900_P1_GAMMA_OVERUNDER 0xf4130001 | ||
| 2278 | 2280 | ||
| 2279 | /*P1_DMDCFGMD*/ | 2281 | /*P1_DMDCFGMD*/ |
| 2280 | #define R0900_P1_DMDCFGMD 0xf414 | 2282 | #define R0900_P1_DMDCFGMD 0xf414 |
| 2281 | #define F0900_P1_DVBS2_ENABLE 0xf4140080 | 2283 | #define DMDCFGMD REGx(R0900_P1_DMDCFGMD) |
| 2282 | #define F0900_P1_DVBS1_ENABLE 0xf4140040 | 2284 | #define F0900_P1_DVBS2_ENABLE 0xf4140080 |
| 2283 | #define F0900_P1_CFR_AUTOSCAN 0xf4140020 | 2285 | #define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE) |
| 2284 | #define F0900_P1_SCAN_ENABLE 0xf4140010 | 2286 | #define F0900_P1_DVBS1_ENABLE 0xf4140040 |
| 2285 | #define F0900_P1_TUN_AUTOSCAN 0xf4140008 | 2287 | #define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE) |
| 2286 | #define F0900_P1_NOFORCE_RELOCK 0xf4140004 | 2288 | #define F0900_P1_SCAN_ENABLE 0xf4140010 |
| 2287 | #define F0900_P1_TUN_RNG 0xf4140003 | 2289 | #define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE) |
| 2290 | #define F0900_P1_CFR_AUTOSCAN 0xf4140008 | ||
| 2291 | #define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN) | ||
| 2292 | #define F0900_P1_TUN_RNG 0xf4140003 | ||
| 2288 | 2293 | ||
| 2289 | /*P1_DMDCFG2*/ | 2294 | /*P1_DMDCFG2*/ |
| 2290 | #define R0900_P1_DMDCFG2 0xf415 | 2295 | #define R0900_P1_DMDCFG2 0xf415 |
| 2291 | #define F0900_P1_AGC1_WAITLOCK 0xf4150080 | 2296 | #define DMDCFG2 REGx(R0900_P1_DMDCFG2) |
| 2292 | #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040 | 2297 | #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040 |
| 2293 | #define F0900_P1_OVERFLOW_TIMEOUT 0xf4150020 | 2298 | #define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL) |
| 2294 | #define F0900_P1_SCANFAIL_TIMEOUT 0xf4150010 | 2299 | #define F0900_P1_INFINITE_RELOCK 0xf4150010 |
| 2295 | #define F0900_P1_DMDTOUT_BACK 0xf4150008 | ||
| 2296 | #define F0900_P1_CARLOCK_S1ENABLE 0xf4150004 | ||
| 2297 | #define F0900_P1_COARSE_LK3MODE 0xf4150002 | ||
| 2298 | #define F0900_P1_COARSE_LK2MODE 0xf4150001 | ||
| 2299 | 2300 | ||
| 2300 | /*P1_DMDISTATE*/ | 2301 | /*P1_DMDISTATE*/ |
| 2301 | #define R0900_P1_DMDISTATE 0xf416 | 2302 | #define R0900_P1_DMDISTATE 0xf416 |
| 2302 | #define F0900_P1_I2C_NORESETDMODE 0xf4160080 | 2303 | #define DMDISTATE REGx(R0900_P1_DMDISTATE) |
| 2303 | #define F0900_P1_FORCE_ETAPED 0xf4160040 | 2304 | #define F0900_P1_I2C_DEMOD_MODE 0xf416001f |
| 2304 | #define F0900_P1_SDMDRST_DIRCLK 0xf4160020 | 2305 | #define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE) |
| 2305 | #define F0900_P1_I2C_DEMOD_MODE 0xf416001f | ||
| 2306 | 2306 | ||
| 2307 | /*P1_DMDT0M*/ | 2307 | /*P1_DMDT0M*/ |
| 2308 | #define R0900_P1_DMDT0M 0xf417 | 2308 | #define R0900_P1_DMDT0M 0xf417 |
| 2309 | #define F0900_P1_DMDT0_MIN 0xf41700ff | 2309 | #define DMDT0M REGx(R0900_P1_DMDT0M) |
| 2310 | #define F0900_P1_DMDT0_MIN 0xf41700ff | ||
| 2310 | 2311 | ||
| 2311 | /*P1_DMDSTATE*/ | 2312 | /*P1_DMDSTATE*/ |
| 2312 | #define R0900_P1_DMDSTATE 0xf41b | 2313 | #define R0900_P1_DMDSTATE 0xf41b |
| 2313 | #define F0900_P1_DEMOD_LOCKED 0xf41b0080 | 2314 | #define DMDSTATE REGx(R0900_P1_DMDSTATE) |
| 2314 | #define F0900_P1_HEADER_MODE 0xf41b0060 | 2315 | #define F0900_P1_HEADER_MODE 0xf41b0060 |
| 2315 | #define F0900_P1_DEMOD_MODE 0xf41b001f | 2316 | #define HEADER_MODE FLDx(F0900_P1_HEADER_MODE) |
| 2316 | 2317 | ||
| 2317 | /*P1_DMDFLYW*/ | 2318 | /*P1_DMDFLYW*/ |
| 2318 | #define R0900_P1_DMDFLYW 0xf41c | 2319 | #define R0900_P1_DMDFLYW 0xf41c |
| 2319 | #define F0900_P1_I2C_IRQVAL 0xf41c00f0 | 2320 | #define DMDFLYW REGx(R0900_P1_DMDFLYW) |
| 2320 | #define F0900_P1_FLYWHEEL_CPT 0xf41c000f | 2321 | #define F0900_P1_I2C_IRQVAL 0xf41c00f0 |
| 2322 | #define F0900_P1_FLYWHEEL_CPT 0xf41c000f | ||
| 2323 | #define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT) | ||
| 2321 | 2324 | ||
| 2322 | /*P1_DSTATUS3*/ | 2325 | /*P1_DSTATUS3*/ |
| 2323 | #define R0900_P1_DSTATUS3 0xf41d | 2326 | #define R0900_P1_DSTATUS3 0xf41d |
| 2324 | #define F0900_P1_CFR_ZIGZAG 0xf41d0080 | 2327 | #define DSTATUS3 REGx(R0900_P1_DSTATUS3) |
| 2325 | #define F0900_P1_DEMOD_CFGMODE 0xf41d0060 | 2328 | #define F0900_P1_DEMOD_CFGMODE 0xf41d0060 |
| 2326 | #define F0900_P1_GAMMA_LOWBAUDRATE 0xf41d0010 | ||
| 2327 | #define F0900_P1_RELOCK_MODE 0xf41d0008 | ||
| 2328 | #define F0900_P1_DEMOD_FAIL 0xf41d0004 | ||
| 2329 | #define F0900_P1_ETAPE1A_DVBXMEM 0xf41d0003 | ||
| 2330 | 2329 | ||
| 2331 | /*P1_DMDCFG3*/ | 2330 | /*P1_DMDCFG3*/ |
| 2332 | #define R0900_P1_DMDCFG3 0xf41e | 2331 | #define R0900_P1_DMDCFG3 0xf41e |
| 2333 | #define F0900_P1_DVBS1_TMGWAIT 0xf41e0080 | 2332 | #define DMDCFG3 REGx(R0900_P1_DMDCFG3) |
| 2334 | #define F0900_P1_NO_BWCENTERING 0xf41e0040 | 2333 | #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008 |
| 2335 | #define F0900_P1_INV_SEQSRCH 0xf41e0020 | ||
| 2336 | #define F0900_P1_DIS_SFRUPLOW_TRK 0xf41e0010 | ||
| 2337 | #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008 | ||
| 2338 | #define F0900_P1_LOCKTIME_MODE 0xf41e0007 | ||
| 2339 | 2334 | ||
| 2340 | /*P1_DMDCFG4*/ | 2335 | /*P1_DMDCFG4*/ |
| 2341 | #define R0900_P1_DMDCFG4 0xf41f | 2336 | #define R0900_P1_DMDCFG4 0xf41f |
| 2342 | #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008 | 2337 | #define DMDCFG4 REGx(R0900_P1_DMDCFG4) |
| 2343 | #define F0900_P1_DIS_CLKENABLE 0xf41f0004 | 2338 | #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008 |
| 2344 | #define F0900_P1_DIS_HDRDIVLOCK 0xf41f0002 | ||
| 2345 | #define F0900_P1_NO_TNRWBINIT 0xf41f0001 | ||
| 2346 | 2339 | ||
| 2347 | /*P1_CORRELMANT*/ | 2340 | /*P1_CORRELMANT*/ |
| 2348 | #define R0900_P1_CORRELMANT 0xf420 | 2341 | #define R0900_P1_CORRELMANT 0xf420 |
| 2349 | #define F0900_P1_CORREL_MANT 0xf42000ff | 2342 | #define CORRELMANT REGx(R0900_P1_CORRELMANT) |
| 2343 | #define F0900_P1_CORREL_MANT 0xf42000ff | ||
| 2350 | 2344 | ||
| 2351 | /*P1_CORRELABS*/ | 2345 | /*P1_CORRELABS*/ |
| 2352 | #define R0900_P1_CORRELABS 0xf421 | 2346 | #define R0900_P1_CORRELABS 0xf421 |
| 2353 | #define F0900_P1_CORREL_ABS 0xf42100ff | 2347 | #define CORRELABS REGx(R0900_P1_CORRELABS) |
| 2348 | #define F0900_P1_CORREL_ABS 0xf42100ff | ||
| 2354 | 2349 | ||
| 2355 | /*P1_CORRELEXP*/ | 2350 | /*P1_CORRELEXP*/ |
| 2356 | #define R0900_P1_CORRELEXP 0xf422 | 2351 | #define R0900_P1_CORRELEXP 0xf422 |
| 2357 | #define F0900_P1_CORREL_ABSEXP 0xf42200f0 | 2352 | #define CORRELEXP REGx(R0900_P1_CORRELEXP) |
| 2358 | #define F0900_P1_CORREL_EXP 0xf422000f | 2353 | #define F0900_P1_CORREL_ABSEXP 0xf42200f0 |
| 2354 | #define F0900_P1_CORREL_EXP 0xf422000f | ||
| 2359 | 2355 | ||
| 2360 | /*P1_PLHMODCOD*/ | 2356 | /*P1_PLHMODCOD*/ |
| 2361 | #define R0900_P1_PLHMODCOD 0xf424 | 2357 | #define R0900_P1_PLHMODCOD 0xf424 |
| 2362 | #define F0900_P1_SPECINV_DEMOD 0xf4240080 | 2358 | #define PLHMODCOD REGx(R0900_P1_PLHMODCOD) |
| 2363 | #define F0900_P1_PLH_MODCOD 0xf424007c | 2359 | #define F0900_P1_SPECINV_DEMOD 0xf4240080 |
| 2364 | #define F0900_P1_PLH_TYPE 0xf4240003 | 2360 | #define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD) |
| 2365 | 2361 | #define F0900_P1_PLH_MODCOD 0xf424007c | |
| 2366 | /*P1_AGCK32*/ | 2362 | #define F0900_P1_PLH_TYPE 0xf4240003 |
| 2367 | #define R0900_P1_AGCK32 0xf42b | 2363 | |
| 2368 | #define F0900_P1_R3ADJOFF_32APSK 0xf42b0080 | 2364 | /*P1_DMDREG*/ |
| 2369 | #define F0900_P1_R2ADJOFF_32APSK 0xf42b0040 | 2365 | #define R0900_P1_DMDREG 0xf425 |
| 2370 | #define F0900_P1_R1ADJOFF_32APSK 0xf42b0020 | 2366 | #define DMDREG REGx(R0900_P1_DMDREG) |
| 2371 | #define F0900_P1_RADJ_32APSK 0xf42b001f | 2367 | #define F0900_P1_DECIM_PLFRAMES 0xf4250001 |
| 2372 | 2368 | ||
| 2373 | /*P1_AGC2O*/ | 2369 | /*P1_AGC2O*/ |
| 2374 | #define R0900_P1_AGC2O 0xf42c | 2370 | #define R0900_P1_AGC2O 0xf42c |
| 2375 | #define F0900_P1_AGC2REF_ADJUSTING 0xf42c0080 | 2371 | #define AGC2O REGx(R0900_P1_AGC2O) |
| 2376 | #define F0900_P1_AGC2_COARSEFAST 0xf42c0040 | 2372 | #define F0900_P1_AGC2_COEF 0xf42c0007 |
| 2377 | #define F0900_P1_AGC2_LKSQRT 0xf42c0020 | ||
| 2378 | #define F0900_P1_AGC2_LKMODE 0xf42c0010 | ||
| 2379 | #define F0900_P1_AGC2_LKEQUA 0xf42c0008 | ||
| 2380 | #define F0900_P1_AGC2_COEF 0xf42c0007 | ||
| 2381 | 2373 | ||
| 2382 | /*P1_AGC2REF*/ | 2374 | /*P1_AGC2REF*/ |
| 2383 | #define R0900_P1_AGC2REF 0xf42d | 2375 | #define R0900_P1_AGC2REF 0xf42d |
| 2384 | #define F0900_P1_AGC2_REF 0xf42d00ff | 2376 | #define AGC2REF REGx(R0900_P1_AGC2REF) |
| 2377 | #define F0900_P1_AGC2_REF 0xf42d00ff | ||
| 2385 | 2378 | ||
| 2386 | /*P1_AGC1ADJ*/ | 2379 | /*P1_AGC1ADJ*/ |
| 2387 | #define R0900_P1_AGC1ADJ 0xf42e | 2380 | #define R0900_P1_AGC1ADJ 0xf42e |
| 2388 | #define F0900_P1_AGC1ADJ_MANUAL 0xf42e0080 | 2381 | #define AGC1ADJ REGx(R0900_P1_AGC1ADJ) |
| 2389 | #define F0900_P1_AGC1_ADJUSTED 0xf42e017f | 2382 | #define F0900_P1_AGC1_ADJUSTED 0xf42e007f |
| 2390 | 2383 | ||
| 2391 | /*P1_AGC2I1*/ | 2384 | /*P1_AGC2I1*/ |
| 2392 | #define R0900_P1_AGC2I1 0xf436 | 2385 | #define R0900_P1_AGC2I1 0xf436 |
| 2393 | #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff | 2386 | #define AGC2I1 REGx(R0900_P1_AGC2I1) |
| 2387 | #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff | ||
| 2394 | 2388 | ||
| 2395 | /*P1_AGC2I0*/ | 2389 | /*P1_AGC2I0*/ |
| 2396 | #define R0900_P1_AGC2I0 0xf437 | 2390 | #define R0900_P1_AGC2I0 0xf437 |
| 2397 | #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff | 2391 | #define AGC2I0 REGx(R0900_P1_AGC2I0) |
| 2392 | #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff | ||
| 2398 | 2393 | ||
| 2399 | /*P1_CARCFG*/ | 2394 | /*P1_CARCFG*/ |
| 2400 | #define R0900_P1_CARCFG 0xf438 | 2395 | #define R0900_P1_CARCFG 0xf438 |
| 2401 | #define F0900_P1_CFRUPLOW_AUTO 0xf4380080 | 2396 | #define CARCFG REGx(R0900_P1_CARCFG) |
| 2402 | #define F0900_P1_CFRUPLOW_TEST 0xf4380040 | 2397 | #define F0900_P1_CFRUPLOW_AUTO 0xf4380080 |
| 2403 | #define F0900_P1_EN_CAR2CENTER 0xf4380020 | 2398 | #define F0900_P1_CFRUPLOW_TEST 0xf4380040 |
| 2404 | #define F0900_P1_CARHDR_NODIV8 0xf4380010 | 2399 | #define F0900_P1_ROTAON 0xf4380004 |
| 2405 | #define F0900_P1_I2C_ROTA 0xf4380008 | 2400 | #define F0900_P1_PH_DET_ALGO 0xf4380003 |
| 2406 | #define F0900_P1_ROTAON 0xf4380004 | ||
| 2407 | #define F0900_P1_PH_DET_ALGO 0xf4380003 | ||
| 2408 | 2401 | ||
| 2409 | /*P1_ACLC*/ | 2402 | /*P1_ACLC*/ |
| 2410 | #define R0900_P1_ACLC 0xf439 | 2403 | #define R0900_P1_ACLC 0xf439 |
| 2411 | #define F0900_P1_STOP_S2ALPHA 0xf43900c0 | 2404 | #define ACLC REGx(R0900_P1_ACLC) |
| 2412 | #define F0900_P1_CAR_ALPHA_MANT 0xf4390030 | 2405 | #define F0900_P1_CAR_ALPHA_MANT 0xf4390030 |
| 2413 | #define F0900_P1_CAR_ALPHA_EXP 0xf439000f | 2406 | #define F0900_P1_CAR_ALPHA_EXP 0xf439000f |
| 2414 | 2407 | ||
| 2415 | /*P1_BCLC*/ | 2408 | /*P1_BCLC*/ |
| 2416 | #define R0900_P1_BCLC 0xf43a | 2409 | #define R0900_P1_BCLC 0xf43a |
| 2417 | #define F0900_P1_STOP_S2BETA 0xf43a00c0 | 2410 | #define BCLC REGx(R0900_P1_BCLC) |
| 2418 | #define F0900_P1_CAR_BETA_MANT 0xf43a0030 | 2411 | #define F0900_P1_CAR_BETA_MANT 0xf43a0030 |
| 2419 | #define F0900_P1_CAR_BETA_EXP 0xf43a000f | 2412 | #define F0900_P1_CAR_BETA_EXP 0xf43a000f |
| 2420 | 2413 | ||
| 2421 | /*P1_CARFREQ*/ | 2414 | /*P1_CARFREQ*/ |
| 2422 | #define R0900_P1_CARFREQ 0xf43d | 2415 | #define R0900_P1_CARFREQ 0xf43d |
| 2423 | #define F0900_P1_KC_COARSE_EXP 0xf43d00f0 | 2416 | #define CARFREQ REGx(R0900_P1_CARFREQ) |
| 2424 | #define F0900_P1_BETA_FREQ 0xf43d000f | 2417 | #define F0900_P1_KC_COARSE_EXP 0xf43d00f0 |
| 2418 | #define F0900_P1_BETA_FREQ 0xf43d000f | ||
| 2425 | 2419 | ||
| 2426 | /*P1_CARHDR*/ | 2420 | /*P1_CARHDR*/ |
| 2427 | #define R0900_P1_CARHDR 0xf43e | 2421 | #define R0900_P1_CARHDR 0xf43e |
| 2428 | #define F0900_P1_K_FREQ_HDR 0xf43e00ff | 2422 | #define CARHDR REGx(R0900_P1_CARHDR) |
| 2423 | #define F0900_P1_K_FREQ_HDR 0xf43e00ff | ||
| 2429 | 2424 | ||
| 2430 | /*P1_LDT*/ | 2425 | /*P1_LDT*/ |
| 2431 | #define R0900_P1_LDT 0xf43f | 2426 | #define R0900_P1_LDT 0xf43f |
| 2432 | #define F0900_P1_CARLOCK_THRES 0xf43f01ff | 2427 | #define LDT REGx(R0900_P1_LDT) |
| 2428 | #define F0900_P1_CARLOCK_THRES 0xf43f01ff | ||
| 2433 | 2429 | ||
| 2434 | /*P1_LDT2*/ | 2430 | /*P1_LDT2*/ |
| 2435 | #define R0900_P1_LDT2 0xf440 | 2431 | #define R0900_P1_LDT2 0xf440 |
| 2436 | #define F0900_P1_CARLOCK_THRES2 0xf44001ff | 2432 | #define LDT2 REGx(R0900_P1_LDT2) |
| 2433 | #define F0900_P1_CARLOCK_THRES2 0xf44001ff | ||
| 2437 | 2434 | ||
| 2438 | /*P1_CFRICFG*/ | 2435 | /*P1_CFRICFG*/ |
| 2439 | #define R0900_P1_CFRICFG 0xf441 | 2436 | #define R0900_P1_CFRICFG 0xf441 |
| 2440 | #define F0900_P1_CFRINIT_UNVALRNG 0xf4410080 | 2437 | #define CFRICFG REGx(R0900_P1_CFRICFG) |
| 2441 | #define F0900_P1_CFRINIT_LUNVALCPT 0xf4410040 | 2438 | #define F0900_P1_NEG_CFRSTEP 0xf4410001 |
| 2442 | #define F0900_P1_CFRINIT_ABORTDBL 0xf4410020 | ||
| 2443 | #define F0900_P1_CFRINIT_ABORTPRED 0xf4410010 | ||
| 2444 | #define F0900_P1_CFRINIT_UNVALSKIP 0xf4410008 | ||
| 2445 | #define F0900_P1_CFRINIT_CSTINC 0xf4410004 | ||
| 2446 | #define F0900_P1_NEG_CFRSTEP 0xf4410001 | ||
| 2447 | 2439 | ||
| 2448 | /*P1_CFRUP1*/ | 2440 | /*P1_CFRUP1*/ |
| 2449 | #define R0900_P1_CFRUP1 0xf442 | 2441 | #define R0900_P1_CFRUP1 0xf442 |
| 2450 | #define F0900_P1_CFR_UP1 0xf44201ff | 2442 | #define CFRUP1 REGx(R0900_P1_CFRUP1) |
| 2443 | #define F0900_P1_CFR_UP1 0xf44201ff | ||
| 2444 | #define CFR_UP1 FLDx(F0900_P1_CFR_UP1) | ||
| 2451 | 2445 | ||
| 2452 | /*P1_CFRUP0*/ | 2446 | /*P1_CFRUP0*/ |
| 2453 | #define R0900_P1_CFRUP0 0xf443 | 2447 | #define R0900_P1_CFRUP0 0xf443 |
| 2454 | #define F0900_P1_CFR_UP0 0xf44300ff | 2448 | #define CFRUP0 REGx(R0900_P1_CFRUP0) |
| 2449 | #define F0900_P1_CFR_UP0 0xf44300ff | ||
| 2450 | #define CFR_UP0 FLDx(F0900_P1_CFR_UP0) | ||
| 2455 | 2451 | ||
| 2456 | /*P1_CFRLOW1*/ | 2452 | /*P1_CFRLOW1*/ |
| 2457 | #define R0900_P1_CFRLOW1 0xf446 | 2453 | #define R0900_P1_CFRLOW1 0xf446 |
| 2458 | #define F0900_P1_CFR_LOW1 0xf44601ff | 2454 | #define CFRLOW1 REGx(R0900_P1_CFRLOW1) |
| 2455 | #define F0900_P1_CFR_LOW1 0xf44601ff | ||
| 2456 | #define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1) | ||
| 2459 | 2457 | ||
| 2460 | /*P1_CFRLOW0*/ | 2458 | /*P1_CFRLOW0*/ |
| 2461 | #define R0900_P1_CFRLOW0 0xf447 | 2459 | #define R0900_P1_CFRLOW0 0xf447 |
| 2462 | #define F0900_P1_CFR_LOW0 0xf44700ff | 2460 | #define CFRLOW0 REGx(R0900_P1_CFRLOW0) |
| 2461 | #define F0900_P1_CFR_LOW0 0xf44700ff | ||
| 2462 | #define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0) | ||
| 2463 | 2463 | ||
| 2464 | /*P1_CFRINIT1*/ | 2464 | /*P1_CFRINIT1*/ |
| 2465 | #define R0900_P1_CFRINIT1 0xf448 | 2465 | #define R0900_P1_CFRINIT1 0xf448 |
| 2466 | #define F0900_P1_CFR_INIT1 0xf44801ff | 2466 | #define CFRINIT1 REGx(R0900_P1_CFRINIT1) |
| 2467 | #define F0900_P1_CFR_INIT1 0xf44801ff | ||
| 2468 | #define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1) | ||
| 2467 | 2469 | ||
| 2468 | /*P1_CFRINIT0*/ | 2470 | /*P1_CFRINIT0*/ |
| 2469 | #define R0900_P1_CFRINIT0 0xf449 | 2471 | #define R0900_P1_CFRINIT0 0xf449 |
| 2470 | #define F0900_P1_CFR_INIT0 0xf44900ff | 2472 | #define CFRINIT0 REGx(R0900_P1_CFRINIT0) |
| 2473 | #define F0900_P1_CFR_INIT0 0xf44900ff | ||
| 2474 | #define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0) | ||
| 2471 | 2475 | ||
| 2472 | /*P1_CFRINC1*/ | 2476 | /*P1_CFRINC1*/ |
| 2473 | #define R0900_P1_CFRINC1 0xf44a | 2477 | #define R0900_P1_CFRINC1 0xf44a |
| 2474 | #define F0900_P1_MANUAL_CFRINC 0xf44a0080 | 2478 | #define CFRINC1 REGx(R0900_P1_CFRINC1) |
| 2475 | #define F0900_P1_CFR_INC1 0xf44a017f | 2479 | #define F0900_P1_MANUAL_CFRINC 0xf44a0080 |
| 2480 | #define F0900_P1_CFR_INC1 0xf44a003f | ||
| 2476 | 2481 | ||
| 2477 | /*P1_CFRINC0*/ | 2482 | /*P1_CFRINC0*/ |
| 2478 | #define R0900_P1_CFRINC0 0xf44b | 2483 | #define R0900_P1_CFRINC0 0xf44b |
| 2479 | #define F0900_P1_CFR_INC0 0xf44b00f0 | 2484 | #define CFRINC0 REGx(R0900_P1_CFRINC0) |
| 2485 | #define F0900_P1_CFR_INC0 0xf44b00f8 | ||
| 2480 | 2486 | ||
| 2481 | /*P1_CFR2*/ | 2487 | /*P1_CFR2*/ |
| 2482 | #define R0900_P1_CFR2 0xf44c | 2488 | #define R0900_P1_CFR2 0xf44c |
| 2483 | #define F0900_P1_CAR_FREQ2 0xf44c01ff | 2489 | #define CFR2 REGx(R0900_P1_CFR2) |
| 2490 | #define F0900_P1_CAR_FREQ2 0xf44c01ff | ||
| 2491 | #define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2) | ||
| 2484 | 2492 | ||
| 2485 | /*P1_CFR1*/ | 2493 | /*P1_CFR1*/ |
| 2486 | #define R0900_P1_CFR1 0xf44d | 2494 | #define R0900_P1_CFR1 0xf44d |
| 2487 | #define F0900_P1_CAR_FREQ1 0xf44d00ff | 2495 | #define CFR1 REGx(R0900_P1_CFR1) |
| 2496 | #define F0900_P1_CAR_FREQ1 0xf44d00ff | ||
| 2497 | #define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1) | ||
| 2488 | 2498 | ||
| 2489 | /*P1_CFR0*/ | 2499 | /*P1_CFR0*/ |
| 2490 | #define R0900_P1_CFR0 0xf44e | 2500 | #define R0900_P1_CFR0 0xf44e |
| 2491 | #define F0900_P1_CAR_FREQ0 0xf44e00ff | 2501 | #define CFR0 REGx(R0900_P1_CFR0) |
| 2502 | #define F0900_P1_CAR_FREQ0 0xf44e00ff | ||
| 2503 | #define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0) | ||
| 2492 | 2504 | ||
| 2493 | /*P1_LDI*/ | 2505 | /*P1_LDI*/ |
| 2494 | #define R0900_P1_LDI 0xf44f | 2506 | #define R0900_P1_LDI 0xf44f |
| 2495 | #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff | 2507 | #define LDI REGx(R0900_P1_LDI) |
| 2508 | #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff | ||
| 2496 | 2509 | ||
| 2497 | /*P1_TMGCFG*/ | 2510 | /*P1_TMGCFG*/ |
| 2498 | #define R0900_P1_TMGCFG 0xf450 | 2511 | #define R0900_P1_TMGCFG 0xf450 |
| 2499 | #define F0900_P1_TMGLOCK_BETA 0xf45000c0 | 2512 | #define TMGCFG REGx(R0900_P1_TMGCFG) |
| 2500 | #define F0900_P1_NOTMG_GROUPDELAY 0xf4500020 | 2513 | #define F0900_P1_TMGLOCK_BETA 0xf45000c0 |
| 2501 | #define F0900_P1_DO_TIMING_CORR 0xf4500010 | 2514 | #define F0900_P1_DO_TIMING_CORR 0xf4500010 |
| 2502 | #define F0900_P1_MANUAL_SCAN 0xf450000c | 2515 | #define F0900_P1_TMG_MINFREQ 0xf4500003 |
| 2503 | #define F0900_P1_TMG_MINFREQ 0xf4500003 | ||
| 2504 | 2516 | ||
| 2505 | /*P1_RTC*/ | 2517 | /*P1_RTC*/ |
| 2506 | #define R0900_P1_RTC 0xf451 | 2518 | #define R0900_P1_RTC 0xf451 |
| 2507 | #define F0900_P1_TMGALPHA_EXP 0xf45100f0 | 2519 | #define RTC REGx(R0900_P1_RTC) |
| 2508 | #define F0900_P1_TMGBETA_EXP 0xf451000f | 2520 | #define F0900_P1_TMGALPHA_EXP 0xf45100f0 |
| 2521 | #define F0900_P1_TMGBETA_EXP 0xf451000f | ||
| 2509 | 2522 | ||
| 2510 | /*P1_RTCS2*/ | 2523 | /*P1_RTCS2*/ |
| 2511 | #define R0900_P1_RTCS2 0xf452 | 2524 | #define R0900_P1_RTCS2 0xf452 |
| 2512 | #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0 | 2525 | #define RTCS2 REGx(R0900_P1_RTCS2) |
| 2513 | #define F0900_P1_TMGBETAS2_EXP 0xf452000f | 2526 | #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0 |
| 2527 | #define F0900_P1_TMGBETAS2_EXP 0xf452000f | ||
| 2514 | 2528 | ||
| 2515 | /*P1_TMGTHRISE*/ | 2529 | /*P1_TMGTHRISE*/ |
| 2516 | #define R0900_P1_TMGTHRISE 0xf453 | 2530 | #define R0900_P1_TMGTHRISE 0xf453 |
| 2517 | #define F0900_P1_TMGLOCK_THRISE 0xf45300ff | 2531 | #define TMGTHRISE REGx(R0900_P1_TMGTHRISE) |
| 2532 | #define F0900_P1_TMGLOCK_THRISE 0xf45300ff | ||
| 2518 | 2533 | ||
| 2519 | /*P1_TMGTHFALL*/ | 2534 | /*P1_TMGTHFALL*/ |
| 2520 | #define R0900_P1_TMGTHFALL 0xf454 | 2535 | #define R0900_P1_TMGTHFALL 0xf454 |
| 2521 | #define F0900_P1_TMGLOCK_THFALL 0xf45400ff | 2536 | #define TMGTHFALL REGx(R0900_P1_TMGTHFALL) |
| 2537 | #define F0900_P1_TMGLOCK_THFALL 0xf45400ff | ||
| 2522 | 2538 | ||
| 2523 | /*P1_SFRUPRATIO*/ | 2539 | /*P1_SFRUPRATIO*/ |
| 2524 | #define R0900_P1_SFRUPRATIO 0xf455 | 2540 | #define R0900_P1_SFRUPRATIO 0xf455 |
| 2525 | #define F0900_P1_SFR_UPRATIO 0xf45500ff | 2541 | #define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO) |
| 2542 | #define F0900_P1_SFR_UPRATIO 0xf45500ff | ||
| 2526 | 2543 | ||
| 2527 | /*P1_SFRLOWRATIO*/ | 2544 | /*P1_SFRLOWRATIO*/ |
| 2528 | #define R0900_P1_SFRLOWRATIO 0xf456 | 2545 | #define R0900_P1_SFRLOWRATIO 0xf456 |
| 2529 | #define F0900_P1_SFR_LOWRATIO 0xf45600ff | 2546 | #define F0900_P1_SFR_LOWRATIO 0xf45600ff |
| 2530 | 2547 | ||
| 2531 | /*P1_KREFTMG*/ | 2548 | /*P1_KREFTMG*/ |
| 2532 | #define R0900_P1_KREFTMG 0xf458 | 2549 | #define R0900_P1_KREFTMG 0xf458 |
| 2533 | #define F0900_P1_KREF_TMG 0xf45800ff | 2550 | #define KREFTMG REGx(R0900_P1_KREFTMG) |
| 2551 | #define F0900_P1_KREF_TMG 0xf45800ff | ||
| 2534 | 2552 | ||
| 2535 | /*P1_SFRSTEP*/ | 2553 | /*P1_SFRSTEP*/ |
| 2536 | #define R0900_P1_SFRSTEP 0xf459 | 2554 | #define R0900_P1_SFRSTEP 0xf459 |
| 2537 | #define F0900_P1_SFR_SCANSTEP 0xf45900f0 | 2555 | #define SFRSTEP REGx(R0900_P1_SFRSTEP) |
| 2538 | #define F0900_P1_SFR_CENTERSTEP 0xf459000f | 2556 | #define F0900_P1_SFR_SCANSTEP 0xf45900f0 |
| 2557 | #define F0900_P1_SFR_CENTERSTEP 0xf459000f | ||
| 2539 | 2558 | ||
| 2540 | /*P1_TMGCFG2*/ | 2559 | /*P1_TMGCFG2*/ |
| 2541 | #define R0900_P1_TMGCFG2 0xf45a | 2560 | #define R0900_P1_TMGCFG2 0xf45a |
| 2542 | #define F0900_P1_DIS_AUTOSAMP 0xf45a0008 | 2561 | #define TMGCFG2 REGx(R0900_P1_TMGCFG2) |
| 2543 | #define F0900_P1_SCANINIT_QUART 0xf45a0004 | 2562 | #define F0900_P1_SFRRATIO_FINE 0xf45a0001 |
| 2544 | #define F0900_P1_NOTMG_DVBS1DERAT 0xf45a0002 | 2563 | |
| 2545 | #define F0900_P1_SFRRATIO_FINE 0xf45a0001 | 2564 | /*P1_KREFTMG2*/ |
| 2565 | #define R0900_P1_KREFTMG2 0xf45b | ||
| 2566 | #define KREFTMG2 REGx(R0900_P1_KREFTMG2) | ||
| 2567 | #define F0900_P1_KREF_TMG2 0xf45b00ff | ||
| 2546 | 2568 | ||
| 2547 | /*P1_SFRINIT1*/ | 2569 | /*P1_SFRINIT1*/ |
| 2548 | #define R0900_P1_SFRINIT1 0xf45e | 2570 | #define R0900_P1_SFRINIT1 0xf45e |
| 2549 | #define F0900_P1_SFR_INIT1 0xf45e00ff | 2571 | #define SFRINIT1 REGx(R0900_P1_SFRINIT1) |
| 2572 | #define F0900_P1_SFR_INIT1 0xf45e007f | ||
| 2550 | 2573 | ||
| 2551 | /*P1_SFRINIT0*/ | 2574 | /*P1_SFRINIT0*/ |
| 2552 | #define R0900_P1_SFRINIT0 0xf45f | 2575 | #define R0900_P1_SFRINIT0 0xf45f |
| 2553 | #define F0900_P1_SFR_INIT0 0xf45f00ff | 2576 | #define SFRINIT0 REGx(R0900_P1_SFRINIT0) |
| 2577 | #define F0900_P1_SFR_INIT0 0xf45f00ff | ||
| 2554 | 2578 | ||
| 2555 | /*P1_SFRUP1*/ | 2579 | /*P1_SFRUP1*/ |
| 2556 | #define R0900_P1_SFRUP1 0xf460 | 2580 | #define R0900_P1_SFRUP1 0xf460 |
| 2557 | #define F0900_P1_AUTO_GUP 0xf4600080 | 2581 | #define SFRUP1 REGx(R0900_P1_SFRUP1) |
| 2558 | #define F0900_P1_SYMB_FREQ_UP1 0xf460007f | 2582 | #define F0900_P1_AUTO_GUP 0xf4600080 |
| 2583 | #define AUTO_GUP FLDx(F0900_P1_AUTO_GUP) | ||
| 2584 | #define F0900_P1_SYMB_FREQ_UP1 0xf460007f | ||
| 2559 | 2585 | ||
| 2560 | /*P1_SFRUP0*/ | 2586 | /*P1_SFRUP0*/ |
| 2561 | #define R0900_P1_SFRUP0 0xf461 | 2587 | #define R0900_P1_SFRUP0 0xf461 |
| 2562 | #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff | 2588 | #define SFRUP0 REGx(R0900_P1_SFRUP0) |
| 2589 | #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff | ||
| 2563 | 2590 | ||
| 2564 | /*P1_SFRLOW1*/ | 2591 | /*P1_SFRLOW1*/ |
| 2565 | #define R0900_P1_SFRLOW1 0xf462 | 2592 | #define R0900_P1_SFRLOW1 0xf462 |
| 2566 | #define F0900_P1_AUTO_GLOW 0xf4620080 | 2593 | #define SFRLOW1 REGx(R0900_P1_SFRLOW1) |
| 2567 | #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f | 2594 | #define F0900_P1_AUTO_GLOW 0xf4620080 |
| 2595 | #define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW) | ||
| 2596 | #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f | ||
| 2568 | 2597 | ||
| 2569 | /*P1_SFRLOW0*/ | 2598 | /*P1_SFRLOW0*/ |
| 2570 | #define R0900_P1_SFRLOW0 0xf463 | 2599 | #define R0900_P1_SFRLOW0 0xf463 |
| 2571 | #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff | 2600 | #define SFRLOW0 REGx(R0900_P1_SFRLOW0) |
| 2601 | #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff | ||
| 2572 | 2602 | ||
| 2573 | /*P1_SFR3*/ | 2603 | /*P1_SFR3*/ |
| 2574 | #define R0900_P1_SFR3 0xf464 | 2604 | #define R0900_P1_SFR3 0xf464 |
| 2575 | #define F0900_P1_SYMB_FREQ3 0xf46400ff | 2605 | #define SFR3 REGx(R0900_P1_SFR3) |
| 2606 | #define F0900_P1_SYMB_FREQ3 0xf46400ff | ||
| 2607 | #define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3) | ||
| 2576 | 2608 | ||
| 2577 | /*P1_SFR2*/ | 2609 | /*P1_SFR2*/ |
| 2578 | #define R0900_P1_SFR2 0xf465 | 2610 | #define R0900_P1_SFR2 0xf465 |
| 2579 | #define F0900_P1_SYMB_FREQ2 0xf46500ff | 2611 | #define SFR2 REGx(R0900_P1_SFR2) |
| 2612 | #define F0900_P1_SYMB_FREQ2 0xf46500ff | ||
| 2613 | #define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2) | ||
| 2580 | 2614 | ||
| 2581 | /*P1_SFR1*/ | 2615 | /*P1_SFR1*/ |
| 2582 | #define R0900_P1_SFR1 0xf466 | 2616 | #define R0900_P1_SFR1 0xf466 |
| 2583 | #define F0900_P1_SYMB_FREQ1 0xf46600ff | 2617 | #define SFR1 REGx(R0900_P1_SFR1) |
| 2618 | #define F0900_P1_SYMB_FREQ1 0xf46600ff | ||
| 2619 | #define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1) | ||
| 2584 | 2620 | ||
| 2585 | /*P1_SFR0*/ | 2621 | /*P1_SFR0*/ |
| 2586 | #define R0900_P1_SFR0 0xf467 | 2622 | #define R0900_P1_SFR0 0xf467 |
| 2587 | #define F0900_P1_SYMB_FREQ0 0xf46700ff | 2623 | #define SFR0 REGx(R0900_P1_SFR0) |
| 2624 | #define F0900_P1_SYMB_FREQ0 0xf46700ff | ||
| 2625 | #define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0) | ||
| 2588 | 2626 | ||
| 2589 | /*P1_TMGREG2*/ | 2627 | /*P1_TMGREG2*/ |
| 2590 | #define R0900_P1_TMGREG2 0xf468 | 2628 | #define R0900_P1_TMGREG2 0xf468 |
| 2591 | #define F0900_P1_TMGREG2 0xf46800ff | 2629 | #define TMGREG2 REGx(R0900_P1_TMGREG2) |
| 2630 | #define F0900_P1_TMGREG2 0xf46800ff | ||
| 2592 | 2631 | ||
| 2593 | /*P1_TMGREG1*/ | 2632 | /*P1_TMGREG1*/ |
| 2594 | #define R0900_P1_TMGREG1 0xf469 | 2633 | #define R0900_P1_TMGREG1 0xf469 |
| 2595 | #define F0900_P1_TMGREG1 0xf46900ff | 2634 | #define TMGREG1 REGx(R0900_P1_TMGREG1) |
| 2635 | #define F0900_P1_TMGREG1 0xf46900ff | ||
| 2596 | 2636 | ||
| 2597 | /*P1_TMGREG0*/ | 2637 | /*P1_TMGREG0*/ |
| 2598 | #define R0900_P1_TMGREG0 0xf46a | 2638 | #define R0900_P1_TMGREG0 0xf46a |
| 2599 | #define F0900_P1_TMGREG0 0xf46a00ff | 2639 | #define TMGREG0 REGx(R0900_P1_TMGREG0) |
| 2640 | #define F0900_P1_TMGREG0 0xf46a00ff | ||
| 2600 | 2641 | ||
| 2601 | /*P1_TMGLOCK1*/ | 2642 | /*P1_TMGLOCK1*/ |
| 2602 | #define R0900_P1_TMGLOCK1 0xf46b | 2643 | #define R0900_P1_TMGLOCK1 0xf46b |
| 2603 | #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff | 2644 | #define TMGLOCK1 REGx(R0900_P1_TMGLOCK1) |
| 2645 | #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff | ||
| 2604 | 2646 | ||
| 2605 | /*P1_TMGLOCK0*/ | 2647 | /*P1_TMGLOCK0*/ |
| 2606 | #define R0900_P1_TMGLOCK0 0xf46c | 2648 | #define R0900_P1_TMGLOCK0 0xf46c |
| 2607 | #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff | 2649 | #define TMGLOCK0 REGx(R0900_P1_TMGLOCK0) |
| 2650 | #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff | ||
| 2608 | 2651 | ||
| 2609 | /*P1_TMGOBS*/ | 2652 | /*P1_TMGOBS*/ |
| 2610 | #define R0900_P1_TMGOBS 0xf46d | 2653 | #define R0900_P1_TMGOBS 0xf46d |
| 2611 | #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0 | 2654 | #define TMGOBS REGx(R0900_P1_TMGOBS) |
| 2612 | #define F0900_P1_SCAN_SIGN 0xf46d0030 | 2655 | #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0 |
| 2613 | #define F0900_P1_TMG_SCANNING 0xf46d0008 | 2656 | #define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS) |
| 2614 | #define F0900_P1_CHCENTERING_MODE 0xf46d0004 | ||
| 2615 | #define F0900_P1_TMG_SCANFAIL 0xf46d0002 | ||
| 2616 | 2657 | ||
| 2617 | /*P1_EQUALCFG*/ | 2658 | /*P1_EQUALCFG*/ |
| 2618 | #define R0900_P1_EQUALCFG 0xf46f | 2659 | #define R0900_P1_EQUALCFG 0xf46f |
| 2619 | #define F0900_P1_NOTMG_NEGALWAIT 0xf46f0080 | 2660 | #define EQUALCFG REGx(R0900_P1_EQUALCFG) |
| 2620 | #define F0900_P1_EQUAL_ON 0xf46f0040 | 2661 | #define F0900_P1_EQUAL_ON 0xf46f0040 |
| 2621 | #define F0900_P1_SEL_EQUALCOR 0xf46f0038 | 2662 | #define F0900_P1_MU_EQUALDFE 0xf46f0007 |
| 2622 | #define F0900_P1_MU_EQUALDFE 0xf46f0007 | ||
| 2623 | 2663 | ||
| 2624 | /*P1_EQUAI1*/ | 2664 | /*P1_EQUAI1*/ |
| 2625 | #define R0900_P1_EQUAI1 0xf470 | 2665 | #define R0900_P1_EQUAI1 0xf470 |
| 2626 | #define F0900_P1_EQUA_ACCI1 0xf47001ff | 2666 | #define EQUAI1 REGx(R0900_P1_EQUAI1) |
| 2667 | #define F0900_P1_EQUA_ACCI1 0xf47001ff | ||
| 2627 | 2668 | ||
| 2628 | /*P1_EQUAQ1*/ | 2669 | /*P1_EQUAQ1*/ |
| 2629 | #define R0900_P1_EQUAQ1 0xf471 | 2670 | #define R0900_P1_EQUAQ1 0xf471 |
| 2630 | #define F0900_P1_EQUA_ACCQ1 0xf47101ff | 2671 | #define EQUAQ1 REGx(R0900_P1_EQUAQ1) |
| 2672 | #define F0900_P1_EQUA_ACCQ1 0xf47101ff | ||
| 2631 | 2673 | ||
| 2632 | /*P1_EQUAI2*/ | 2674 | /*P1_EQUAI2*/ |
| 2633 | #define R0900_P1_EQUAI2 0xf472 | 2675 | #define R0900_P1_EQUAI2 0xf472 |
| 2634 | #define F0900_P1_EQUA_ACCI2 0xf47201ff | 2676 | #define EQUAI2 REGx(R0900_P1_EQUAI2) |
| 2677 | #define F0900_P1_EQUA_ACCI2 0xf47201ff | ||
| 2635 | 2678 | ||
| 2636 | /*P1_EQUAQ2*/ | 2679 | /*P1_EQUAQ2*/ |
| 2637 | #define R0900_P1_EQUAQ2 0xf473 | 2680 | #define R0900_P1_EQUAQ2 0xf473 |
| 2638 | #define F0900_P1_EQUA_ACCQ2 0xf47301ff | 2681 | #define EQUAQ2 REGx(R0900_P1_EQUAQ2) |
| 2682 | #define F0900_P1_EQUA_ACCQ2 0xf47301ff | ||
| 2639 | 2683 | ||
| 2640 | /*P1_EQUAI3*/ | 2684 | /*P1_EQUAI3*/ |
| 2641 | #define R0900_P1_EQUAI3 0xf474 | 2685 | #define R0900_P1_EQUAI3 0xf474 |
| 2642 | #define F0900_P1_EQUA_ACCI3 0xf47401ff | 2686 | #define EQUAI3 REGx(R0900_P1_EQUAI3) |
| 2687 | #define F0900_P1_EQUA_ACCI3 0xf47401ff | ||
| 2643 | 2688 | ||
| 2644 | /*P1_EQUAQ3*/ | 2689 | /*P1_EQUAQ3*/ |
| 2645 | #define R0900_P1_EQUAQ3 0xf475 | 2690 | #define R0900_P1_EQUAQ3 0xf475 |
| 2646 | #define F0900_P1_EQUA_ACCQ3 0xf47501ff | 2691 | #define EQUAQ3 REGx(R0900_P1_EQUAQ3) |
| 2692 | #define F0900_P1_EQUA_ACCQ3 0xf47501ff | ||
| 2647 | 2693 | ||
| 2648 | /*P1_EQUAI4*/ | 2694 | /*P1_EQUAI4*/ |
| 2649 | #define R0900_P1_EQUAI4 0xf476 | 2695 | #define R0900_P1_EQUAI4 0xf476 |
| 2650 | #define F0900_P1_EQUA_ACCI4 0xf47601ff | 2696 | #define EQUAI4 REGx(R0900_P1_EQUAI4) |
| 2697 | #define F0900_P1_EQUA_ACCI4 0xf47601ff | ||
| 2651 | 2698 | ||
| 2652 | /*P1_EQUAQ4*/ | 2699 | /*P1_EQUAQ4*/ |
| 2653 | #define R0900_P1_EQUAQ4 0xf477 | 2700 | #define R0900_P1_EQUAQ4 0xf477 |
| 2654 | #define F0900_P1_EQUA_ACCQ4 0xf47701ff | 2701 | #define EQUAQ4 REGx(R0900_P1_EQUAQ4) |
| 2702 | #define F0900_P1_EQUA_ACCQ4 0xf47701ff | ||
| 2655 | 2703 | ||
| 2656 | /*P1_EQUAI5*/ | 2704 | /*P1_EQUAI5*/ |
| 2657 | #define R0900_P1_EQUAI5 0xf478 | 2705 | #define R0900_P1_EQUAI5 0xf478 |
| 2658 | #define F0900_P1_EQUA_ACCI5 0xf47801ff | 2706 | #define EQUAI5 REGx(R0900_P1_EQUAI5) |
| 2707 | #define F0900_P1_EQUA_ACCI5 0xf47801ff | ||
| 2659 | 2708 | ||
| 2660 | /*P1_EQUAQ5*/ | 2709 | /*P1_EQUAQ5*/ |
| 2661 | #define R0900_P1_EQUAQ5 0xf479 | 2710 | #define R0900_P1_EQUAQ5 0xf479 |
| 2662 | #define F0900_P1_EQUA_ACCQ5 0xf47901ff | 2711 | #define EQUAQ5 REGx(R0900_P1_EQUAQ5) |
| 2712 | #define F0900_P1_EQUA_ACCQ5 0xf47901ff | ||
| 2663 | 2713 | ||
| 2664 | /*P1_EQUAI6*/ | 2714 | /*P1_EQUAI6*/ |
| 2665 | #define R0900_P1_EQUAI6 0xf47a | 2715 | #define R0900_P1_EQUAI6 0xf47a |
| 2666 | #define F0900_P1_EQUA_ACCI6 0xf47a01ff | 2716 | #define EQUAI6 REGx(R0900_P1_EQUAI6) |
| 2717 | #define F0900_P1_EQUA_ACCI6 0xf47a01ff | ||
| 2667 | 2718 | ||
| 2668 | /*P1_EQUAQ6*/ | 2719 | /*P1_EQUAQ6*/ |
| 2669 | #define R0900_P1_EQUAQ6 0xf47b | 2720 | #define R0900_P1_EQUAQ6 0xf47b |
| 2670 | #define F0900_P1_EQUA_ACCQ6 0xf47b01ff | 2721 | #define EQUAQ6 REGx(R0900_P1_EQUAQ6) |
| 2722 | #define F0900_P1_EQUA_ACCQ6 0xf47b01ff | ||
| 2671 | 2723 | ||
| 2672 | /*P1_EQUAI7*/ | 2724 | /*P1_EQUAI7*/ |
| 2673 | #define R0900_P1_EQUAI7 0xf47c | 2725 | #define R0900_P1_EQUAI7 0xf47c |
| 2674 | #define F0900_P1_EQUA_ACCI7 0xf47c01ff | 2726 | #define EQUAI7 REGx(R0900_P1_EQUAI7) |
| 2727 | #define F0900_P1_EQUA_ACCI7 0xf47c01ff | ||
| 2675 | 2728 | ||
| 2676 | /*P1_EQUAQ7*/ | 2729 | /*P1_EQUAQ7*/ |
| 2677 | #define R0900_P1_EQUAQ7 0xf47d | 2730 | #define R0900_P1_EQUAQ7 0xf47d |
| 2678 | #define F0900_P1_EQUA_ACCQ7 0xf47d01ff | 2731 | #define EQUAQ7 REGx(R0900_P1_EQUAQ7) |
| 2732 | #define F0900_P1_EQUA_ACCQ7 0xf47d01ff | ||
| 2679 | 2733 | ||
| 2680 | /*P1_EQUAI8*/ | 2734 | /*P1_EQUAI8*/ |
| 2681 | #define R0900_P1_EQUAI8 0xf47e | 2735 | #define R0900_P1_EQUAI8 0xf47e |
| 2682 | #define F0900_P1_EQUA_ACCI8 0xf47e01ff | 2736 | #define EQUAI8 REGx(R0900_P1_EQUAI8) |
| 2737 | #define F0900_P1_EQUA_ACCI8 0xf47e01ff | ||
| 2683 | 2738 | ||
| 2684 | /*P1_EQUAQ8*/ | 2739 | /*P1_EQUAQ8*/ |
| 2685 | #define R0900_P1_EQUAQ8 0xf47f | 2740 | #define R0900_P1_EQUAQ8 0xf47f |
| 2686 | #define F0900_P1_EQUA_ACCQ8 0xf47f01ff | 2741 | #define EQUAQ8 REGx(R0900_P1_EQUAQ8) |
| 2742 | #define F0900_P1_EQUA_ACCQ8 0xf47f01ff | ||
| 2687 | 2743 | ||
| 2688 | /*P1_NNOSDATAT1*/ | 2744 | /*P1_NNOSDATAT1*/ |
| 2689 | #define R0900_P1_NNOSDATAT1 0xf480 | 2745 | #define R0900_P1_NNOSDATAT1 0xf480 |
| 2690 | #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff | 2746 | #define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1) |
| 2747 | #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff | ||
| 2748 | #define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1) | ||
| 2691 | 2749 | ||
| 2692 | /*P1_NNOSDATAT0*/ | 2750 | /*P1_NNOSDATAT0*/ |
| 2693 | #define R0900_P1_NNOSDATAT0 0xf481 | 2751 | #define R0900_P1_NNOSDATAT0 0xf481 |
| 2694 | #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff | 2752 | #define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0) |
| 2753 | #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff | ||
| 2754 | #define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0) | ||
| 2695 | 2755 | ||
| 2696 | /*P1_NNOSDATA1*/ | 2756 | /*P1_NNOSDATA1*/ |
| 2697 | #define R0900_P1_NNOSDATA1 0xf482 | 2757 | #define R0900_P1_NNOSDATA1 0xf482 |
| 2698 | #define F0900_P1_NOSDATA_NORMED1 0xf48200ff | 2758 | #define NNOSDATA1 REGx(R0900_P1_NNOSDATA1) |
| 2759 | #define F0900_P1_NOSDATA_NORMED1 0xf48200ff | ||
| 2699 | 2760 | ||
| 2700 | /*P1_NNOSDATA0*/ | 2761 | /*P1_NNOSDATA0*/ |
| 2701 | #define R0900_P1_NNOSDATA0 0xf483 | 2762 | #define R0900_P1_NNOSDATA0 0xf483 |
| 2702 | #define F0900_P1_NOSDATA_NORMED0 0xf48300ff | 2763 | #define NNOSDATA0 REGx(R0900_P1_NNOSDATA0) |
| 2764 | #define F0900_P1_NOSDATA_NORMED0 0xf48300ff | ||
| 2703 | 2765 | ||
| 2704 | /*P1_NNOSPLHT1*/ | 2766 | /*P1_NNOSPLHT1*/ |
| 2705 | #define R0900_P1_NNOSPLHT1 0xf484 | 2767 | #define R0900_P1_NNOSPLHT1 0xf484 |
| 2706 | #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff | 2768 | #define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1) |
| 2769 | #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff | ||
| 2770 | #define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1) | ||
| 2707 | 2771 | ||
| 2708 | /*P1_NNOSPLHT0*/ | 2772 | /*P1_NNOSPLHT0*/ |
| 2709 | #define R0900_P1_NNOSPLHT0 0xf485 | 2773 | #define R0900_P1_NNOSPLHT0 0xf485 |
| 2710 | #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff | 2774 | #define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0) |
| 2775 | #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff | ||
| 2776 | #define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0) | ||
| 2711 | 2777 | ||
| 2712 | /*P1_NNOSPLH1*/ | 2778 | /*P1_NNOSPLH1*/ |
| 2713 | #define R0900_P1_NNOSPLH1 0xf486 | 2779 | #define R0900_P1_NNOSPLH1 0xf486 |
| 2714 | #define F0900_P1_NOSPLH_NORMED1 0xf48600ff | 2780 | #define NNOSPLH1 REGx(R0900_P1_NNOSPLH1) |
| 2781 | #define F0900_P1_NOSPLH_NORMED1 0xf48600ff | ||
| 2715 | 2782 | ||
| 2716 | /*P1_NNOSPLH0*/ | 2783 | /*P1_NNOSPLH0*/ |
| 2717 | #define R0900_P1_NNOSPLH0 0xf487 | 2784 | #define R0900_P1_NNOSPLH0 0xf487 |
| 2718 | #define F0900_P1_NOSPLH_NORMED0 0xf48700ff | 2785 | #define NNOSPLH0 REGx(R0900_P1_NNOSPLH0) |
| 2786 | #define F0900_P1_NOSPLH_NORMED0 0xf48700ff | ||
| 2719 | 2787 | ||
| 2720 | /*P1_NOSDATAT1*/ | 2788 | /*P1_NOSDATAT1*/ |
| 2721 | #define R0900_P1_NOSDATAT1 0xf488 | 2789 | #define R0900_P1_NOSDATAT1 0xf488 |
| 2722 | #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff | 2790 | #define NOSDATAT1 REGx(R0900_P1_NOSDATAT1) |
| 2791 | #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff | ||
| 2723 | 2792 | ||
| 2724 | /*P1_NOSDATAT0*/ | 2793 | /*P1_NOSDATAT0*/ |
| 2725 | #define R0900_P1_NOSDATAT0 0xf489 | 2794 | #define R0900_P1_NOSDATAT0 0xf489 |
| 2726 | #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff | 2795 | #define NOSDATAT0 REGx(R0900_P1_NOSDATAT0) |
| 2796 | #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff | ||
| 2727 | 2797 | ||
| 2728 | /*P1_NOSDATA1*/ | 2798 | /*P1_NOSDATA1*/ |
| 2729 | #define R0900_P1_NOSDATA1 0xf48a | 2799 | #define R0900_P1_NOSDATA1 0xf48a |
| 2730 | #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff | 2800 | #define NOSDATA1 REGx(R0900_P1_NOSDATA1) |
| 2801 | #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff | ||
| 2731 | 2802 | ||
| 2732 | /*P1_NOSDATA0*/ | 2803 | /*P1_NOSDATA0*/ |
| 2733 | #define R0900_P1_NOSDATA0 0xf48b | 2804 | #define R0900_P1_NOSDATA0 0xf48b |
| 2734 | #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff | 2805 | #define NOSDATA0 REGx(R0900_P1_NOSDATA0) |
| 2806 | #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff | ||
| 2735 | 2807 | ||
| 2736 | /*P1_NOSPLHT1*/ | 2808 | /*P1_NOSPLHT1*/ |
| 2737 | #define R0900_P1_NOSPLHT1 0xf48c | 2809 | #define R0900_P1_NOSPLHT1 0xf48c |
| 2738 | #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff | 2810 | #define NOSPLHT1 REGx(R0900_P1_NOSPLHT1) |
| 2811 | #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff | ||
| 2739 | 2812 | ||
| 2740 | /*P1_NOSPLHT0*/ | 2813 | /*P1_NOSPLHT0*/ |
| 2741 | #define R0900_P1_NOSPLHT0 0xf48d | 2814 | #define R0900_P1_NOSPLHT0 0xf48d |
| 2742 | #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff | 2815 | #define NOSPLHT0 REGx(R0900_P1_NOSPLHT0) |
| 2816 | #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff | ||
| 2743 | 2817 | ||
| 2744 | /*P1_NOSPLH1*/ | 2818 | /*P1_NOSPLH1*/ |
| 2745 | #define R0900_P1_NOSPLH1 0xf48e | 2819 | #define R0900_P1_NOSPLH1 0xf48e |
| 2746 | #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff | 2820 | #define NOSPLH1 REGx(R0900_P1_NOSPLH1) |
| 2821 | #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff | ||
| 2747 | 2822 | ||
| 2748 | /*P1_NOSPLH0*/ | 2823 | /*P1_NOSPLH0*/ |
| 2749 | #define R0900_P1_NOSPLH0 0xf48f | 2824 | #define R0900_P1_NOSPLH0 0xf48f |
| 2750 | #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff | 2825 | #define NOSPLH0 REGx(R0900_P1_NOSPLH0) |
| 2826 | #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff | ||
| 2751 | 2827 | ||
| 2752 | /*P1_CAR2CFG*/ | 2828 | /*P1_CAR2CFG*/ |
| 2753 | #define R0900_P1_CAR2CFG 0xf490 | 2829 | #define R0900_P1_CAR2CFG 0xf490 |
| 2754 | #define F0900_P1_DESCRAMB_OFF 0xf4900080 | 2830 | #define CAR2CFG REGx(R0900_P1_CAR2CFG) |
| 2755 | #define F0900_P1_PN4_SELECT 0xf4900040 | 2831 | #define F0900_P1_CARRIER3_DISABLE 0xf4900040 |
| 2756 | #define F0900_P1_CFR2_STOPDVBS1 0xf4900020 | 2832 | #define F0900_P1_ROTA2ON 0xf4900004 |
| 2757 | #define F0900_P1_STOP_CFR2UPDATE 0xf4900010 | 2833 | #define F0900_P1_PH_DET_ALGO2 0xf4900003 |
| 2758 | #define F0900_P1_STOP_NCO2UPDATE 0xf4900008 | 2834 | |
| 2759 | #define F0900_P1_ROTA2ON 0xf4900004 | 2835 | /*P1_CFR2CFR1*/ |
| 2760 | #define F0900_P1_PH_DET_ALGO2 0xf4900003 | 2836 | #define R0900_P1_CFR2CFR1 0xf491 |
| 2761 | 2837 | #define CFR2CFR1 REGx(R0900_P1_CFR2CFR1) | |
| 2762 | /*P1_ACLC2*/ | 2838 | #define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0 |
| 2763 | #define R0900_P1_ACLC2 0xf491 | 2839 | #define F0900_P1_EN_S2CAR2CENTER 0xf4910020 |
| 2764 | #define F0900_P1_CAR2_PUNCT_ADERAT 0xf4910040 | 2840 | #define F0900_P1_DIS_BCHERRCFR2 0xf4910010 |
| 2765 | #define F0900_P1_CAR2_ALPHA_MANT 0xf4910030 | 2841 | #define F0900_P1_CFR2TOCFR1_BETA 0xf4910007 |
| 2766 | #define F0900_P1_CAR2_ALPHA_EXP 0xf491000f | ||
| 2767 | |||
| 2768 | /*P1_BCLC2*/ | ||
| 2769 | #define R0900_P1_BCLC2 0xf492 | ||
| 2770 | #define F0900_P1_DVBS2_NIP 0xf4920080 | ||
| 2771 | #define F0900_P1_CAR2_PUNCT_BDERAT 0xf4920040 | ||
| 2772 | #define F0900_P1_CAR2_BETA_MANT 0xf4920030 | ||
| 2773 | #define F0900_P1_CAR2_BETA_EXP 0xf492000f | ||
| 2774 | 2842 | ||
| 2775 | /*P1_CFR22*/ | 2843 | /*P1_CFR22*/ |
| 2776 | #define R0900_P1_CFR22 0xf493 | 2844 | #define R0900_P1_CFR22 0xf493 |
| 2777 | #define F0900_P1_CAR2_FREQ2 0xf49301ff | 2845 | #define CFR22 REGx(R0900_P1_CFR22) |
| 2846 | #define F0900_P1_CAR2_FREQ2 0xf49301ff | ||
| 2778 | 2847 | ||
| 2779 | /*P1_CFR21*/ | 2848 | /*P1_CFR21*/ |
| 2780 | #define R0900_P1_CFR21 0xf494 | 2849 | #define R0900_P1_CFR21 0xf494 |
| 2781 | #define F0900_P1_CAR2_FREQ1 0xf49400ff | 2850 | #define CFR21 REGx(R0900_P1_CFR21) |
| 2851 | #define F0900_P1_CAR2_FREQ1 0xf49400ff | ||
| 2782 | 2852 | ||
| 2783 | /*P1_CFR20*/ | 2853 | /*P1_CFR20*/ |
| 2784 | #define R0900_P1_CFR20 0xf495 | 2854 | #define R0900_P1_CFR20 0xf495 |
| 2785 | #define F0900_P1_CAR2_FREQ0 0xf49500ff | 2855 | #define CFR20 REGx(R0900_P1_CFR20) |
| 2856 | #define F0900_P1_CAR2_FREQ0 0xf49500ff | ||
| 2786 | 2857 | ||
| 2787 | /*P1_ACLC2S2Q*/ | 2858 | /*P1_ACLC2S2Q*/ |
| 2788 | #define R0900_P1_ACLC2S2Q 0xf497 | 2859 | #define R0900_P1_ACLC2S2Q 0xf497 |
| 2789 | #define F0900_P1_ENAB_SPSKSYMB 0xf4970080 | 2860 | #define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q) |
| 2790 | #define F0900_P1_CAR2S2_QADERAT 0xf4970040 | 2861 | #define F0900_P1_ENAB_SPSKSYMB 0xf4970080 |
| 2791 | #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030 | 2862 | #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030 |
| 2792 | #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f | 2863 | #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f |
| 2793 | 2864 | ||
| 2794 | /*P1_ACLC2S28*/ | 2865 | /*P1_ACLC2S28*/ |
| 2795 | #define R0900_P1_ACLC2S28 0xf498 | 2866 | #define R0900_P1_ACLC2S28 0xf498 |
| 2796 | #define F0900_P1_OLDI3Q_MODE 0xf4980080 | 2867 | #define ACLC2S28 REGx(R0900_P1_ACLC2S28) |
| 2797 | #define F0900_P1_CAR2S2_8ADERAT 0xf4980040 | 2868 | #define F0900_P1_OLDI3Q_MODE 0xf4980080 |
| 2798 | #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030 | 2869 | #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030 |
| 2799 | #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f | 2870 | #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f |
| 2800 | 2871 | ||
| 2801 | /*P1_ACLC2S216A*/ | 2872 | /*P1_ACLC2S216A*/ |
| 2802 | #define R0900_P1_ACLC2S216A 0xf499 | 2873 | #define R0900_P1_ACLC2S216A 0xf499 |
| 2803 | #define F0900_P1_CAR2S2_16ADERAT 0xf4990040 | 2874 | #define ACLC2S216A REGx(R0900_P1_ACLC2S216A) |
| 2804 | #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030 | 2875 | #define F0900_P1_DIS_C3STOPA2 0xf4990080 |
| 2805 | #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f | 2876 | #define F0900_P1_CAR2S2_16ADERAT 0xf4990040 |
| 2877 | #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030 | ||
| 2878 | #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f | ||
| 2806 | 2879 | ||
| 2807 | /*P1_ACLC2S232A*/ | 2880 | /*P1_ACLC2S232A*/ |
| 2808 | #define R0900_P1_ACLC2S232A 0xf49a | 2881 | #define R0900_P1_ACLC2S232A 0xf49a |
| 2809 | #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040 | 2882 | #define ACLC2S232A REGx(R0900_P1_ACLC2S232A) |
| 2810 | #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030 | 2883 | #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040 |
| 2811 | #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f | 2884 | #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030 |
| 2885 | #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f | ||
| 2812 | 2886 | ||
| 2813 | /*P1_BCLC2S2Q*/ | 2887 | /*P1_BCLC2S2Q*/ |
| 2814 | #define R0900_P1_BCLC2S2Q 0xf49c | 2888 | #define R0900_P1_BCLC2S2Q 0xf49c |
| 2815 | #define F0900_P1_DVBS2S2Q_NIP 0xf49c0080 | 2889 | #define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q) |
| 2816 | #define F0900_P1_CAR2S2_QBDERAT 0xf49c0040 | 2890 | #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030 |
| 2817 | #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030 | 2891 | #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f |
| 2818 | #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f | ||
| 2819 | 2892 | ||
| 2820 | /*P1_BCLC2S28*/ | 2893 | /*P1_BCLC2S28*/ |
| 2821 | #define R0900_P1_BCLC2S28 0xf49d | 2894 | #define R0900_P1_BCLC2S28 0xf49d |
| 2822 | #define F0900_P1_DVBS2S28_NIP 0xf49d0080 | 2895 | #define BCLC2S28 REGx(R0900_P1_BCLC2S28) |
| 2823 | #define F0900_P1_CAR2S2_8BDERAT 0xf49d0040 | 2896 | #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030 |
| 2824 | #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030 | 2897 | #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f |
| 2825 | #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f | ||
| 2826 | 2898 | ||
| 2827 | /*P1_BCLC2S216A*/ | 2899 | /*P1_BCLC2S216A*/ |
| 2828 | #define R0900_P1_BCLC2S216A 0xf49e | 2900 | #define R0900_P1_BCLC2S216A 0xf49e |
| 2829 | #define F0900_P1_DVBS2S216A_NIP 0xf49e0080 | 2901 | #define BCLC2S216A REGx(R0900_P1_BCLC2S216A) |
| 2830 | #define F0900_P1_CAR2S2_16BDERAT 0xf49e0040 | ||
| 2831 | #define F0900_P1_CAR2S2_16A_BETA_M 0xf49e0030 | ||
| 2832 | #define F0900_P1_CAR2S2_16A_BETA_E 0xf49e000f | ||
| 2833 | 2902 | ||
| 2834 | /*P1_BCLC2S232A*/ | 2903 | /*P1_BCLC2S232A*/ |
| 2835 | #define R0900_P1_BCLC2S232A 0xf49f | 2904 | #define R0900_P1_BCLC2S232A 0xf49f |
| 2836 | #define F0900_P1_DVBS2S232A_NIP 0xf49f0080 | 2905 | #define BCLC2S232A REGx(R0900_P1_BCLC2S232A) |
| 2837 | #define F0900_P1_CAR2S2_32BDERAT 0xf49f0040 | ||
| 2838 | #define F0900_P1_CAR2S2_32A_BETA_M 0xf49f0030 | ||
| 2839 | #define F0900_P1_CAR2S2_32A_BETA_E 0xf49f000f | ||
| 2840 | 2906 | ||
| 2841 | /*P1_PLROOT2*/ | 2907 | /*P1_PLROOT2*/ |
| 2842 | #define R0900_P1_PLROOT2 0xf4ac | 2908 | #define R0900_P1_PLROOT2 0xf4ac |
| 2843 | #define F0900_P1_SHORTFR_DISABLE 0xf4ac0080 | 2909 | #define PLROOT2 REGx(R0900_P1_PLROOT2) |
| 2844 | #define F0900_P1_LONGFR_DISABLE 0xf4ac0040 | 2910 | #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c |
| 2845 | #define F0900_P1_DUMMYPL_DISABLE 0xf4ac0020 | 2911 | #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003 |
| 2846 | #define F0900_P1_SHORTFR_AVOID 0xf4ac0010 | ||
| 2847 | #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c | ||
| 2848 | #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003 | ||
| 2849 | 2912 | ||
| 2850 | /*P1_PLROOT1*/ | 2913 | /*P1_PLROOT1*/ |
| 2851 | #define R0900_P1_PLROOT1 0xf4ad | 2914 | #define R0900_P1_PLROOT1 0xf4ad |
| 2852 | #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff | 2915 | #define PLROOT1 REGx(R0900_P1_PLROOT1) |
| 2916 | #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff | ||
| 2853 | 2917 | ||
| 2854 | /*P1_PLROOT0*/ | 2918 | /*P1_PLROOT0*/ |
| 2855 | #define R0900_P1_PLROOT0 0xf4ae | 2919 | #define R0900_P1_PLROOT0 0xf4ae |
| 2856 | #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff | 2920 | #define PLROOT0 REGx(R0900_P1_PLROOT0) |
| 2921 | #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff | ||
| 2857 | 2922 | ||
| 2858 | /*P1_MODCODLST0*/ | 2923 | /*P1_MODCODLST0*/ |
| 2859 | #define R0900_P1_MODCODLST0 0xf4b0 | 2924 | #define R0900_P1_MODCODLST0 0xf4b0 |
| 2860 | #define F0900_P1_EN_TOKEN31 0xf4b00080 | 2925 | #define MODCODLST0 REGx(R0900_P1_MODCODLST0) |
| 2861 | #define F0900_P1_SYNCTAG_SELECT 0xf4b00040 | ||
| 2862 | #define F0900_P1_MODCODRQ_MODE 0xf4b00030 | ||
| 2863 | 2926 | ||
| 2864 | /*P1_MODCODLST1*/ | 2927 | /*P1_MODCODLST1*/ |
| 2865 | #define R0900_P1_MODCODLST1 0xf4b1 | 2928 | #define R0900_P1_MODCODLST1 0xf4b1 |
| 2866 | #define F0900_P1_DIS_MODCOD29 0xf4b100f0 | 2929 | #define MODCODLST1 REGx(R0900_P1_MODCODLST1) |
| 2867 | #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f | 2930 | #define F0900_P1_DIS_MODCOD29 0xf4b100f0 |
| 2931 | #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f | ||
| 2868 | 2932 | ||
| 2869 | /*P1_MODCODLST2*/ | 2933 | /*P1_MODCODLST2*/ |
| 2870 | #define R0900_P1_MODCODLST2 0xf4b2 | 2934 | #define R0900_P1_MODCODLST2 0xf4b2 |
| 2871 | #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0 | 2935 | #define MODCODLST2 REGx(R0900_P1_MODCODLST2) |
| 2872 | #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f | 2936 | #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0 |
| 2937 | #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f | ||
| 2873 | 2938 | ||
| 2874 | /*P1_MODCODLST3*/ | 2939 | /*P1_MODCODLST3*/ |
| 2875 | #define R0900_P1_MODCODLST3 0xf4b3 | 2940 | #define R0900_P1_MODCODLST3 0xf4b3 |
| 2876 | #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0 | 2941 | #define MODCODLST3 REGx(R0900_P1_MODCODLST3) |
| 2877 | #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f | 2942 | #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0 |
| 2943 | #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f | ||
| 2878 | 2944 | ||
| 2879 | /*P1_MODCODLST4*/ | 2945 | /*P1_MODCODLST4*/ |
| 2880 | #define R0900_P1_MODCODLST4 0xf4b4 | 2946 | #define R0900_P1_MODCODLST4 0xf4b4 |
| 2881 | #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0 | 2947 | #define MODCODLST4 REGx(R0900_P1_MODCODLST4) |
| 2882 | #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f | 2948 | #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0 |
| 2949 | #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f | ||
| 2883 | 2950 | ||
| 2884 | /*P1_MODCODLST5*/ | 2951 | /*P1_MODCODLST5*/ |
| 2885 | #define R0900_P1_MODCODLST5 0xf4b5 | 2952 | #define R0900_P1_MODCODLST5 0xf4b5 |
| 2886 | #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0 | 2953 | #define MODCODLST5 REGx(R0900_P1_MODCODLST5) |
| 2887 | #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f | 2954 | #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0 |
| 2955 | #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f | ||
| 2888 | 2956 | ||
| 2889 | /*P1_MODCODLST6*/ | 2957 | /*P1_MODCODLST6*/ |
| 2890 | #define R0900_P1_MODCODLST6 0xf4b6 | 2958 | #define R0900_P1_MODCODLST6 0xf4b6 |
| 2891 | #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0 | 2959 | #define MODCODLST6 REGx(R0900_P1_MODCODLST6) |
| 2892 | #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f | 2960 | #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0 |
| 2961 | #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f | ||
| 2893 | 2962 | ||
| 2894 | /*P1_MODCODLST7*/ | 2963 | /*P1_MODCODLST7*/ |
| 2895 | #define R0900_P1_MODCODLST7 0xf4b7 | 2964 | #define R0900_P1_MODCODLST7 0xf4b7 |
| 2896 | #define F0900_P1_DIS_8P_9_10 0xf4b700f0 | 2965 | #define MODCODLST7 REGx(R0900_P1_MODCODLST7) |
| 2897 | #define F0900_P1_DIS_8P_8_9 0xf4b7000f | 2966 | #define F0900_P1_DIS_8P_9_10 0xf4b700f0 |
| 2967 | #define F0900_P1_DIS_8P_8_9 0xf4b7000f | ||
| 2898 | 2968 | ||
| 2899 | /*P1_MODCODLST8*/ | 2969 | /*P1_MODCODLST8*/ |
| 2900 | #define R0900_P1_MODCODLST8 0xf4b8 | 2970 | #define R0900_P1_MODCODLST8 0xf4b8 |
| 2901 | #define F0900_P1_DIS_8P_5_6 0xf4b800f0 | 2971 | #define MODCODLST8 REGx(R0900_P1_MODCODLST8) |
| 2902 | #define F0900_P1_DIS_8P_3_4 0xf4b8000f | 2972 | #define F0900_P1_DIS_8P_5_6 0xf4b800f0 |
| 2973 | #define F0900_P1_DIS_8P_3_4 0xf4b8000f | ||
| 2903 | 2974 | ||
| 2904 | /*P1_MODCODLST9*/ | 2975 | /*P1_MODCODLST9*/ |
| 2905 | #define R0900_P1_MODCODLST9 0xf4b9 | 2976 | #define R0900_P1_MODCODLST9 0xf4b9 |
| 2906 | #define F0900_P1_DIS_8P_2_3 0xf4b900f0 | 2977 | #define MODCODLST9 REGx(R0900_P1_MODCODLST9) |
| 2907 | #define F0900_P1_DIS_8P_3_5 0xf4b9000f | 2978 | #define F0900_P1_DIS_8P_2_3 0xf4b900f0 |
| 2979 | #define F0900_P1_DIS_8P_3_5 0xf4b9000f | ||
| 2908 | 2980 | ||
| 2909 | /*P1_MODCODLSTA*/ | 2981 | /*P1_MODCODLSTA*/ |
| 2910 | #define R0900_P1_MODCODLSTA 0xf4ba | 2982 | #define R0900_P1_MODCODLSTA 0xf4ba |
| 2911 | #define F0900_P1_DIS_QP_9_10 0xf4ba00f0 | 2983 | #define MODCODLSTA REGx(R0900_P1_MODCODLSTA) |
| 2912 | #define F0900_P1_DIS_QP_8_9 0xf4ba000f | 2984 | #define F0900_P1_DIS_QP_9_10 0xf4ba00f0 |
| 2985 | #define F0900_P1_DIS_QP_8_9 0xf4ba000f | ||
| 2913 | 2986 | ||
| 2914 | /*P1_MODCODLSTB*/ | 2987 | /*P1_MODCODLSTB*/ |
| 2915 | #define R0900_P1_MODCODLSTB 0xf4bb | 2988 | #define R0900_P1_MODCODLSTB 0xf4bb |
| 2916 | #define F0900_P1_DIS_QP_5_6 0xf4bb00f0 | 2989 | #define MODCODLSTB REGx(R0900_P1_MODCODLSTB) |
| 2917 | #define F0900_P1_DIS_QP_4_5 0xf4bb000f | 2990 | #define F0900_P1_DIS_QP_5_6 0xf4bb00f0 |
| 2991 | #define F0900_P1_DIS_QP_4_5 0xf4bb000f | ||
| 2918 | 2992 | ||
| 2919 | /*P1_MODCODLSTC*/ | 2993 | /*P1_MODCODLSTC*/ |
| 2920 | #define R0900_P1_MODCODLSTC 0xf4bc | 2994 | #define R0900_P1_MODCODLSTC 0xf4bc |
| 2921 | #define F0900_P1_DIS_QP_3_4 0xf4bc00f0 | 2995 | #define MODCODLSTC REGx(R0900_P1_MODCODLSTC) |
| 2922 | #define F0900_P1_DIS_QP_2_3 0xf4bc000f | 2996 | #define F0900_P1_DIS_QP_3_4 0xf4bc00f0 |
| 2997 | #define F0900_P1_DIS_QP_2_3 0xf4bc000f | ||
| 2923 | 2998 | ||
| 2924 | /*P1_MODCODLSTD*/ | 2999 | /*P1_MODCODLSTD*/ |
| 2925 | #define R0900_P1_MODCODLSTD 0xf4bd | 3000 | #define R0900_P1_MODCODLSTD 0xf4bd |
| 2926 | #define F0900_P1_DIS_QP_3_5 0xf4bd00f0 | 3001 | #define MODCODLSTD REGx(R0900_P1_MODCODLSTD) |
| 2927 | #define F0900_P1_DIS_QP_1_2 0xf4bd000f | 3002 | #define F0900_P1_DIS_QP_3_5 0xf4bd00f0 |
| 3003 | #define F0900_P1_DIS_QP_1_2 0xf4bd000f | ||
| 2928 | 3004 | ||
| 2929 | /*P1_MODCODLSTE*/ | 3005 | /*P1_MODCODLSTE*/ |
| 2930 | #define R0900_P1_MODCODLSTE 0xf4be | 3006 | #define R0900_P1_MODCODLSTE 0xf4be |
| 2931 | #define F0900_P1_DIS_QP_2_5 0xf4be00f0 | 3007 | #define MODCODLSTE REGx(R0900_P1_MODCODLSTE) |
| 2932 | #define F0900_P1_DIS_QP_1_3 0xf4be000f | 3008 | #define F0900_P1_DIS_QP_2_5 0xf4be00f0 |
| 3009 | #define F0900_P1_DIS_QP_1_3 0xf4be000f | ||
| 2933 | 3010 | ||
| 2934 | /*P1_MODCODLSTF*/ | 3011 | /*P1_MODCODLSTF*/ |
| 2935 | #define R0900_P1_MODCODLSTF 0xf4bf | 3012 | #define R0900_P1_MODCODLSTF 0xf4bf |
| 2936 | #define F0900_P1_DIS_QP_1_4 0xf4bf00f0 | 3013 | #define MODCODLSTF REGx(R0900_P1_MODCODLSTF) |
| 2937 | #define F0900_P1_DDEMOD_SET 0xf4bf0002 | 3014 | #define F0900_P1_DIS_QP_1_4 0xf4bf00f0 |
| 2938 | #define F0900_P1_DDEMOD_MASK 0xf4bf0001 | 3015 | |
| 3016 | /*P1_GAUSSR0*/ | ||
| 3017 | #define R0900_P1_GAUSSR0 0xf4c0 | ||
| 3018 | #define GAUSSR0 REGx(R0900_P1_GAUSSR0) | ||
| 3019 | #define F0900_P1_EN_CCIMODE 0xf4c00080 | ||
| 3020 | #define F0900_P1_R0_GAUSSIEN 0xf4c0007f | ||
| 3021 | |||
| 3022 | /*P1_CCIR0*/ | ||
| 3023 | #define R0900_P1_CCIR0 0xf4c1 | ||
| 3024 | #define CCIR0 REGx(R0900_P1_CCIR0) | ||
| 3025 | #define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080 | ||
| 3026 | #define F0900_P1_R0_CCI 0xf4c1007f | ||
| 3027 | |||
| 3028 | /*P1_CCIQUANT*/ | ||
| 3029 | #define R0900_P1_CCIQUANT 0xf4c2 | ||
| 3030 | #define CCIQUANT REGx(R0900_P1_CCIQUANT) | ||
| 3031 | #define F0900_P1_CCI_BETA 0xf4c200e0 | ||
| 3032 | #define F0900_P1_CCI_QUANT 0xf4c2001f | ||
| 3033 | |||
| 3034 | /*P1_CCITHRES*/ | ||
| 3035 | #define R0900_P1_CCITHRES 0xf4c3 | ||
| 3036 | #define CCITHRES REGx(R0900_P1_CCITHRES) | ||
| 3037 | #define F0900_P1_CCI_THRESHOLD 0xf4c300ff | ||
| 3038 | |||
| 3039 | /*P1_CCIACC*/ | ||
| 3040 | #define R0900_P1_CCIACC 0xf4c4 | ||
| 3041 | #define CCIACC REGx(R0900_P1_CCIACC) | ||
| 3042 | #define F0900_P1_CCI_VALUE 0xf4c400ff | ||
| 2939 | 3043 | ||
| 2940 | /*P1_DMDRESCFG*/ | 3044 | /*P1_DMDRESCFG*/ |
| 2941 | #define R0900_P1_DMDRESCFG 0xf4c6 | 3045 | #define R0900_P1_DMDRESCFG 0xf4c6 |
| 2942 | #define F0900_P1_DMDRES_RESET 0xf4c60080 | 3046 | #define DMDRESCFG REGx(R0900_P1_DMDRESCFG) |
| 2943 | #define F0900_P1_DMDRES_NOISESQR 0xf4c60010 | 3047 | #define F0900_P1_DMDRES_RESET 0xf4c60080 |
| 2944 | #define F0900_P1_DMDRES_STRALL 0xf4c60008 | 3048 | #define F0900_P1_DMDRES_STRALL 0xf4c60008 |
| 2945 | #define F0900_P1_DMDRES_NEWONLY 0xf4c60004 | 3049 | #define F0900_P1_DMDRES_NEWONLY 0xf4c60004 |
| 2946 | #define F0900_P1_DMDRES_NOSTORE 0xf4c60002 | 3050 | #define F0900_P1_DMDRES_NOSTORE 0xf4c60002 |
| 2947 | #define F0900_P1_DMDRES_AGC2MEM 0xf4c60001 | ||
| 2948 | 3051 | ||
| 2949 | /*P1_DMDRESADR*/ | 3052 | /*P1_DMDRESADR*/ |
| 2950 | #define R0900_P1_DMDRESADR 0xf4c7 | 3053 | #define R0900_P1_DMDRESADR 0xf4c7 |
| 2951 | #define F0900_P1_SUSP_PREDCANAL 0xf4c70080 | 3054 | #define DMDRESADR REGx(R0900_P1_DMDRESADR) |
| 2952 | #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040 | 3055 | #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040 |
| 2953 | #define F0900_P1_DMDRES_MEMFULL 0xf4c70030 | 3056 | #define F0900_P1_DMDRES_MEMFULL 0xf4c70030 |
| 2954 | #define F0900_P1_DMDRES_RESNBR 0xf4c7000f | 3057 | #define F0900_P1_DMDRES_RESNBR 0xf4c7000f |
| 2955 | 3058 | ||
| 2956 | /*P1_DMDRESDATA7*/ | 3059 | /*P1_DMDRESDATA7*/ |
| 2957 | #define R0900_P1_DMDRESDATA7 0xf4c8 | 3060 | #define R0900_P1_DMDRESDATA7 0xf4c8 |
| 2958 | #define F0900_P1_DMDRES_DATA7 0xf4c800ff | 3061 | #define F0900_P1_DMDRES_DATA7 0xf4c800ff |
| 2959 | 3062 | ||
| 2960 | /*P1_DMDRESDATA6*/ | 3063 | /*P1_DMDRESDATA6*/ |
| 2961 | #define R0900_P1_DMDRESDATA6 0xf4c9 | 3064 | #define R0900_P1_DMDRESDATA6 0xf4c9 |
| 2962 | #define F0900_P1_DMDRES_DATA6 0xf4c900ff | 3065 | #define F0900_P1_DMDRES_DATA6 0xf4c900ff |
| 2963 | 3066 | ||
| 2964 | /*P1_DMDRESDATA5*/ | 3067 | /*P1_DMDRESDATA5*/ |
| 2965 | #define R0900_P1_DMDRESDATA5 0xf4ca | 3068 | #define R0900_P1_DMDRESDATA5 0xf4ca |
| 2966 | #define F0900_P1_DMDRES_DATA5 0xf4ca00ff | 3069 | #define F0900_P1_DMDRES_DATA5 0xf4ca00ff |
| 2967 | 3070 | ||
| 2968 | /*P1_DMDRESDATA4*/ | 3071 | /*P1_DMDRESDATA4*/ |
| 2969 | #define R0900_P1_DMDRESDATA4 0xf4cb | 3072 | #define R0900_P1_DMDRESDATA4 0xf4cb |
| 2970 | #define F0900_P1_DMDRES_DATA4 0xf4cb00ff | 3073 | #define F0900_P1_DMDRES_DATA4 0xf4cb00ff |
| 2971 | 3074 | ||
| 2972 | /*P1_DMDRESDATA3*/ | 3075 | /*P1_DMDRESDATA3*/ |
| 2973 | #define R0900_P1_DMDRESDATA3 0xf4cc | 3076 | #define R0900_P1_DMDRESDATA3 0xf4cc |
| 2974 | #define F0900_P1_DMDRES_DATA3 0xf4cc00ff | 3077 | #define F0900_P1_DMDRES_DATA3 0xf4cc00ff |
| 2975 | 3078 | ||
| 2976 | /*P1_DMDRESDATA2*/ | 3079 | /*P1_DMDRESDATA2*/ |
| 2977 | #define R0900_P1_DMDRESDATA2 0xf4cd | 3080 | #define R0900_P1_DMDRESDATA2 0xf4cd |
| 2978 | #define F0900_P1_DMDRES_DATA2 0xf4cd00ff | 3081 | #define F0900_P1_DMDRES_DATA2 0xf4cd00ff |
| 2979 | 3082 | ||
| 2980 | /*P1_DMDRESDATA1*/ | 3083 | /*P1_DMDRESDATA1*/ |
| 2981 | #define R0900_P1_DMDRESDATA1 0xf4ce | 3084 | #define R0900_P1_DMDRESDATA1 0xf4ce |
| 2982 | #define F0900_P1_DMDRES_DATA1 0xf4ce00ff | 3085 | #define F0900_P1_DMDRES_DATA1 0xf4ce00ff |
| 2983 | 3086 | ||
| 2984 | /*P1_DMDRESDATA0*/ | 3087 | /*P1_DMDRESDATA0*/ |
| 2985 | #define R0900_P1_DMDRESDATA0 0xf4cf | 3088 | #define R0900_P1_DMDRESDATA0 0xf4cf |
| 2986 | #define F0900_P1_DMDRES_DATA0 0xf4cf00ff | 3089 | #define F0900_P1_DMDRES_DATA0 0xf4cf00ff |
| 2987 | 3090 | ||
| 2988 | /*P1_FFEI1*/ | 3091 | /*P1_FFEI1*/ |
| 2989 | #define R0900_P1_FFEI1 0xf4d0 | 3092 | #define R0900_P1_FFEI1 0xf4d0 |
| 2990 | #define F0900_P1_FFE_ACCI1 0xf4d001ff | 3093 | #define FFEI1 REGx(R0900_P1_FFEI1) |
| 3094 | #define F0900_P1_FFE_ACCI1 0xf4d001ff | ||
| 2991 | 3095 | ||
| 2992 | /*P1_FFEQ1*/ | 3096 | /*P1_FFEQ1*/ |
| 2993 | #define R0900_P1_FFEQ1 0xf4d1 | 3097 | #define R0900_P1_FFEQ1 0xf4d1 |
| 2994 | #define F0900_P1_FFE_ACCQ1 0xf4d101ff | 3098 | #define FFEQ1 REGx(R0900_P1_FFEQ1) |
| 3099 | #define F0900_P1_FFE_ACCQ1 0xf4d101ff | ||
| 2995 | 3100 | ||
| 2996 | /*P1_FFEI2*/ | 3101 | /*P1_FFEI2*/ |
| 2997 | #define R0900_P1_FFEI2 0xf4d2 | 3102 | #define R0900_P1_FFEI2 0xf4d2 |
| 2998 | #define F0900_P1_FFE_ACCI2 0xf4d201ff | 3103 | #define FFEI2 REGx(R0900_P1_FFEI2) |
| 3104 | #define F0900_P1_FFE_ACCI2 0xf4d201ff | ||
| 2999 | 3105 | ||
| 3000 | /*P1_FFEQ2*/ | 3106 | /*P1_FFEQ2*/ |
| 3001 | #define R0900_P1_FFEQ2 0xf4d3 | 3107 | #define R0900_P1_FFEQ2 0xf4d3 |
| 3002 | #define F0900_P1_FFE_ACCQ2 0xf4d301ff | 3108 | #define FFEQ2 REGx(R0900_P1_FFEQ2) |
| 3109 | #define F0900_P1_FFE_ACCQ2 0xf4d301ff | ||
| 3003 | 3110 | ||
| 3004 | /*P1_FFEI3*/ | 3111 | /*P1_FFEI3*/ |
| 3005 | #define R0900_P1_FFEI3 0xf4d4 | 3112 | #define R0900_P1_FFEI3 0xf4d4 |
| 3006 | #define F0900_P1_FFE_ACCI3 0xf4d401ff | 3113 | #define FFEI3 REGx(R0900_P1_FFEI3) |
| 3114 | #define F0900_P1_FFE_ACCI3 0xf4d401ff | ||
| 3007 | 3115 | ||
| 3008 | /*P1_FFEQ3*/ | 3116 | /*P1_FFEQ3*/ |
| 3009 | #define R0900_P1_FFEQ3 0xf4d5 | 3117 | #define R0900_P1_FFEQ3 0xf4d5 |
| 3010 | #define F0900_P1_FFE_ACCQ3 0xf4d501ff | 3118 | #define FFEQ3 REGx(R0900_P1_FFEQ3) |
| 3119 | #define F0900_P1_FFE_ACCQ3 0xf4d501ff | ||
| 3011 | 3120 | ||
| 3012 | /*P1_FFEI4*/ | 3121 | /*P1_FFEI4*/ |
| 3013 | #define R0900_P1_FFEI4 0xf4d6 | 3122 | #define R0900_P1_FFEI4 0xf4d6 |
| 3014 | #define F0900_P1_FFE_ACCI4 0xf4d601ff | 3123 | #define FFEI4 REGx(R0900_P1_FFEI4) |
| 3124 | #define F0900_P1_FFE_ACCI4 0xf4d601ff | ||
| 3015 | 3125 | ||
| 3016 | /*P1_FFEQ4*/ | 3126 | /*P1_FFEQ4*/ |
| 3017 | #define R0900_P1_FFEQ4 0xf4d7 | 3127 | #define R0900_P1_FFEQ4 0xf4d7 |
| 3018 | #define F0900_P1_FFE_ACCQ4 0xf4d701ff | 3128 | #define FFEQ4 REGx(R0900_P1_FFEQ4) |
| 3129 | #define F0900_P1_FFE_ACCQ4 0xf4d701ff | ||
| 3019 | 3130 | ||
| 3020 | /*P1_FFECFG*/ | 3131 | /*P1_FFECFG*/ |
| 3021 | #define R0900_P1_FFECFG 0xf4d8 | 3132 | #define R0900_P1_FFECFG 0xf4d8 |
| 3022 | #define F0900_P1_EQUALFFE_ON 0xf4d80040 | 3133 | #define FFECFG REGx(R0900_P1_FFECFG) |
| 3023 | #define F0900_P1_EQUAL_USEDSYMB 0xf4d80030 | 3134 | #define F0900_P1_EQUALFFE_ON 0xf4d80040 |
| 3024 | #define F0900_P1_MU_EQUALFFE 0xf4d80007 | 3135 | #define F0900_P1_MU_EQUALFFE 0xf4d80007 |
| 3025 | 3136 | ||
| 3026 | /*P1_TNRCFG*/ | 3137 | /*P1_TNRCFG*/ |
| 3027 | #define R0900_P1_TNRCFG 0xf4e0 | 3138 | #define R0900_P1_TNRCFG 0xf4e0 |
| 3028 | #define F0900_P1_TUN_ACKFAIL 0xf4e00080 | 3139 | #define TNRCFG REGx(R0900_P1_TNRCFG) |
| 3029 | #define F0900_P1_TUN_TYPE 0xf4e00070 | 3140 | #define F0900_P1_TUN_ACKFAIL 0xf4e00080 |
| 3030 | #define F0900_P1_TUN_SECSTOP 0xf4e00008 | 3141 | #define F0900_P1_TUN_TYPE 0xf4e00070 |
| 3031 | #define F0900_P1_TUN_VCOSRCH 0xf4e00004 | 3142 | #define F0900_P1_TUN_SECSTOP 0xf4e00008 |
| 3032 | #define F0900_P1_TUN_MADDRESS 0xf4e00003 | 3143 | #define F0900_P1_TUN_VCOSRCH 0xf4e00004 |
| 3144 | #define F0900_P1_TUN_MADDRESS 0xf4e00003 | ||
| 3033 | 3145 | ||
| 3034 | /*P1_TNRCFG2*/ | 3146 | /*P1_TNRCFG2*/ |
| 3035 | #define R0900_P1_TNRCFG2 0xf4e1 | 3147 | #define R0900_P1_TNRCFG2 0xf4e1 |
| 3036 | #define F0900_P1_TUN_IQSWAP 0xf4e10080 | 3148 | #define TNRCFG2 REGx(R0900_P1_TNRCFG2) |
| 3037 | #define F0900_P1_STB6110_STEP2MHZ 0xf4e10040 | 3149 | #define F0900_P1_TUN_IQSWAP 0xf4e10080 |
| 3038 | #define F0900_P1_STB6120_DBLI2C 0xf4e10020 | 3150 | #define F0900_P1_DIS_BWCALC 0xf4e10004 |
| 3039 | #define F0900_P1_DIS_FCCK 0xf4e10010 | 3151 | #define F0900_P1_SHORT_WAITSTATES 0xf4e10002 |
| 3040 | #define F0900_P1_DIS_LPEN 0xf4e10008 | ||
| 3041 | #define F0900_P1_DIS_BWCALC 0xf4e10004 | ||
| 3042 | #define F0900_P1_SHORT_WAITSTATES 0xf4e10002 | ||
| 3043 | #define F0900_P1_DIS_2BWAGC1 0xf4e10001 | ||
| 3044 | 3152 | ||
| 3045 | /*P1_TNRXTAL*/ | 3153 | /*P1_TNRXTAL*/ |
| 3046 | #define R0900_P1_TNRXTAL 0xf4e4 | 3154 | #define R0900_P1_TNRXTAL 0xf4e4 |
| 3047 | #define F0900_P1_TUN_MCLKDECIMAL 0xf4e400e0 | 3155 | #define TNRXTAL REGx(R0900_P1_TNRXTAL) |
| 3048 | #define F0900_P1_TUN_XTALFREQ 0xf4e4001f | 3156 | #define F0900_P1_TUN_XTALFREQ 0xf4e4001f |
| 3049 | 3157 | ||
| 3050 | /*P1_TNRSTEPS*/ | 3158 | /*P1_TNRSTEPS*/ |
| 3051 | #define R0900_P1_TNRSTEPS 0xf4e7 | 3159 | #define R0900_P1_TNRSTEPS 0xf4e7 |
| 3052 | #define F0900_P1_TUNER_BW1P6 0xf4e70080 | 3160 | #define TNRSTEPS REGx(R0900_P1_TNRSTEPS) |
| 3053 | #define F0900_P1_BWINC_OFFSET 0xf4e70070 | 3161 | #define F0900_P1_TUNER_BW0P125 0xf4e70080 |
| 3054 | #define F0900_P1_SOFTSTEP_RNG 0xf4e70008 | 3162 | #define F0900_P1_BWINC_OFFSET 0xf4e70170 |
| 3055 | #define F0900_P1_TUN_BWOFFSET 0xf4e70107 | 3163 | #define F0900_P1_SOFTSTEP_RNG 0xf4e70008 |
| 3164 | #define F0900_P1_TUN_BWOFFSET 0xf4e70007 | ||
| 3056 | 3165 | ||
| 3057 | /*P1_TNRGAIN*/ | 3166 | /*P1_TNRGAIN*/ |
| 3058 | #define R0900_P1_TNRGAIN 0xf4e8 | 3167 | #define R0900_P1_TNRGAIN 0xf4e8 |
| 3059 | #define F0900_P1_TUN_KDIVEN 0xf4e800c0 | 3168 | #define TNRGAIN REGx(R0900_P1_TNRGAIN) |
| 3060 | #define F0900_P1_STB6X00_OCK 0xf4e80030 | 3169 | #define F0900_P1_TUN_KDIVEN 0xf4e800c0 |
| 3061 | #define F0900_P1_TUN_GAIN 0xf4e8000f | 3170 | #define F0900_P1_STB6X00_OCK 0xf4e80030 |
| 3171 | #define F0900_P1_TUN_GAIN 0xf4e8000f | ||
| 3062 | 3172 | ||
| 3063 | /*P1_TNRRF1*/ | 3173 | /*P1_TNRRF1*/ |
| 3064 | #define R0900_P1_TNRRF1 0xf4e9 | 3174 | #define R0900_P1_TNRRF1 0xf4e9 |
| 3065 | #define F0900_P1_TUN_RFFREQ2 0xf4e900ff | 3175 | #define TNRRF1 REGx(R0900_P1_TNRRF1) |
| 3176 | #define F0900_P1_TUN_RFFREQ2 0xf4e900ff | ||
| 3066 | 3177 | ||
| 3067 | /*P1_TNRRF0*/ | 3178 | /*P1_TNRRF0*/ |
| 3068 | #define R0900_P1_TNRRF0 0xf4ea | 3179 | #define R0900_P1_TNRRF0 0xf4ea |
| 3069 | #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff | 3180 | #define TNRRF0 REGx(R0900_P1_TNRRF0) |
| 3181 | #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff | ||
| 3070 | 3182 | ||
| 3071 | /*P1_TNRBW*/ | 3183 | /*P1_TNRBW*/ |
| 3072 | #define R0900_P1_TNRBW 0xf4eb | 3184 | #define R0900_P1_TNRBW 0xf4eb |
| 3073 | #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0 | 3185 | #define TNRBW REGx(R0900_P1_TNRBW) |
| 3074 | #define F0900_P1_TUN_BW 0xf4eb003f | 3186 | #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0 |
| 3187 | #define F0900_P1_TUN_BW 0xf4eb003f | ||
| 3075 | 3188 | ||
| 3076 | /*P1_TNRADJ*/ | 3189 | /*P1_TNRADJ*/ |
| 3077 | #define R0900_P1_TNRADJ 0xf4ec | 3190 | #define R0900_P1_TNRADJ 0xf4ec |
| 3078 | #define F0900_P1_STB61X0_RCLK 0xf4ec0080 | 3191 | #define TNRADJ REGx(R0900_P1_TNRADJ) |
| 3079 | #define F0900_P1_STB61X0_CALTIME 0xf4ec0040 | 3192 | #define F0900_P1_STB61X0_CALTIME 0xf4ec0040 |
| 3080 | #define F0900_P1_STB6X00_DLB 0xf4ec0038 | ||
| 3081 | #define F0900_P1_STB6000_FCL 0xf4ec0007 | ||
| 3082 | 3193 | ||
| 3083 | /*P1_TNRCTL2*/ | 3194 | /*P1_TNRCTL2*/ |
| 3084 | #define R0900_P1_TNRCTL2 0xf4ed | 3195 | #define R0900_P1_TNRCTL2 0xf4ed |
| 3085 | #define F0900_P1_STB61X0_LCP1_RCCKOFF 0xf4ed0080 | 3196 | #define TNRCTL2 REGx(R0900_P1_TNRCTL2) |
| 3086 | #define F0900_P1_STB61X0_LCP0 0xf4ed0040 | 3197 | #define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080 |
| 3087 | #define F0900_P1_STB61X0_XTOUT_RFOUTS 0xf4ed0020 | 3198 | #define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040 |
| 3088 | #define F0900_P1_STB61X0_XTON_MCKDV 0xf4ed0010 | 3199 | #define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020 |
| 3089 | #define F0900_P1_STB61X0_CALOFF_DCOFF 0xf4ed0008 | 3200 | #define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010 |
| 3090 | #define F0900_P1_STB6110_LPT 0xf4ed0004 | 3201 | #define F0900_P1_STB61X0_CALOFF 0xf4ed0008 |
| 3091 | #define F0900_P1_STB6110_RX 0xf4ed0002 | 3202 | #define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004 |
| 3092 | #define F0900_P1_STB6110_SYN 0xf4ed0001 | 3203 | #define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002 |
| 3204 | #define F0900_P1_STB6XX0_SYN 0xf4ed0001 | ||
| 3093 | 3205 | ||
| 3094 | /*P1_TNRCFG3*/ | 3206 | /*P1_TNRCFG3*/ |
| 3095 | #define R0900_P1_TNRCFG3 0xf4ee | 3207 | #define R0900_P1_TNRCFG3 0xf4ee |
| 3096 | #define F0900_P1_STB6120_DISCTRL1 0xf4ee0080 | 3208 | #define TNRCFG3 REGx(R0900_P1_TNRCFG3) |
| 3097 | #define F0900_P1_STB6120_INVORDER 0xf4ee0040 | 3209 | #define F0900_P1_TUN_PLLFREQ 0xf4ee001c |
| 3098 | #define F0900_P1_STB6120_ENCTRL6 0xf4ee0020 | 3210 | #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003 |
| 3099 | #define F0900_P1_TUN_PLLFREQ 0xf4ee001c | ||
| 3100 | #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003 | ||
| 3101 | 3211 | ||
| 3102 | /*P1_TNRLAUNCH*/ | 3212 | /*P1_TNRLAUNCH*/ |
| 3103 | #define R0900_P1_TNRLAUNCH 0xf4f0 | 3213 | #define R0900_P1_TNRLAUNCH 0xf4f0 |
| 3214 | #define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH) | ||
| 3104 | 3215 | ||
| 3105 | /*P1_TNRLD*/ | 3216 | /*P1_TNRLD*/ |
| 3106 | #define R0900_P1_TNRLD 0xf4f0 | 3217 | #define R0900_P1_TNRLD 0xf4f0 |
| 3107 | #define F0900_P1_TUNLD_VCOING 0xf4f00080 | 3218 | #define TNRLD REGx(R0900_P1_TNRLD) |
| 3108 | #define F0900_P1_TUN_REG1FAIL 0xf4f00040 | 3219 | #define F0900_P1_TUNLD_VCOING 0xf4f00080 |
| 3109 | #define F0900_P1_TUN_REG2FAIL 0xf4f00020 | 3220 | #define F0900_P1_TUN_REG1FAIL 0xf4f00040 |
| 3110 | #define F0900_P1_TUN_REG3FAIL 0xf4f00010 | 3221 | #define F0900_P1_TUN_REG2FAIL 0xf4f00020 |
| 3111 | #define F0900_P1_TUN_REG4FAIL 0xf4f00008 | 3222 | #define F0900_P1_TUN_REG3FAIL 0xf4f00010 |
| 3112 | #define F0900_P1_TUN_REG5FAIL 0xf4f00004 | 3223 | #define F0900_P1_TUN_REG4FAIL 0xf4f00008 |
| 3113 | #define F0900_P1_TUN_BWING 0xf4f00002 | 3224 | #define F0900_P1_TUN_REG5FAIL 0xf4f00004 |
| 3114 | #define F0900_P1_TUN_LOCKED 0xf4f00001 | 3225 | #define F0900_P1_TUN_BWING 0xf4f00002 |
| 3226 | #define F0900_P1_TUN_LOCKED 0xf4f00001 | ||
| 3115 | 3227 | ||
| 3116 | /*P1_TNROBSL*/ | 3228 | /*P1_TNROBSL*/ |
| 3117 | #define R0900_P1_TNROBSL 0xf4f6 | 3229 | #define R0900_P1_TNROBSL 0xf4f6 |
| 3118 | #define F0900_P1_TUN_I2CABORTED 0xf4f60080 | 3230 | #define TNROBSL REGx(R0900_P1_TNROBSL) |
| 3119 | #define F0900_P1_TUN_LPEN 0xf4f60040 | 3231 | #define F0900_P1_TUN_I2CABORTED 0xf4f60080 |
| 3120 | #define F0900_P1_TUN_FCCK 0xf4f60020 | 3232 | #define F0900_P1_TUN_LPEN 0xf4f60040 |
| 3121 | #define F0900_P1_TUN_I2CLOCKED 0xf4f60010 | 3233 | #define F0900_P1_TUN_FCCK 0xf4f60020 |
| 3122 | #define F0900_P1_TUN_PROGDONE 0xf4f6000c | 3234 | #define F0900_P1_TUN_I2CLOCKED 0xf4f60010 |
| 3123 | #define F0900_P1_TUN_RFRESTE1 0xf4f60003 | 3235 | #define F0900_P1_TUN_PROGDONE 0xf4f6000c |
| 3236 | #define F0900_P1_TUN_RFRESTE1 0xf4f60003 | ||
| 3124 | 3237 | ||
| 3125 | /*P1_TNRRESTE*/ | 3238 | /*P1_TNRRESTE*/ |
| 3126 | #define R0900_P1_TNRRESTE 0xf4f7 | 3239 | #define R0900_P1_TNRRESTE 0xf4f7 |
| 3127 | #define F0900_P1_TUN_RFRESTE0 0xf4f700ff | 3240 | #define TNRRESTE REGx(R0900_P1_TNRRESTE) |
| 3241 | #define F0900_P1_TUN_RFRESTE0 0xf4f700ff | ||
| 3128 | 3242 | ||
| 3129 | /*P1_SMAPCOEF7*/ | 3243 | /*P1_SMAPCOEF7*/ |
| 3130 | #define R0900_P1_SMAPCOEF7 0xf500 | 3244 | #define R0900_P1_SMAPCOEF7 0xf500 |
| 3131 | #define F0900_P1_DIS_QSCALE 0xf5000080 | 3245 | #define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7) |
| 3132 | #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f | 3246 | #define F0900_P1_DIS_QSCALE 0xf5000080 |
| 3247 | #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f | ||
| 3133 | 3248 | ||
| 3134 | /*P1_SMAPCOEF6*/ | 3249 | /*P1_SMAPCOEF6*/ |
| 3135 | #define R0900_P1_SMAPCOEF6 0xf501 | 3250 | #define R0900_P1_SMAPCOEF6 0xf501 |
| 3136 | #define F0900_P1_DIS_NEWSCALE 0xf5010008 | 3251 | #define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6) |
| 3137 | #define F0900_P1_ADJ_8PSKLLR1 0xf5010004 | 3252 | #define F0900_P1_ADJ_8PSKLLR1 0xf5010004 |
| 3138 | #define F0900_P1_OLD_8PSKLLR1 0xf5010002 | 3253 | #define F0900_P1_OLD_8PSKLLR1 0xf5010002 |
| 3139 | #define F0900_P1_DIS_AB8PSK 0xf5010001 | 3254 | #define F0900_P1_DIS_AB8PSK 0xf5010001 |
| 3140 | 3255 | ||
| 3141 | /*P1_SMAPCOEF5*/ | 3256 | /*P1_SMAPCOEF5*/ |
| 3142 | #define R0900_P1_SMAPCOEF5 0xf502 | 3257 | #define R0900_P1_SMAPCOEF5 0xf502 |
| 3143 | #define F0900_P1_DIS_8SCALE 0xf5020080 | 3258 | #define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5) |
| 3144 | #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f | 3259 | #define F0900_P1_DIS_8SCALE 0xf5020080 |
| 3260 | #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f | ||
| 3261 | |||
| 3262 | /*P1_NCO2MAX1*/ | ||
| 3263 | #define R0900_P1_NCO2MAX1 0xf514 | ||
| 3264 | #define NCO2MAX1 REGx(R0900_P1_NCO2MAX1) | ||
| 3265 | #define F0900_P1_TETA2_MAXVABS1 0xf51400ff | ||
| 3266 | |||
| 3267 | /*P1_NCO2MAX0*/ | ||
| 3268 | #define R0900_P1_NCO2MAX0 0xf515 | ||
| 3269 | #define NCO2MAX0 REGx(R0900_P1_NCO2MAX0) | ||
| 3270 | #define F0900_P1_TETA2_MAXVABS0 0xf51500ff | ||
| 3271 | |||
| 3272 | /*P1_NCO2FR1*/ | ||
| 3273 | #define R0900_P1_NCO2FR1 0xf516 | ||
| 3274 | #define NCO2FR1 REGx(R0900_P1_NCO2FR1) | ||
| 3275 | #define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff | ||
| 3276 | |||
| 3277 | /*P1_NCO2FR0*/ | ||
| 3278 | #define R0900_P1_NCO2FR0 0xf517 | ||
| 3279 | #define NCO2FR0 REGx(R0900_P1_NCO2FR0) | ||
| 3280 | #define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff | ||
| 3281 | |||
| 3282 | /*P1_CFR2AVRGE1*/ | ||
| 3283 | #define R0900_P1_CFR2AVRGE1 0xf518 | ||
| 3284 | #define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1) | ||
| 3285 | #define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff | ||
| 3286 | |||
| 3287 | /*P1_CFR2AVRGE0*/ | ||
| 3288 | #define R0900_P1_CFR2AVRGE0 0xf519 | ||
| 3289 | #define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0) | ||
| 3290 | #define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff | ||
| 3145 | 3291 | ||
| 3146 | /*P1_DMDPLHSTAT*/ | 3292 | /*P1_DMDPLHSTAT*/ |
| 3147 | #define R0900_P1_DMDPLHSTAT 0xf520 | 3293 | #define R0900_P1_DMDPLHSTAT 0xf520 |
| 3148 | #define F0900_P1_PLH_STATISTIC 0xf52000ff | 3294 | #define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT) |
| 3295 | #define F0900_P1_PLH_STATISTIC 0xf52000ff | ||
| 3149 | 3296 | ||
| 3150 | /*P1_LOCKTIME3*/ | 3297 | /*P1_LOCKTIME3*/ |
| 3151 | #define R0900_P1_LOCKTIME3 0xf522 | 3298 | #define R0900_P1_LOCKTIME3 0xf522 |
| 3152 | #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff | 3299 | #define LOCKTIME3 REGx(R0900_P1_LOCKTIME3) |
| 3300 | #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff | ||
| 3153 | 3301 | ||
| 3154 | /*P1_LOCKTIME2*/ | 3302 | /*P1_LOCKTIME2*/ |
| 3155 | #define R0900_P1_LOCKTIME2 0xf523 | 3303 | #define R0900_P1_LOCKTIME2 0xf523 |
| 3156 | #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff | 3304 | #define LOCKTIME2 REGx(R0900_P1_LOCKTIME2) |
| 3305 | #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff | ||
| 3157 | 3306 | ||
| 3158 | /*P1_LOCKTIME1*/ | 3307 | /*P1_LOCKTIME1*/ |
| 3159 | #define R0900_P1_LOCKTIME1 0xf524 | 3308 | #define R0900_P1_LOCKTIME1 0xf524 |
| 3160 | #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff | 3309 | #define LOCKTIME1 REGx(R0900_P1_LOCKTIME1) |
| 3310 | #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff | ||
| 3161 | 3311 | ||
| 3162 | /*P1_LOCKTIME0*/ | 3312 | /*P1_LOCKTIME0*/ |
| 3163 | #define R0900_P1_LOCKTIME0 0xf525 | 3313 | #define R0900_P1_LOCKTIME0 0xf525 |
| 3164 | #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff | 3314 | #define LOCKTIME0 REGx(R0900_P1_LOCKTIME0) |
| 3315 | #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff | ||
| 3165 | 3316 | ||
| 3166 | /*P1_VITSCALE*/ | 3317 | /*P1_VITSCALE*/ |
| 3167 | #define R0900_P1_VITSCALE 0xf532 | 3318 | #define R0900_P1_VITSCALE 0xf532 |
| 3168 | #define F0900_P1_NVTH_NOSRANGE 0xf5320080 | 3319 | #define VITSCALE REGx(R0900_P1_VITSCALE) |
| 3169 | #define F0900_P1_VERROR_MAXMODE 0xf5320040 | 3320 | #define F0900_P1_NVTH_NOSRANGE 0xf5320080 |
| 3170 | #define F0900_P1_KDIV_MODE 0xf5320030 | 3321 | #define F0900_P1_VERROR_MAXMODE 0xf5320040 |
| 3171 | #define F0900_P1_NSLOWSN_LOCKED 0xf5320008 | 3322 | #define F0900_P1_NSLOWSN_LOCKED 0xf5320008 |
| 3172 | #define F0900_P1_DELOCK_PRFLOSS 0xf5320004 | 3323 | #define F0900_P1_DIS_RSFLOCK 0xf5320002 |
| 3173 | #define F0900_P1_DIS_RSFLOCK 0xf5320002 | ||
| 3174 | 3324 | ||
| 3175 | /*P1_FECM*/ | 3325 | /*P1_FECM*/ |
| 3176 | #define R0900_P1_FECM 0xf533 | 3326 | #define R0900_P1_FECM 0xf533 |
| 3177 | #define F0900_P1_DSS_DVB 0xf5330080 | 3327 | #define FECM REGx(R0900_P1_FECM) |
| 3178 | #define F0900_P1_DEMOD_BYPASS 0xf5330040 | 3328 | #define F0900_P1_DSS_DVB 0xf5330080 |
| 3179 | #define F0900_P1_CMP_SLOWMODE 0xf5330020 | 3329 | #define DSS_DVB FLDx(F0900_P1_DSS_DVB) |
| 3180 | #define F0900_P1_DSS_SRCH 0xf5330010 | 3330 | #define F0900_P1_DSS_SRCH 0xf5330010 |
| 3181 | #define F0900_P1_DIFF_MODEVIT 0xf5330004 | 3331 | #define F0900_P1_SYNCVIT 0xf5330002 |
| 3182 | #define F0900_P1_SYNCVIT 0xf5330002 | 3332 | #define F0900_P1_IQINV 0xf5330001 |
| 3183 | #define F0900_P1_IQINV 0xf5330001 | 3333 | #define IQINV FLDx(F0900_P1_IQINV) |
| 3184 | 3334 | ||
| 3185 | /*P1_VTH12*/ | 3335 | /*P1_VTH12*/ |
| 3186 | #define R0900_P1_VTH12 0xf534 | 3336 | #define R0900_P1_VTH12 0xf534 |
| 3187 | #define F0900_P1_VTH12 0xf53400ff | 3337 | #define VTH12 REGx(R0900_P1_VTH12) |
| 3338 | #define F0900_P1_VTH12 0xf53400ff | ||
| 3188 | 3339 | ||
| 3189 | /*P1_VTH23*/ | 3340 | /*P1_VTH23*/ |
| 3190 | #define R0900_P1_VTH23 0xf535 | 3341 | #define R0900_P1_VTH23 0xf535 |
| 3191 | #define F0900_P1_VTH23 0xf53500ff | 3342 | #define VTH23 REGx(R0900_P1_VTH23) |
| 3343 | #define F0900_P1_VTH23 0xf53500ff | ||
| 3192 | 3344 | ||
| 3193 | /*P1_VTH34*/ | 3345 | /*P1_VTH34*/ |
| 3194 | #define R0900_P1_VTH34 0xf536 | 3346 | #define R0900_P1_VTH34 0xf536 |
| 3195 | #define F0900_P1_VTH34 0xf53600ff | 3347 | #define VTH34 REGx(R0900_P1_VTH34) |
| 3348 | #define F0900_P1_VTH34 0xf53600ff | ||
| 3196 | 3349 | ||
| 3197 | /*P1_VTH56*/ | 3350 | /*P1_VTH56*/ |
| 3198 | #define R0900_P1_VTH56 0xf537 | 3351 | #define R0900_P1_VTH56 0xf537 |
| 3199 | #define F0900_P1_VTH56 0xf53700ff | 3352 | #define VTH56 REGx(R0900_P1_VTH56) |
| 3353 | #define F0900_P1_VTH56 0xf53700ff | ||
| 3200 | 3354 | ||
| 3201 | /*P1_VTH67*/ | 3355 | /*P1_VTH67*/ |
| 3202 | #define R0900_P1_VTH67 0xf538 | 3356 | #define R0900_P1_VTH67 0xf538 |
| 3203 | #define F0900_P1_VTH67 0xf53800ff | 3357 | #define VTH67 REGx(R0900_P1_VTH67) |
| 3358 | #define F0900_P1_VTH67 0xf53800ff | ||
| 3204 | 3359 | ||
| 3205 | /*P1_VTH78*/ | 3360 | /*P1_VTH78*/ |
| 3206 | #define R0900_P1_VTH78 0xf539 | 3361 | #define R0900_P1_VTH78 0xf539 |
| 3207 | #define F0900_P1_VTH78 0xf53900ff | 3362 | #define VTH78 REGx(R0900_P1_VTH78) |
| 3363 | #define F0900_P1_VTH78 0xf53900ff | ||
| 3208 | 3364 | ||
| 3209 | /*P1_VITCURPUN*/ | 3365 | /*P1_VITCURPUN*/ |
| 3210 | #define R0900_P1_VITCURPUN 0xf53a | 3366 | #define R0900_P1_VITCURPUN 0xf53a |
| 3211 | #define F0900_P1_VIT_MAPPING 0xf53a00e0 | 3367 | #define VITCURPUN REGx(R0900_P1_VITCURPUN) |
| 3212 | #define F0900_P1_VIT_CURPUN 0xf53a001f | 3368 | #define F0900_P1_VIT_CURPUN 0xf53a001f |
| 3369 | #define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN) | ||
| 3213 | 3370 | ||
| 3214 | /*P1_VERROR*/ | 3371 | /*P1_VERROR*/ |
| 3215 | #define R0900_P1_VERROR 0xf53b | 3372 | #define R0900_P1_VERROR 0xf53b |
| 3216 | #define F0900_P1_REGERR_VIT 0xf53b00ff | 3373 | #define VERROR REGx(R0900_P1_VERROR) |
| 3374 | #define F0900_P1_REGERR_VIT 0xf53b00ff | ||
| 3217 | 3375 | ||
| 3218 | /*P1_PRVIT*/ | 3376 | /*P1_PRVIT*/ |
| 3219 | #define R0900_P1_PRVIT 0xf53c | 3377 | #define R0900_P1_PRVIT 0xf53c |
| 3220 | #define F0900_P1_DIS_VTHLOCK 0xf53c0040 | 3378 | #define PRVIT REGx(R0900_P1_PRVIT) |
| 3221 | #define F0900_P1_E7_8VIT 0xf53c0020 | 3379 | #define F0900_P1_DIS_VTHLOCK 0xf53c0040 |
| 3222 | #define F0900_P1_E6_7VIT 0xf53c0010 | 3380 | #define F0900_P1_E7_8VIT 0xf53c0020 |
| 3223 | #define F0900_P1_E5_6VIT 0xf53c0008 | 3381 | #define F0900_P1_E6_7VIT 0xf53c0010 |
| 3224 | #define F0900_P1_E3_4VIT 0xf53c0004 | 3382 | #define F0900_P1_E5_6VIT 0xf53c0008 |
| 3225 | #define F0900_P1_E2_3VIT 0xf53c0002 | 3383 | #define F0900_P1_E3_4VIT 0xf53c0004 |
| 3226 | #define F0900_P1_E1_2VIT 0xf53c0001 | 3384 | #define F0900_P1_E2_3VIT 0xf53c0002 |
| 3385 | #define F0900_P1_E1_2VIT 0xf53c0001 | ||
| 3227 | 3386 | ||
| 3228 | /*P1_VAVSRVIT*/ | 3387 | /*P1_VAVSRVIT*/ |
| 3229 | #define R0900_P1_VAVSRVIT 0xf53d | 3388 | #define R0900_P1_VAVSRVIT 0xf53d |
| 3230 | #define F0900_P1_AMVIT 0xf53d0080 | 3389 | #define VAVSRVIT REGx(R0900_P1_VAVSRVIT) |
| 3231 | #define F0900_P1_FROZENVIT 0xf53d0040 | 3390 | #define F0900_P1_AMVIT 0xf53d0080 |
| 3232 | #define F0900_P1_SNVIT 0xf53d0030 | 3391 | #define F0900_P1_FROZENVIT 0xf53d0040 |
| 3233 | #define F0900_P1_TOVVIT 0xf53d000c | 3392 | #define F0900_P1_SNVIT 0xf53d0030 |
| 3234 | #define F0900_P1_HYPVIT 0xf53d0003 | 3393 | #define F0900_P1_TOVVIT 0xf53d000c |
| 3394 | #define F0900_P1_HYPVIT 0xf53d0003 | ||
| 3235 | 3395 | ||
| 3236 | /*P1_VSTATUSVIT*/ | 3396 | /*P1_VSTATUSVIT*/ |
| 3237 | #define R0900_P1_VSTATUSVIT 0xf53e | 3397 | #define R0900_P1_VSTATUSVIT 0xf53e |
| 3238 | #define F0900_P1_VITERBI_ON 0xf53e0080 | 3398 | #define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT) |
| 3239 | #define F0900_P1_END_LOOPVIT 0xf53e0040 | 3399 | #define F0900_P1_PRFVIT 0xf53e0010 |
| 3240 | #define F0900_P1_VITERBI_DEPRF 0xf53e0020 | 3400 | #define PRFVIT FLDx(F0900_P1_PRFVIT) |
| 3241 | #define F0900_P1_PRFVIT 0xf53e0010 | 3401 | #define F0900_P1_LOCKEDVIT 0xf53e0008 |
| 3242 | #define F0900_P1_LOCKEDVIT 0xf53e0008 | 3402 | #define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT) |
| 3243 | #define F0900_P1_VITERBI_DELOCK 0xf53e0004 | ||
| 3244 | #define F0900_P1_VIT_DEMODSEL 0xf53e0002 | ||
| 3245 | #define F0900_P1_VITERBI_COMPOUT 0xf53e0001 | ||
| 3246 | 3403 | ||
| 3247 | /*P1_VTHINUSE*/ | 3404 | /*P1_VTHINUSE*/ |
| 3248 | #define R0900_P1_VTHINUSE 0xf53f | 3405 | #define R0900_P1_VTHINUSE 0xf53f |
| 3249 | #define F0900_P1_VIT_INUSE 0xf53f00ff | 3406 | #define VTHINUSE REGx(R0900_P1_VTHINUSE) |
| 3407 | #define F0900_P1_VIT_INUSE 0xf53f00ff | ||
| 3250 | 3408 | ||
| 3251 | /*P1_KDIV12*/ | 3409 | /*P1_KDIV12*/ |
| 3252 | #define R0900_P1_KDIV12 0xf540 | 3410 | #define R0900_P1_KDIV12 0xf540 |
| 3253 | #define F0900_P1_KDIV12_MANUAL 0xf5400080 | 3411 | #define KDIV12 REGx(R0900_P1_KDIV12) |
| 3254 | #define F0900_P1_K_DIVIDER_12 0xf540007f | 3412 | #define F0900_P1_K_DIVIDER_12 0xf540007f |
| 3255 | 3413 | ||
| 3256 | /*P1_KDIV23*/ | 3414 | /*P1_KDIV23*/ |
| 3257 | #define R0900_P1_KDIV23 0xf541 | 3415 | #define R0900_P1_KDIV23 0xf541 |
| 3258 | #define F0900_P1_KDIV23_MANUAL 0xf5410080 | 3416 | #define KDIV23 REGx(R0900_P1_KDIV23) |
| 3259 | #define F0900_P1_K_DIVIDER_23 0xf541007f | 3417 | #define F0900_P1_K_DIVIDER_23 0xf541007f |
| 3260 | 3418 | ||
| 3261 | /*P1_KDIV34*/ | 3419 | /*P1_KDIV34*/ |
| 3262 | #define R0900_P1_KDIV34 0xf542 | 3420 | #define R0900_P1_KDIV34 0xf542 |
| 3263 | #define F0900_P1_KDIV34_MANUAL 0xf5420080 | 3421 | #define KDIV34 REGx(R0900_P1_KDIV34) |
| 3264 | #define F0900_P1_K_DIVIDER_34 0xf542007f | 3422 | #define F0900_P1_K_DIVIDER_34 0xf542007f |
| 3265 | 3423 | ||
| 3266 | /*P1_KDIV56*/ | 3424 | /*P1_KDIV56*/ |
| 3267 | #define R0900_P1_KDIV56 0xf543 | 3425 | #define R0900_P1_KDIV56 0xf543 |
| 3268 | #define F0900_P1_KDIV56_MANUAL 0xf5430080 | 3426 | #define KDIV56 REGx(R0900_P1_KDIV56) |
| 3269 | #define F0900_P1_K_DIVIDER_56 0xf543007f | 3427 | #define F0900_P1_K_DIVIDER_56 0xf543007f |
| 3270 | 3428 | ||
| 3271 | /*P1_KDIV67*/ | 3429 | /*P1_KDIV67*/ |
| 3272 | #define R0900_P1_KDIV67 0xf544 | 3430 | #define R0900_P1_KDIV67 0xf544 |
| 3273 | #define F0900_P1_KDIV67_MANUAL 0xf5440080 | 3431 | #define KDIV67 REGx(R0900_P1_KDIV67) |
| 3274 | #define F0900_P1_K_DIVIDER_67 0xf544007f | 3432 | #define F0900_P1_K_DIVIDER_67 0xf544007f |
| 3275 | 3433 | ||
| 3276 | /*P1_KDIV78*/ | 3434 | /*P1_KDIV78*/ |
| 3277 | #define R0900_P1_KDIV78 0xf545 | 3435 | #define R0900_P1_KDIV78 0xf545 |
| 3278 | #define F0900_P1_KDIV78_MANUAL 0xf5450080 | 3436 | #define KDIV78 REGx(R0900_P1_KDIV78) |
| 3279 | #define F0900_P1_K_DIVIDER_78 0xf545007f | 3437 | #define F0900_P1_K_DIVIDER_78 0xf545007f |
| 3280 | 3438 | ||
| 3281 | /*P1_PDELCTRL1*/ | 3439 | /*P1_PDELCTRL1*/ |
| 3282 | #define R0900_P1_PDELCTRL1 0xf550 | 3440 | #define R0900_P1_PDELCTRL1 0xf550 |
| 3283 | #define F0900_P1_INV_MISMASK 0xf5500080 | 3441 | #define PDELCTRL1 REGx(R0900_P1_PDELCTRL1) |
| 3284 | #define F0900_P1_FORCE_ACCEPTED 0xf5500040 | 3442 | #define F0900_P1_INV_MISMASK 0xf5500080 |
| 3285 | #define F0900_P1_FILTER_EN 0xf5500020 | 3443 | #define F0900_P1_FILTER_EN 0xf5500020 |
| 3286 | #define F0900_P1_FORCE_PKTDELINUSE 0xf5500010 | 3444 | #define F0900_P1_EN_MIS00 0xf5500002 |
| 3287 | #define F0900_P1_HYSTEN 0xf5500008 | 3445 | #define F0900_P1_ALGOSWRST 0xf5500001 |
| 3288 | #define F0900_P1_HYSTSWRST 0xf5500004 | 3446 | #define ALGOSWRST FLDx(F0900_P1_ALGOSWRST) |
| 3289 | #define F0900_P1_EN_MIS00 0xf5500002 | ||
| 3290 | #define F0900_P1_ALGOSWRST 0xf5500001 | ||
| 3291 | 3447 | ||
| 3292 | /*P1_PDELCTRL2*/ | 3448 | /*P1_PDELCTRL2*/ |
| 3293 | #define R0900_P1_PDELCTRL2 0xf551 | 3449 | #define R0900_P1_PDELCTRL2 0xf551 |
| 3294 | #define F0900_P1_FORCE_CONTINUOUS 0xf5510080 | 3450 | #define PDELCTRL2 REGx(R0900_P1_PDELCTRL2) |
| 3295 | #define F0900_P1_RESET_UPKO_COUNT 0xf5510040 | 3451 | #define F0900_P1_RESET_UPKO_COUNT 0xf5510040 |
| 3296 | #define F0900_P1_USER_PKTDELIN_NB 0xf5510020 | 3452 | #define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT) |
| 3297 | #define F0900_P1_FORCE_LOCKED 0xf5510010 | 3453 | #define F0900_P1_FRAME_MODE 0xf5510002 |
| 3298 | #define F0900_P1_DATA_UNBBSCRAM 0xf5510008 | 3454 | #define F0900_P1_NOBCHERRFLG_USE 0xf5510001 |
| 3299 | #define F0900_P1_FORCE_LONGPKT 0xf5510004 | ||
| 3300 | #define F0900_P1_FRAME_MODE 0xf5510002 | ||
| 3301 | 3455 | ||
| 3302 | /*P1_HYSTTHRESH*/ | 3456 | /*P1_HYSTTHRESH*/ |
| 3303 | #define R0900_P1_HYSTTHRESH 0xf554 | 3457 | #define R0900_P1_HYSTTHRESH 0xf554 |
| 3304 | #define F0900_P1_UNLCK_THRESH 0xf55400f0 | 3458 | #define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH) |
| 3305 | #define F0900_P1_DELIN_LCK_THRESH 0xf554000f | 3459 | #define F0900_P1_UNLCK_THRESH 0xf55400f0 |
| 3460 | #define F0900_P1_DELIN_LCK_THRESH 0xf554000f | ||
| 3306 | 3461 | ||
| 3307 | /*P1_ISIENTRY*/ | 3462 | /*P1_ISIENTRY*/ |
| 3308 | #define R0900_P1_ISIENTRY 0xf55e | 3463 | #define R0900_P1_ISIENTRY 0xf55e |
| 3309 | #define F0900_P1_ISI_ENTRY 0xf55e00ff | 3464 | #define ISIENTRY REGx(R0900_P1_ISIENTRY) |
| 3465 | #define F0900_P1_ISI_ENTRY 0xf55e00ff | ||
| 3310 | 3466 | ||
| 3311 | /*P1_ISIBITENA*/ | 3467 | /*P1_ISIBITENA*/ |
| 3312 | #define R0900_P1_ISIBITENA 0xf55f | 3468 | #define R0900_P1_ISIBITENA 0xf55f |
| 3313 | #define F0900_P1_ISI_BIT_EN 0xf55f00ff | 3469 | #define ISIBITENA REGx(R0900_P1_ISIBITENA) |
| 3470 | #define F0900_P1_ISI_BIT_EN 0xf55f00ff | ||
| 3314 | 3471 | ||
| 3315 | /*P1_MATSTR1*/ | 3472 | /*P1_MATSTR1*/ |
| 3316 | #define R0900_P1_MATSTR1 0xf560 | 3473 | #define R0900_P1_MATSTR1 0xf560 |
| 3317 | #define F0900_P1_MATYPE_CURRENT1 0xf56000ff | 3474 | #define MATSTR1 REGx(R0900_P1_MATSTR1) |
| 3475 | #define F0900_P1_MATYPE_CURRENT1 0xf56000ff | ||
| 3318 | 3476 | ||
| 3319 | /*P1_MATSTR0*/ | 3477 | /*P1_MATSTR0*/ |
| 3320 | #define R0900_P1_MATSTR0 0xf561 | 3478 | #define R0900_P1_MATSTR0 0xf561 |
| 3321 | #define F0900_P1_MATYPE_CURRENT0 0xf56100ff | 3479 | #define MATSTR0 REGx(R0900_P1_MATSTR0) |
| 3480 | #define F0900_P1_MATYPE_CURRENT0 0xf56100ff | ||
| 3322 | 3481 | ||
| 3323 | /*P1_UPLSTR1*/ | 3482 | /*P1_UPLSTR1*/ |
| 3324 | #define R0900_P1_UPLSTR1 0xf562 | 3483 | #define R0900_P1_UPLSTR1 0xf562 |
| 3325 | #define F0900_P1_UPL_CURRENT1 0xf56200ff | 3484 | #define UPLSTR1 REGx(R0900_P1_UPLSTR1) |
| 3485 | #define F0900_P1_UPL_CURRENT1 0xf56200ff | ||
| 3326 | 3486 | ||
| 3327 | /*P1_UPLSTR0*/ | 3487 | /*P1_UPLSTR0*/ |
| 3328 | #define R0900_P1_UPLSTR0 0xf563 | 3488 | #define R0900_P1_UPLSTR0 0xf563 |
| 3329 | #define F0900_P1_UPL_CURRENT0 0xf56300ff | 3489 | #define UPLSTR0 REGx(R0900_P1_UPLSTR0) |
| 3490 | #define F0900_P1_UPL_CURRENT0 0xf56300ff | ||
| 3330 | 3491 | ||
| 3331 | /*P1_DFLSTR1*/ | 3492 | /*P1_DFLSTR1*/ |
| 3332 | #define R0900_P1_DFLSTR1 0xf564 | 3493 | #define R0900_P1_DFLSTR1 0xf564 |
| 3333 | #define F0900_P1_DFL_CURRENT1 0xf56400ff | 3494 | #define DFLSTR1 REGx(R0900_P1_DFLSTR1) |
| 3495 | #define F0900_P1_DFL_CURRENT1 0xf56400ff | ||
| 3334 | 3496 | ||
| 3335 | /*P1_DFLSTR0*/ | 3497 | /*P1_DFLSTR0*/ |
| 3336 | #define R0900_P1_DFLSTR0 0xf565 | 3498 | #define R0900_P1_DFLSTR0 0xf565 |
| 3337 | #define F0900_P1_DFL_CURRENT0 0xf56500ff | 3499 | #define DFLSTR0 REGx(R0900_P1_DFLSTR0) |
| 3500 | #define F0900_P1_DFL_CURRENT0 0xf56500ff | ||
| 3338 | 3501 | ||
| 3339 | /*P1_SYNCSTR*/ | 3502 | /*P1_SYNCSTR*/ |
| 3340 | #define R0900_P1_SYNCSTR 0xf566 | 3503 | #define R0900_P1_SYNCSTR 0xf566 |
| 3341 | #define F0900_P1_SYNC_CURRENT 0xf56600ff | 3504 | #define SYNCSTR REGx(R0900_P1_SYNCSTR) |
| 3505 | #define F0900_P1_SYNC_CURRENT 0xf56600ff | ||
| 3342 | 3506 | ||
| 3343 | /*P1_SYNCDSTR1*/ | 3507 | /*P1_SYNCDSTR1*/ |
| 3344 | #define R0900_P1_SYNCDSTR1 0xf567 | 3508 | #define R0900_P1_SYNCDSTR1 0xf567 |
| 3345 | #define F0900_P1_SYNCD_CURRENT1 0xf56700ff | 3509 | #define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1) |
| 3510 | #define F0900_P1_SYNCD_CURRENT1 0xf56700ff | ||
| 3346 | 3511 | ||
| 3347 | /*P1_SYNCDSTR0*/ | 3512 | /*P1_SYNCDSTR0*/ |
| 3348 | #define R0900_P1_SYNCDSTR0 0xf568 | 3513 | #define R0900_P1_SYNCDSTR0 0xf568 |
| 3349 | #define F0900_P1_SYNCD_CURRENT0 0xf56800ff | 3514 | #define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0) |
| 3515 | #define F0900_P1_SYNCD_CURRENT0 0xf56800ff | ||
| 3350 | 3516 | ||
| 3351 | /*P1_PDELSTATUS1*/ | 3517 | /*P1_PDELSTATUS1*/ |
| 3352 | #define R0900_P1_PDELSTATUS1 0xf569 | 3518 | #define R0900_P1_PDELSTATUS1 0xf569 |
| 3353 | #define F0900_P1_PKTDELIN_DELOCK 0xf5690080 | 3519 | #define F0900_P1_PKTDELIN_DELOCK 0xf5690080 |
| 3354 | #define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040 | 3520 | #define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040 |
| 3355 | #define F0900_P1_CONTINUOUS_STREAM 0xf5690020 | 3521 | #define F0900_P1_CONTINUOUS_STREAM 0xf5690020 |
| 3356 | #define F0900_P1_UNACCEPTED_STREAM 0xf5690010 | 3522 | #define F0900_P1_UNACCEPTED_STREAM 0xf5690010 |
| 3357 | #define F0900_P1_BCH_ERROR_FLAG 0xf5690008 | 3523 | #define F0900_P1_BCH_ERROR_FLAG 0xf5690008 |
| 3358 | #define F0900_P1_BBHCRCKO 0xf5690004 | 3524 | #define F0900_P1_PKTDELIN_LOCK 0xf5690002 |
| 3359 | #define F0900_P1_PKTDELIN_LOCK 0xf5690002 | 3525 | #define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK) |
| 3360 | #define F0900_P1_FIRST_LOCK 0xf5690001 | 3526 | #define F0900_P1_FIRST_LOCK 0xf5690001 |
| 3361 | 3527 | ||
| 3362 | /*P1_PDELSTATUS2*/ | 3528 | /*P1_PDELSTATUS2*/ |
| 3363 | #define R0900_P1_PDELSTATUS2 0xf56a | 3529 | #define R0900_P1_PDELSTATUS2 0xf56a |
| 3364 | #define F0900_P1_PKTDEL_DEMODSEL 0xf56a0080 | 3530 | #define F0900_P1_FRAME_MODCOD 0xf56a007c |
| 3365 | #define F0900_P1_FRAME_MODCOD 0xf56a007c | 3531 | #define F0900_P1_FRAME_TYPE 0xf56a0003 |
| 3366 | #define F0900_P1_FRAME_TYPE 0xf56a0003 | ||
| 3367 | 3532 | ||
| 3368 | /*P1_BBFCRCKO1*/ | 3533 | /*P1_BBFCRCKO1*/ |
| 3369 | #define R0900_P1_BBFCRCKO1 0xf56b | 3534 | #define R0900_P1_BBFCRCKO1 0xf56b |
| 3370 | #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff | 3535 | #define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1) |
| 3536 | #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff | ||
| 3371 | 3537 | ||
| 3372 | /*P1_BBFCRCKO0*/ | 3538 | /*P1_BBFCRCKO0*/ |
| 3373 | #define R0900_P1_BBFCRCKO0 0xf56c | 3539 | #define R0900_P1_BBFCRCKO0 0xf56c |
| 3374 | #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff | 3540 | #define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0) |
| 3541 | #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff | ||
| 3375 | 3542 | ||
| 3376 | /*P1_UPCRCKO1*/ | 3543 | /*P1_UPCRCKO1*/ |
| 3377 | #define R0900_P1_UPCRCKO1 0xf56d | 3544 | #define R0900_P1_UPCRCKO1 0xf56d |
| 3378 | #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff | 3545 | #define UPCRCKO1 REGx(R0900_P1_UPCRCKO1) |
| 3546 | #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff | ||
| 3379 | 3547 | ||
| 3380 | /*P1_UPCRCKO0*/ | 3548 | /*P1_UPCRCKO0*/ |
| 3381 | #define R0900_P1_UPCRCKO0 0xf56e | 3549 | #define R0900_P1_UPCRCKO0 0xf56e |
| 3382 | #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff | 3550 | #define UPCRCKO0 REGx(R0900_P1_UPCRCKO0) |
| 3551 | #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff | ||
| 3552 | |||
| 3553 | /*P1_PDELCTRL3*/ | ||
| 3554 | #define R0900_P1_PDELCTRL3 0xf56f | ||
| 3555 | #define PDELCTRL3 REGx(R0900_P1_PDELCTRL3) | ||
| 3556 | #define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080 | ||
| 3557 | #define F0900_P1_NOFIFO_BCHERR 0xf56f0020 | ||
| 3383 | 3558 | ||
| 3384 | /*P1_TSSTATEM*/ | 3559 | /*P1_TSSTATEM*/ |
| 3385 | #define R0900_P1_TSSTATEM 0xf570 | 3560 | #define R0900_P1_TSSTATEM 0xf570 |
| 3386 | #define F0900_P1_TSDIL_ON 0xf5700080 | 3561 | #define TSSTATEM REGx(R0900_P1_TSSTATEM) |
| 3387 | #define F0900_P1_TSSKIPRS_ON 0xf5700040 | 3562 | #define F0900_P1_TSDIL_ON 0xf5700080 |
| 3388 | #define F0900_P1_TSRS_ON 0xf5700020 | 3563 | #define F0900_P1_TSRS_ON 0xf5700020 |
| 3389 | #define F0900_P1_TSDESCRAMB_ON 0xf5700010 | 3564 | #define F0900_P1_TSDESCRAMB_ON 0xf5700010 |
| 3390 | #define F0900_P1_TSFRAME_MODE 0xf5700008 | 3565 | #define F0900_P1_TSFRAME_MODE 0xf5700008 |
| 3391 | #define F0900_P1_TS_DISABLE 0xf5700004 | 3566 | #define F0900_P1_TS_DISABLE 0xf5700004 |
| 3392 | #define F0900_P1_TSACM_MODE 0xf5700002 | 3567 | #define F0900_P1_TSOUT_NOSYNC 0xf5700001 |
| 3393 | #define F0900_P1_TSOUT_NOSYNC 0xf5700001 | ||
| 3394 | 3568 | ||
| 3395 | /*P1_TSCFGH*/ | 3569 | /*P1_TSCFGH*/ |
| 3396 | #define R0900_P1_TSCFGH 0xf572 | 3570 | #define R0900_P1_TSCFGH 0xf572 |
| 3397 | #define F0900_P1_TSFIFO_DVBCI 0xf5720080 | 3571 | #define TSCFGH REGx(R0900_P1_TSCFGH) |
| 3398 | #define F0900_P1_TSFIFO_SERIAL 0xf5720040 | 3572 | #define F0900_P1_TSFIFO_DVBCI 0xf5720080 |
| 3399 | #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020 | 3573 | #define F0900_P1_TSFIFO_SERIAL 0xf5720040 |
| 3400 | #define F0900_P1_TSFIFO_DUTY50 0xf5720010 | 3574 | #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020 |
| 3401 | #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008 | 3575 | #define F0900_P1_TSFIFO_DUTY50 0xf5720010 |
| 3402 | #define F0900_P1_TSFIFO_ERRMODE 0xf5720006 | 3576 | #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008 |
| 3403 | #define F0900_P1_RST_HWARE 0xf5720001 | 3577 | #define F0900_P1_TSFIFO_ERRMODE 0xf5720006 |
| 3578 | #define F0900_P1_RST_HWARE 0xf5720001 | ||
| 3579 | #define RST_HWARE FLDx(F0900_P1_RST_HWARE) | ||
| 3404 | 3580 | ||
| 3405 | /*P1_TSCFGM*/ | 3581 | /*P1_TSCFGM*/ |
| 3406 | #define R0900_P1_TSCFGM 0xf573 | 3582 | #define R0900_P1_TSCFGM 0xf573 |
| 3407 | #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0 | 3583 | #define TSCFGM REGx(R0900_P1_TSCFGM) |
| 3408 | #define F0900_P1_TSFIFO_PERMDATA 0xf5730020 | 3584 | #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0 |
| 3409 | #define F0900_P1_TSFIFO_NONEWSGNL 0xf5730010 | 3585 | #define F0900_P1_TSFIFO_PERMDATA 0xf5730020 |
| 3410 | #define F0900_P1_TSFIFO_BITSPEED 0xf5730008 | 3586 | #define F0900_P1_TSFIFO_DPUNACT 0xf5730002 |
| 3411 | #define F0900_P1_NPD_SPECDVBS2 0xf5730004 | 3587 | #define F0900_P1_TSFIFO_INVDATA 0xf5730001 |
| 3412 | #define F0900_P1_TSFIFO_STOPCKDIS 0xf5730002 | ||
| 3413 | #define F0900_P1_TSFIFO_INVDATA 0xf5730001 | ||
| 3414 | 3588 | ||
| 3415 | /*P1_TSCFGL*/ | 3589 | /*P1_TSCFGL*/ |
| 3416 | #define R0900_P1_TSCFGL 0xf574 | 3590 | #define R0900_P1_TSCFGL 0xf574 |
| 3417 | #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 | 3591 | #define TSCFGL REGx(R0900_P1_TSCFGL) |
| 3418 | #define F0900_P1_BCHERROR_MODE 0xf5740030 | 3592 | #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 |
| 3419 | #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008 | 3593 | #define F0900_P1_BCHERROR_MODE 0xf5740030 |
| 3420 | #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004 | 3594 | #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008 |
| 3421 | #define F0900_P1_TSFIFO_DPUNACT 0xf5740002 | 3595 | #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004 |
| 3422 | #define F0900_P1_TSFIFO_NPDOFF 0xf5740001 | 3596 | #define F0900_P1_TSFIFO_BITSPEED 0xf5740003 |
| 3423 | 3597 | ||
| 3424 | /*P1_TSINSDELH*/ | 3598 | /*P1_TSINSDELH*/ |
| 3425 | #define R0900_P1_TSINSDELH 0xf576 | 3599 | #define R0900_P1_TSINSDELH 0xf576 |
| 3426 | #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080 | 3600 | #define TSINSDELH REGx(R0900_P1_TSINSDELH) |
| 3427 | #define F0900_P1_TSDEL_XXHEADER 0xf5760040 | 3601 | #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080 |
| 3428 | #define F0900_P1_TSDEL_BBHEADER 0xf5760020 | 3602 | #define F0900_P1_TSDEL_XXHEADER 0xf5760040 |
| 3429 | #define F0900_P1_TSDEL_DATAFIELD 0xf5760010 | 3603 | #define F0900_P1_TSDEL_BBHEADER 0xf5760020 |
| 3430 | #define F0900_P1_TSINSDEL_ISCR 0xf5760008 | 3604 | #define F0900_P1_TSDEL_DATAFIELD 0xf5760010 |
| 3431 | #define F0900_P1_TSINSDEL_NPD 0xf5760004 | 3605 | #define F0900_P1_TSINSDEL_ISCR 0xf5760008 |
| 3432 | #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002 | 3606 | #define F0900_P1_TSINSDEL_NPD 0xf5760004 |
| 3433 | #define F0900_P1_TSINSDEL_CRC8 0xf5760001 | 3607 | #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002 |
| 3608 | #define F0900_P1_TSINSDEL_CRC8 0xf5760001 | ||
| 3609 | |||
| 3610 | /*P1_TSDIVN*/ | ||
| 3611 | #define R0900_P1_TSDIVN 0xf579 | ||
| 3612 | #define TSDIVN REGx(R0900_P1_TSDIVN) | ||
| 3613 | #define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0 | ||
| 3614 | |||
| 3615 | /*P1_TSCFG4*/ | ||
| 3616 | #define R0900_P1_TSCFG4 0xf57a | ||
| 3617 | #define TSCFG4 REGx(R0900_P1_TSCFG4) | ||
| 3618 | #define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 | ||
| 3434 | 3619 | ||
| 3435 | /*P1_TSSPEED*/ | 3620 | /*P1_TSSPEED*/ |
| 3436 | #define R0900_P1_TSSPEED 0xf580 | 3621 | #define R0900_P1_TSSPEED 0xf580 |
| 3437 | #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff | 3622 | #define TSSPEED REGx(R0900_P1_TSSPEED) |
| 3623 | #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff | ||
| 3438 | 3624 | ||
| 3439 | /*P1_TSSTATUS*/ | 3625 | /*P1_TSSTATUS*/ |
| 3440 | #define R0900_P1_TSSTATUS 0xf581 | 3626 | #define R0900_P1_TSSTATUS 0xf581 |
| 3441 | #define F0900_P1_TSFIFO_LINEOK 0xf5810080 | 3627 | #define TSSTATUS REGx(R0900_P1_TSSTATUS) |
| 3442 | #define F0900_P1_TSFIFO_ERROR 0xf5810040 | 3628 | #define F0900_P1_TSFIFO_LINEOK 0xf5810080 |
| 3443 | #define F0900_P1_TSFIFO_DATA7 0xf5810020 | 3629 | #define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK) |
| 3444 | #define F0900_P1_TSFIFO_NOSYNC 0xf5810010 | 3630 | #define F0900_P1_TSFIFO_ERROR 0xf5810040 |
| 3445 | #define F0900_P1_ISCR_INITIALIZED 0xf5810008 | 3631 | #define F0900_P1_DIL_READY 0xf5810001 |
| 3446 | #define F0900_P1_ISCR_UPDATED 0xf5810004 | ||
| 3447 | #define F0900_P1_SOFFIFO_UNREGUL 0xf5810002 | ||
| 3448 | #define F0900_P1_DIL_READY 0xf5810001 | ||
| 3449 | 3632 | ||
| 3450 | /*P1_TSSTATUS2*/ | 3633 | /*P1_TSSTATUS2*/ |
| 3451 | #define R0900_P1_TSSTATUS2 0xf582 | 3634 | #define R0900_P1_TSSTATUS2 0xf582 |
| 3452 | #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080 | 3635 | #define TSSTATUS2 REGx(R0900_P1_TSSTATUS2) |
| 3453 | #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040 | 3636 | #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080 |
| 3454 | #define F0900_P1_DILXX_RESET 0xf5820020 | 3637 | #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040 |
| 3455 | #define F0900_P1_TSSERIAL_IMPOS 0xf5820010 | 3638 | #define F0900_P1_DILXX_RESET 0xf5820020 |
| 3456 | #define F0900_P1_TSFIFO_LINENOK 0xf5820008 | 3639 | #define F0900_P1_TSSERIAL_IMPOS 0xf5820010 |
| 3457 | #define F0900_P1_BITSPEED_EVENT 0xf5820004 | 3640 | #define F0900_P1_SCRAMBDETECT 0xf5820002 |
| 3458 | #define F0900_P1_SCRAMBDETECT 0xf5820002 | ||
| 3459 | #define F0900_P1_ULDTV67_FALSELOCK 0xf5820001 | ||
| 3460 | 3641 | ||
| 3461 | /*P1_TSBITRATE1*/ | 3642 | /*P1_TSBITRATE1*/ |
| 3462 | #define R0900_P1_TSBITRATE1 0xf583 | 3643 | #define R0900_P1_TSBITRATE1 0xf583 |
| 3463 | #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff | 3644 | #define TSBITRATE1 REGx(R0900_P1_TSBITRATE1) |
| 3645 | #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff | ||
| 3464 | 3646 | ||
| 3465 | /*P1_TSBITRATE0*/ | 3647 | /*P1_TSBITRATE0*/ |
| 3466 | #define R0900_P1_TSBITRATE0 0xf584 | 3648 | #define R0900_P1_TSBITRATE0 0xf584 |
| 3467 | #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff | 3649 | #define TSBITRATE0 REGx(R0900_P1_TSBITRATE0) |
| 3650 | #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff | ||
| 3468 | 3651 | ||
| 3469 | /*P1_ERRCTRL1*/ | 3652 | /*P1_ERRCTRL1*/ |
| 3470 | #define R0900_P1_ERRCTRL1 0xf598 | 3653 | #define R0900_P1_ERRCTRL1 0xf598 |
| 3471 | #define F0900_P1_ERR_SOURCE1 0xf59800f0 | 3654 | #define ERRCTRL1 REGx(R0900_P1_ERRCTRL1) |
| 3472 | #define F0900_P1_NUM_EVENT1 0xf5980007 | 3655 | #define F0900_P1_ERR_SOURCE1 0xf59800f0 |
| 3656 | #define F0900_P1_NUM_EVENT1 0xf5980007 | ||
| 3473 | 3657 | ||
| 3474 | /*P1_ERRCNT12*/ | 3658 | /*P1_ERRCNT12*/ |
| 3475 | #define R0900_P1_ERRCNT12 0xf599 | 3659 | #define R0900_P1_ERRCNT12 0xf599 |
| 3476 | #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080 | 3660 | #define ERRCNT12 REGx(R0900_P1_ERRCNT12) |
| 3477 | #define F0900_P1_ERR_CNT12 0xf599007f | 3661 | #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080 |
| 3662 | #define F0900_P1_ERR_CNT12 0xf599007f | ||
| 3663 | #define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12) | ||
| 3478 | 3664 | ||
| 3479 | /*P1_ERRCNT11*/ | 3665 | /*P1_ERRCNT11*/ |
| 3480 | #define R0900_P1_ERRCNT11 0xf59a | 3666 | #define R0900_P1_ERRCNT11 0xf59a |
| 3481 | #define F0900_P1_ERR_CNT11 0xf59a00ff | 3667 | #define ERRCNT11 REGx(R0900_P1_ERRCNT11) |
| 3668 | #define F0900_P1_ERR_CNT11 0xf59a00ff | ||
| 3669 | #define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11) | ||
| 3482 | 3670 | ||
| 3483 | /*P1_ERRCNT10*/ | 3671 | /*P1_ERRCNT10*/ |
| 3484 | #define R0900_P1_ERRCNT10 0xf59b | 3672 | #define R0900_P1_ERRCNT10 0xf59b |
| 3485 | #define F0900_P1_ERR_CNT10 0xf59b00ff | 3673 | #define ERRCNT10 REGx(R0900_P1_ERRCNT10) |
| 3674 | #define F0900_P1_ERR_CNT10 0xf59b00ff | ||
| 3675 | #define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10) | ||
| 3486 | 3676 | ||
| 3487 | /*P1_ERRCTRL2*/ | 3677 | /*P1_ERRCTRL2*/ |
| 3488 | #define R0900_P1_ERRCTRL2 0xf59c | 3678 | #define R0900_P1_ERRCTRL2 0xf59c |
| 3489 | #define F0900_P1_ERR_SOURCE2 0xf59c00f0 | 3679 | #define ERRCTRL2 REGx(R0900_P1_ERRCTRL2) |
| 3490 | #define F0900_P1_NUM_EVENT2 0xf59c0007 | 3680 | #define F0900_P1_ERR_SOURCE2 0xf59c00f0 |
| 3681 | #define F0900_P1_NUM_EVENT2 0xf59c0007 | ||
| 3491 | 3682 | ||
| 3492 | /*P1_ERRCNT22*/ | 3683 | /*P1_ERRCNT22*/ |
| 3493 | #define R0900_P1_ERRCNT22 0xf59d | 3684 | #define R0900_P1_ERRCNT22 0xf59d |
| 3494 | #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080 | 3685 | #define ERRCNT22 REGx(R0900_P1_ERRCNT22) |
| 3495 | #define F0900_P1_ERR_CNT22 0xf59d007f | 3686 | #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080 |
| 3687 | #define F0900_P1_ERR_CNT22 0xf59d007f | ||
| 3688 | #define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22) | ||
| 3496 | 3689 | ||
| 3497 | /*P1_ERRCNT21*/ | 3690 | /*P1_ERRCNT21*/ |
| 3498 | #define R0900_P1_ERRCNT21 0xf59e | 3691 | #define R0900_P1_ERRCNT21 0xf59e |
| 3499 | #define F0900_P1_ERR_CNT21 0xf59e00ff | 3692 | #define ERRCNT21 REGx(R0900_P1_ERRCNT21) |
| 3693 | #define F0900_P1_ERR_CNT21 0xf59e00ff | ||
| 3694 | #define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21) | ||
| 3500 | 3695 | ||
| 3501 | /*P1_ERRCNT20*/ | 3696 | /*P1_ERRCNT20*/ |
| 3502 | #define R0900_P1_ERRCNT20 0xf59f | 3697 | #define R0900_P1_ERRCNT20 0xf59f |
| 3503 | #define F0900_P1_ERR_CNT20 0xf59f00ff | 3698 | #define ERRCNT20 REGx(R0900_P1_ERRCNT20) |
| 3699 | #define F0900_P1_ERR_CNT20 0xf59f00ff | ||
| 3700 | #define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20) | ||
| 3504 | 3701 | ||
| 3505 | /*P1_FECSPY*/ | 3702 | /*P1_FECSPY*/ |
| 3506 | #define R0900_P1_FECSPY 0xf5a0 | 3703 | #define R0900_P1_FECSPY 0xf5a0 |
| 3507 | #define F0900_P1_SPY_ENABLE 0xf5a00080 | 3704 | #define FECSPY REGx(R0900_P1_FECSPY) |
| 3508 | #define F0900_P1_NO_SYNCBYTE 0xf5a00040 | 3705 | #define F0900_P1_SPY_ENABLE 0xf5a00080 |
| 3509 | #define F0900_P1_SERIAL_MODE 0xf5a00020 | 3706 | #define F0900_P1_NO_SYNCBYTE 0xf5a00040 |
| 3510 | #define F0900_P1_UNUSUAL_PACKET 0xf5a00010 | 3707 | #define F0900_P1_SERIAL_MODE 0xf5a00020 |
| 3511 | #define F0900_P1_BER_PACKMODE 0xf5a00008 | 3708 | #define F0900_P1_UNUSUAL_PACKET 0xf5a00010 |
| 3512 | #define F0900_P1_BERMETER_LMODE 0xf5a00002 | 3709 | #define F0900_P1_BERMETER_DATAMODE 0xf5a00008 |
| 3513 | #define F0900_P1_BERMETER_RESET 0xf5a00001 | 3710 | #define F0900_P1_BERMETER_LMODE 0xf5a00002 |
| 3711 | #define F0900_P1_BERMETER_RESET 0xf5a00001 | ||
| 3514 | 3712 | ||
| 3515 | /*P1_FSPYCFG*/ | 3713 | /*P1_FSPYCFG*/ |
| 3516 | #define R0900_P1_FSPYCFG 0xf5a1 | 3714 | #define R0900_P1_FSPYCFG 0xf5a1 |
| 3517 | #define F0900_P1_FECSPY_INPUT 0xf5a100c0 | 3715 | #define FSPYCFG REGx(R0900_P1_FSPYCFG) |
| 3518 | #define F0900_P1_RST_ON_ERROR 0xf5a10020 | 3716 | #define F0900_P1_FECSPY_INPUT 0xf5a100c0 |
| 3519 | #define F0900_P1_ONE_SHOT 0xf5a10010 | 3717 | #define F0900_P1_RST_ON_ERROR 0xf5a10020 |
| 3520 | #define F0900_P1_I2C_MODE 0xf5a1000c | 3718 | #define F0900_P1_ONE_SHOT 0xf5a10010 |
| 3521 | #define F0900_P1_SPY_HYSTERESIS 0xf5a10003 | 3719 | #define F0900_P1_I2C_MODE 0xf5a1000c |
| 3720 | #define F0900_P1_SPY_HYSTERESIS 0xf5a10003 | ||
| 3522 | 3721 | ||
| 3523 | /*P1_FSPYDATA*/ | 3722 | /*P1_FSPYDATA*/ |
| 3524 | #define R0900_P1_FSPYDATA 0xf5a2 | 3723 | #define R0900_P1_FSPYDATA 0xf5a2 |
| 3525 | #define F0900_P1_SPY_STUFFING 0xf5a20080 | 3724 | #define FSPYDATA REGx(R0900_P1_FSPYDATA) |
| 3526 | #define F0900_P1_NOERROR_PKTJITTER 0xf5a20040 | 3725 | #define F0900_P1_SPY_STUFFING 0xf5a20080 |
| 3527 | #define F0900_P1_SPY_CNULLPKT 0xf5a20020 | 3726 | #define F0900_P1_SPY_CNULLPKT 0xf5a20020 |
| 3528 | #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f | 3727 | #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f |
| 3529 | 3728 | ||
| 3530 | /*P1_FSPYOUT*/ | 3729 | /*P1_FSPYOUT*/ |
| 3531 | #define R0900_P1_FSPYOUT 0xf5a3 | 3730 | #define R0900_P1_FSPYOUT 0xf5a3 |
| 3532 | #define F0900_P1_FSPY_DIRECT 0xf5a30080 | 3731 | #define FSPYOUT REGx(R0900_P1_FSPYOUT) |
| 3533 | #define F0900_P1_SPY_OUTDATA_BUS 0xf5a30038 | 3732 | #define F0900_P1_FSPY_DIRECT 0xf5a30080 |
| 3534 | #define F0900_P1_STUFF_MODE 0xf5a30007 | 3733 | #define F0900_P1_STUFF_MODE 0xf5a30007 |
| 3535 | 3734 | ||
| 3536 | /*P1_FSTATUS*/ | 3735 | /*P1_FSTATUS*/ |
| 3537 | #define R0900_P1_FSTATUS 0xf5a4 | 3736 | #define R0900_P1_FSTATUS 0xf5a4 |
| 3538 | #define F0900_P1_SPY_ENDSIM 0xf5a40080 | 3737 | #define FSTATUS REGx(R0900_P1_FSTATUS) |
| 3539 | #define F0900_P1_VALID_SIM 0xf5a40040 | 3738 | #define F0900_P1_SPY_ENDSIM 0xf5a40080 |
| 3540 | #define F0900_P1_FOUND_SIGNAL 0xf5a40020 | 3739 | #define F0900_P1_VALID_SIM 0xf5a40040 |
| 3541 | #define F0900_P1_DSS_SYNCBYTE 0xf5a40010 | 3740 | #define F0900_P1_FOUND_SIGNAL 0xf5a40020 |
| 3542 | #define F0900_P1_RESULT_STATE 0xf5a4000f | 3741 | #define F0900_P1_DSS_SYNCBYTE 0xf5a40010 |
| 3742 | #define F0900_P1_RESULT_STATE 0xf5a4000f | ||
| 3543 | 3743 | ||
| 3544 | /*P1_FBERCPT4*/ | 3744 | /*P1_FBERCPT4*/ |
| 3545 | #define R0900_P1_FBERCPT4 0xf5a8 | 3745 | #define R0900_P1_FBERCPT4 0xf5a8 |
| 3546 | #define F0900_P1_FBERMETER_CPT4 0xf5a800ff | 3746 | #define FBERCPT4 REGx(R0900_P1_FBERCPT4) |
| 3747 | #define F0900_P1_FBERMETER_CPT4 0xf5a800ff | ||
| 3547 | 3748 | ||
| 3548 | /*P1_FBERCPT3*/ | 3749 | /*P1_FBERCPT3*/ |
| 3549 | #define R0900_P1_FBERCPT3 0xf5a9 | 3750 | #define R0900_P1_FBERCPT3 0xf5a9 |
| 3550 | #define F0900_P1_FBERMETER_CPT3 0xf5a900ff | 3751 | #define FBERCPT3 REGx(R0900_P1_FBERCPT3) |
| 3752 | #define F0900_P1_FBERMETER_CPT3 0xf5a900ff | ||
| 3551 | 3753 | ||
| 3552 | /*P1_FBERCPT2*/ | 3754 | /*P1_FBERCPT2*/ |
| 3553 | #define R0900_P1_FBERCPT2 0xf5aa | 3755 | #define R0900_P1_FBERCPT2 0xf5aa |
| 3554 | #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff | 3756 | #define FBERCPT2 REGx(R0900_P1_FBERCPT2) |
| 3757 | #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff | ||
| 3555 | 3758 | ||
| 3556 | /*P1_FBERCPT1*/ | 3759 | /*P1_FBERCPT1*/ |
| 3557 | #define R0900_P1_FBERCPT1 0xf5ab | 3760 | #define R0900_P1_FBERCPT1 0xf5ab |
| 3558 | #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff | 3761 | #define FBERCPT1 REGx(R0900_P1_FBERCPT1) |
| 3762 | #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff | ||
| 3559 | 3763 | ||
| 3560 | /*P1_FBERCPT0*/ | 3764 | /*P1_FBERCPT0*/ |
| 3561 | #define R0900_P1_FBERCPT0 0xf5ac | 3765 | #define R0900_P1_FBERCPT0 0xf5ac |
| 3562 | #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff | 3766 | #define FBERCPT0 REGx(R0900_P1_FBERCPT0) |
| 3767 | #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff | ||
| 3563 | 3768 | ||
| 3564 | /*P1_FBERERR2*/ | 3769 | /*P1_FBERERR2*/ |
| 3565 | #define R0900_P1_FBERERR2 0xf5ad | 3770 | #define R0900_P1_FBERERR2 0xf5ad |
| 3566 | #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff | 3771 | #define FBERERR2 REGx(R0900_P1_FBERERR2) |
| 3772 | #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff | ||
| 3567 | 3773 | ||
| 3568 | /*P1_FBERERR1*/ | 3774 | /*P1_FBERERR1*/ |
| 3569 | #define R0900_P1_FBERERR1 0xf5ae | 3775 | #define R0900_P1_FBERERR1 0xf5ae |
| 3570 | #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff | 3776 | #define FBERERR1 REGx(R0900_P1_FBERERR1) |
| 3777 | #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff | ||
| 3571 | 3778 | ||
| 3572 | /*P1_FBERERR0*/ | 3779 | /*P1_FBERERR0*/ |
| 3573 | #define R0900_P1_FBERERR0 0xf5af | 3780 | #define R0900_P1_FBERERR0 0xf5af |
| 3574 | #define F0900_P1_FBERMETER_ERR0 0xf5af00ff | 3781 | #define FBERERR0 REGx(R0900_P1_FBERERR0) |
| 3782 | #define F0900_P1_FBERMETER_ERR0 0xf5af00ff | ||
| 3575 | 3783 | ||
| 3576 | /*P1_FSPYBER*/ | 3784 | /*P1_FSPYBER*/ |
| 3577 | #define R0900_P1_FSPYBER 0xf5b2 | 3785 | #define R0900_P1_FSPYBER 0xf5b2 |
| 3578 | #define F0900_P1_FSPYOBS_XORREAD 0xf5b20040 | 3786 | #define FSPYBER REGx(R0900_P1_FSPYBER) |
| 3579 | #define F0900_P1_FSPYBER_OBSMODE 0xf5b20020 | 3787 | #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010 |
| 3580 | #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010 | 3788 | #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008 |
| 3581 | #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008 | 3789 | #define F0900_P1_FSPYBER_CTIME 0xf5b20007 |
| 3582 | #define F0900_P1_FSPYBER_CTIME 0xf5b20007 | 3790 | |
| 3583 | 3791 | /*RCCFG2*/ | |
| 3584 | /*RCCFGH*/ | 3792 | #define R0900_RCCFG2 0xf600 |
| 3585 | #define R0900_RCCFGH 0xf600 | ||
| 3586 | #define F0900_TSRCFIFO_DVBCI 0xf6000080 | ||
| 3587 | #define F0900_TSRCFIFO_SERIAL 0xf6000040 | ||
| 3588 | #define F0900_TSRCFIFO_DISABLE 0xf6000020 | ||
| 3589 | #define F0900_TSFIFO_2TORC 0xf6000010 | ||
| 3590 | #define F0900_TSRCFIFO_HSGNLOUT 0xf6000008 | ||
| 3591 | #define F0900_TSRCFIFO_ERRMODE 0xf6000006 | ||
| 3592 | 3793 | ||
| 3593 | /*TSGENERAL*/ | 3794 | /*TSGENERAL*/ |
| 3594 | #define R0900_TSGENERAL 0xf630 | 3795 | #define R0900_TSGENERAL 0xf630 |
| 3595 | #define F0900_TSFIFO_BCLK1ALL 0xf6300020 | 3796 | #define F0900_TSFIFO_DISTS2PAR 0xf6300040 |
| 3596 | #define F0900_MUXSTREAM_OUTMODE 0xf6300008 | 3797 | #define F0900_MUXSTREAM_OUTMODE 0xf6300008 |
| 3597 | #define F0900_TSFIFO_PERMPARAL 0xf6300006 | 3798 | #define F0900_TSFIFO_PERMPARAL 0xf6300006 |
| 3598 | #define F0900_RST_REEDSOLO 0xf6300001 | ||
| 3599 | 3799 | ||
| 3600 | /*TSGENERAL1X*/ | 3800 | /*TSGENERAL1X*/ |
| 3601 | #define R0900_TSGENERAL1X 0xf670 | 3801 | #define R0900_TSGENERAL1X 0xf670 |
| 3602 | #define F0900_TSFIFO1X_BCLK1ALL 0xf6700020 | ||
| 3603 | #define F0900_MUXSTREAM1X_OUTMODE 0xf6700008 | ||
| 3604 | #define F0900_TSFIFO1X_PERMPARAL 0xf6700006 | ||
| 3605 | #define F0900_RST1X_REEDSOLO 0xf6700001 | ||
| 3606 | 3802 | ||
| 3607 | /*NBITER_NF4*/ | 3803 | /*NBITER_NF4*/ |
| 3608 | #define R0900_NBITER_NF4 0xfa03 | 3804 | #define R0900_NBITER_NF4 0xfa03 |
| 3609 | #define F0900_NBITER_NF_QP_1_2 0xfa0300ff | 3805 | #define F0900_NBITER_NF_QP_1_2 0xfa0300ff |
| 3610 | 3806 | ||
| 3611 | /*NBITER_NF5*/ | 3807 | /*NBITER_NF5*/ |
| 3612 | #define R0900_NBITER_NF5 0xfa04 | 3808 | #define R0900_NBITER_NF5 0xfa04 |
| 3613 | #define F0900_NBITER_NF_QP_3_5 0xfa0400ff | 3809 | #define F0900_NBITER_NF_QP_3_5 0xfa0400ff |
| 3614 | 3810 | ||
| 3615 | /*NBITER_NF6*/ | 3811 | /*NBITER_NF6*/ |
| 3616 | #define R0900_NBITER_NF6 0xfa05 | 3812 | #define R0900_NBITER_NF6 0xfa05 |
| 3617 | #define F0900_NBITER_NF_QP_2_3 0xfa0500ff | 3813 | #define F0900_NBITER_NF_QP_2_3 0xfa0500ff |
| 3618 | 3814 | ||
| 3619 | /*NBITER_NF7*/ | 3815 | /*NBITER_NF7*/ |
| 3620 | #define R0900_NBITER_NF7 0xfa06 | 3816 | #define R0900_NBITER_NF7 0xfa06 |
| 3621 | #define F0900_NBITER_NF_QP_3_4 0xfa0600ff | 3817 | #define F0900_NBITER_NF_QP_3_4 0xfa0600ff |
| 3622 | 3818 | ||
| 3623 | /*NBITER_NF8*/ | 3819 | /*NBITER_NF8*/ |
| 3624 | #define R0900_NBITER_NF8 0xfa07 | 3820 | #define R0900_NBITER_NF8 0xfa07 |
| 3625 | #define F0900_NBITER_NF_QP_4_5 0xfa0700ff | 3821 | #define F0900_NBITER_NF_QP_4_5 0xfa0700ff |
| 3626 | 3822 | ||
| 3627 | /*NBITER_NF9*/ | 3823 | /*NBITER_NF9*/ |
| 3628 | #define R0900_NBITER_NF9 0xfa08 | 3824 | #define R0900_NBITER_NF9 0xfa08 |
| 3629 | #define F0900_NBITER_NF_QP_5_6 0xfa0800ff | 3825 | #define F0900_NBITER_NF_QP_5_6 0xfa0800ff |
| 3630 | 3826 | ||
| 3631 | /*NBITER_NF10*/ | 3827 | /*NBITER_NF10*/ |
| 3632 | #define R0900_NBITER_NF10 0xfa09 | 3828 | #define R0900_NBITER_NF10 0xfa09 |
| 3633 | #define F0900_NBITER_NF_QP_8_9 0xfa0900ff | 3829 | #define F0900_NBITER_NF_QP_8_9 0xfa0900ff |
| 3634 | 3830 | ||
| 3635 | /*NBITER_NF11*/ | 3831 | /*NBITER_NF11*/ |
| 3636 | #define R0900_NBITER_NF11 0xfa0a | 3832 | #define R0900_NBITER_NF11 0xfa0a |
| 3637 | #define F0900_NBITER_NF_QP_9_10 0xfa0a00ff | 3833 | #define F0900_NBITER_NF_QP_9_10 0xfa0a00ff |
| 3638 | 3834 | ||
| 3639 | /*NBITER_NF12*/ | 3835 | /*NBITER_NF12*/ |
| 3640 | #define R0900_NBITER_NF12 0xfa0b | 3836 | #define R0900_NBITER_NF12 0xfa0b |
| 3641 | #define F0900_NBITER_NF_8P_3_5 0xfa0b00ff | 3837 | #define F0900_NBITER_NF_8P_3_5 0xfa0b00ff |
| 3642 | 3838 | ||
| 3643 | /*NBITER_NF13*/ | 3839 | /*NBITER_NF13*/ |
| 3644 | #define R0900_NBITER_NF13 0xfa0c | 3840 | #define R0900_NBITER_NF13 0xfa0c |
| 3645 | #define F0900_NBITER_NF_8P_2_3 0xfa0c00ff | 3841 | #define F0900_NBITER_NF_8P_2_3 0xfa0c00ff |
| 3646 | 3842 | ||
| 3647 | /*NBITER_NF14*/ | 3843 | /*NBITER_NF14*/ |
| 3648 | #define R0900_NBITER_NF14 0xfa0d | 3844 | #define R0900_NBITER_NF14 0xfa0d |
| 3649 | #define F0900_NBITER_NF_8P_3_4 0xfa0d00ff | 3845 | #define F0900_NBITER_NF_8P_3_4 0xfa0d00ff |
| 3650 | 3846 | ||
| 3651 | /*NBITER_NF15*/ | 3847 | /*NBITER_NF15*/ |
| 3652 | #define R0900_NBITER_NF15 0xfa0e | 3848 | #define R0900_NBITER_NF15 0xfa0e |
| 3653 | #define F0900_NBITER_NF_8P_5_6 0xfa0e00ff | 3849 | #define F0900_NBITER_NF_8P_5_6 0xfa0e00ff |
| 3654 | 3850 | ||
| 3655 | /*NBITER_NF16*/ | 3851 | /*NBITER_NF16*/ |
| 3656 | #define R0900_NBITER_NF16 0xfa0f | 3852 | #define R0900_NBITER_NF16 0xfa0f |
| 3657 | #define F0900_NBITER_NF_8P_8_9 0xfa0f00ff | 3853 | #define F0900_NBITER_NF_8P_8_9 0xfa0f00ff |
| 3658 | 3854 | ||
| 3659 | /*NBITER_NF17*/ | 3855 | /*NBITER_NF17*/ |
| 3660 | #define R0900_NBITER_NF17 0xfa10 | 3856 | #define R0900_NBITER_NF17 0xfa10 |
| 3661 | #define F0900_NBITER_NF_8P_9_10 0xfa1000ff | 3857 | #define F0900_NBITER_NF_8P_9_10 0xfa1000ff |
| 3662 | 3858 | ||
| 3663 | /*NBITERNOERR*/ | 3859 | /*NBITERNOERR*/ |
| 3664 | #define R0900_NBITERNOERR 0xfa3f | 3860 | #define R0900_NBITERNOERR 0xfa3f |
| 3665 | #define F0900_NBITER_STOP_CRIT 0xfa3f000f | 3861 | #define F0900_NBITER_STOP_CRIT 0xfa3f000f |
| 3666 | 3862 | ||
| 3667 | /*GAINLLR_NF4*/ | 3863 | /*GAINLLR_NF4*/ |
| 3668 | #define R0900_GAINLLR_NF4 0xfa43 | 3864 | #define R0900_GAINLLR_NF4 0xfa43 |
| 3669 | #define F0900_GAINLLR_NF_QP_1_2 0xfa43007f | 3865 | #define F0900_GAINLLR_NF_QP_1_2 0xfa43007f |
| 3670 | 3866 | ||
| 3671 | /*GAINLLR_NF5*/ | 3867 | /*GAINLLR_NF5*/ |
| 3672 | #define R0900_GAINLLR_NF5 0xfa44 | 3868 | #define R0900_GAINLLR_NF5 0xfa44 |
| 3673 | #define F0900_GAINLLR_NF_QP_3_5 0xfa44007f | 3869 | #define F0900_GAINLLR_NF_QP_3_5 0xfa44007f |
| 3674 | 3870 | ||
| 3675 | /*GAINLLR_NF6*/ | 3871 | /*GAINLLR_NF6*/ |
| 3676 | #define R0900_GAINLLR_NF6 0xfa45 | 3872 | #define R0900_GAINLLR_NF6 0xfa45 |
| 3677 | #define F0900_GAINLLR_NF_QP_2_3 0xfa45007f | 3873 | #define F0900_GAINLLR_NF_QP_2_3 0xfa45007f |
| 3678 | 3874 | ||
| 3679 | /*GAINLLR_NF7*/ | 3875 | /*GAINLLR_NF7*/ |
| 3680 | #define R0900_GAINLLR_NF7 0xfa46 | 3876 | #define R0900_GAINLLR_NF7 0xfa46 |
| 3681 | #define F0900_GAINLLR_NF_QP_3_4 0xfa46007f | 3877 | #define F0900_GAINLLR_NF_QP_3_4 0xfa46007f |
| 3682 | 3878 | ||
| 3683 | /*GAINLLR_NF8*/ | 3879 | /*GAINLLR_NF8*/ |
| 3684 | #define R0900_GAINLLR_NF8 0xfa47 | 3880 | #define R0900_GAINLLR_NF8 0xfa47 |
| 3685 | #define F0900_GAINLLR_NF_QP_4_5 0xfa47007f | 3881 | #define F0900_GAINLLR_NF_QP_4_5 0xfa47007f |
| 3686 | 3882 | ||
| 3687 | /*GAINLLR_NF9*/ | 3883 | /*GAINLLR_NF9*/ |
| 3688 | #define R0900_GAINLLR_NF9 0xfa48 | 3884 | #define R0900_GAINLLR_NF9 0xfa48 |
| 3689 | #define F0900_GAINLLR_NF_QP_5_6 0xfa48007f | 3885 | #define F0900_GAINLLR_NF_QP_5_6 0xfa48007f |
| 3690 | 3886 | ||
| 3691 | /*GAINLLR_NF10*/ | 3887 | /*GAINLLR_NF10*/ |
| 3692 | #define R0900_GAINLLR_NF10 0xfa49 | 3888 | #define R0900_GAINLLR_NF10 0xfa49 |
| 3693 | #define F0900_GAINLLR_NF_QP_8_9 0xfa49007f | 3889 | #define F0900_GAINLLR_NF_QP_8_9 0xfa49007f |
| 3694 | 3890 | ||
| 3695 | /*GAINLLR_NF11*/ | 3891 | /*GAINLLR_NF11*/ |
| 3696 | #define R0900_GAINLLR_NF11 0xfa4a | 3892 | #define R0900_GAINLLR_NF11 0xfa4a |
| 3697 | #define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f | 3893 | #define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f |
| 3698 | 3894 | ||
| 3699 | /*GAINLLR_NF12*/ | 3895 | /*GAINLLR_NF12*/ |
| 3700 | #define R0900_GAINLLR_NF12 0xfa4b | 3896 | #define R0900_GAINLLR_NF12 0xfa4b |
| 3701 | #define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f | 3897 | #define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f |
| 3702 | 3898 | ||
| 3703 | /*GAINLLR_NF13*/ | 3899 | /*GAINLLR_NF13*/ |
| 3704 | #define R0900_GAINLLR_NF13 0xfa4c | 3900 | #define R0900_GAINLLR_NF13 0xfa4c |
| 3705 | #define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f | 3901 | #define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f |
| 3706 | 3902 | ||
| 3707 | /*GAINLLR_NF14*/ | 3903 | /*GAINLLR_NF14*/ |
| 3708 | #define R0900_GAINLLR_NF14 0xfa4d | 3904 | #define R0900_GAINLLR_NF14 0xfa4d |
| 3709 | #define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f | 3905 | #define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f |
| 3710 | 3906 | ||
| 3711 | /*GAINLLR_NF15*/ | 3907 | /*GAINLLR_NF15*/ |
| 3712 | #define R0900_GAINLLR_NF15 0xfa4e | 3908 | #define R0900_GAINLLR_NF15 0xfa4e |
| 3713 | #define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f | 3909 | #define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f |
| 3714 | 3910 | ||
| 3715 | /*GAINLLR_NF16*/ | 3911 | /*GAINLLR_NF16*/ |
| 3716 | #define R0900_GAINLLR_NF16 0xfa4f | 3912 | #define R0900_GAINLLR_NF16 0xfa4f |
| 3717 | #define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f | 3913 | #define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f |
| 3718 | 3914 | ||
| 3719 | /*GAINLLR_NF17*/ | 3915 | /*GAINLLR_NF17*/ |
| 3720 | #define R0900_GAINLLR_NF17 0xfa50 | 3916 | #define R0900_GAINLLR_NF17 0xfa50 |
| 3721 | #define F0900_GAINLLR_NF_8P_9_10 0xfa50007f | 3917 | #define F0900_GAINLLR_NF_8P_9_10 0xfa50007f |
| 3722 | 3918 | ||
| 3723 | /*CFGEXT*/ | 3919 | /*CFGEXT*/ |
| 3724 | #define R0900_CFGEXT 0xfa80 | 3920 | #define R0900_CFGEXT 0xfa80 |
| 3725 | #define F0900_STAGMODE 0xfa800080 | 3921 | #define F0900_STAGMODE 0xfa800080 |
| 3726 | #define F0900_BYPBCH 0xfa800040 | 3922 | #define F0900_BYPBCH 0xfa800040 |
| 3727 | #define F0900_BYPLDPC 0xfa800020 | 3923 | #define F0900_BYPLDPC 0xfa800020 |
| 3728 | #define F0900_LDPCMODE 0xfa800010 | 3924 | #define F0900_LDPCMODE 0xfa800010 |
| 3729 | #define F0900_INVLLRSIGN 0xfa800008 | 3925 | #define F0900_INVLLRSIGN 0xfa800008 |
| 3730 | #define F0900_SHORTMULT 0xfa800004 | 3926 | #define F0900_SHORTMULT 0xfa800004 |
| 3731 | #define F0900_EXTERNTX 0xfa800001 | 3927 | #define F0900_EXTERNTX 0xfa800001 |
| 3732 | 3928 | ||
| 3733 | /*GENCFG*/ | 3929 | /*GENCFG*/ |
| 3734 | #define R0900_GENCFG 0xfa86 | 3930 | #define R0900_GENCFG 0xfa86 |
| 3735 | #define F0900_BROADCAST 0xfa860010 | 3931 | #define F0900_BROADCAST 0xfa860010 |
| 3736 | #define F0900_NOSHFRD2 0xfa860008 | 3932 | #define F0900_PRIORITY 0xfa860002 |
| 3737 | #define F0900_BCHERRFLAG 0xfa860004 | 3933 | #define F0900_DDEMOD 0xfa860001 |
| 3738 | #define F0900_PRIORITY 0xfa860002 | ||
| 3739 | #define F0900_DDEMOD 0xfa860001 | ||
| 3740 | 3934 | ||
| 3741 | /*LDPCERR1*/ | 3935 | /*LDPCERR1*/ |
| 3742 | #define R0900_LDPCERR1 0xfa96 | 3936 | #define R0900_LDPCERR1 0xfa96 |
| 3743 | #define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff | 3937 | #define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff |
| 3744 | 3938 | ||
| 3745 | /*LDPCERR0*/ | 3939 | /*LDPCERR0*/ |
| 3746 | #define R0900_LDPCERR0 0xfa97 | 3940 | #define R0900_LDPCERR0 0xfa97 |
| 3747 | #define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff | 3941 | #define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff |
| 3748 | 3942 | ||
| 3749 | /*BCHERR*/ | 3943 | /*BCHERR*/ |
| 3750 | #define R0900_BCHERR 0xfa98 | 3944 | #define R0900_BCHERR 0xfa98 |
| 3751 | #define F0900_ERRORFLAG 0xfa980010 | 3945 | #define F0900_ERRORFLAG 0xfa980010 |
| 3752 | #define F0900_BCH_ERRORS_COUNTER 0xfa98000f | 3946 | #define F0900_BCH_ERRORS_COUNTER 0xfa98000f |
| 3753 | 3947 | ||
| 3754 | /*TSTRES0*/ | 3948 | /*TSTRES0*/ |
| 3755 | #define R0900_TSTRES0 0xff11 | 3949 | #define R0900_TSTRES0 0xff11 |
| 3756 | #define F0900_FRESFEC 0xff110080 | 3950 | #define F0900_FRESFEC 0xff110080 |
| 3757 | #define F0900_FRESTS 0xff110040 | 3951 | |
| 3758 | #define F0900_FRESVIT1 0xff110020 | 3952 | /*P2_TCTL4*/ |
| 3759 | #define F0900_FRESVIT2 0xff110010 | 3953 | #define R0900_P2_TCTL4 0xff28 |
| 3760 | #define F0900_FRESSYM1 0xff110008 | 3954 | #define F0900_P2_PN4_SELECT 0xff280020 |
| 3761 | #define F0900_FRESSYM2 0xff110004 | 3955 | |
| 3762 | #define F0900_FRESMAS 0xff110002 | 3956 | /*P1_TCTL4*/ |
| 3763 | #define F0900_FRESINT 0xff110001 | 3957 | #define R0900_P1_TCTL4 0xff48 |
| 3958 | #define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20) | ||
| 3959 | #define F0900_P1_PN4_SELECT 0xff480020 | ||
| 3764 | 3960 | ||
| 3765 | /*P2_TSTDISRX*/ | 3961 | /*P2_TSTDISRX*/ |
| 3766 | #define R0900_P2_TSTDISRX 0xff65 | 3962 | #define R0900_P2_TSTDISRX 0xff65 |
| 3767 | #define F0900_P2_EN_DISRX 0xff650080 | 3963 | #define F0900_P2_PIN_SELECT1 0xff650008 |
| 3768 | #define F0900_P2_TST_CURRSRC 0xff650040 | ||
| 3769 | #define F0900_P2_IN_DIGSIGNAL 0xff650020 | ||
| 3770 | #define F0900_P2_HIZ_CURRENTSRC 0xff650010 | ||
| 3771 | #define F0900_TST_P2_PIN_SELECT 0xff650008 | ||
| 3772 | #define F0900_P2_TST_DISRX 0xff650007 | ||
| 3773 | 3964 | ||
| 3774 | /*P1_TSTDISRX*/ | 3965 | /*P1_TSTDISRX*/ |
| 3775 | #define R0900_P1_TSTDISRX 0xff67 | 3966 | #define R0900_P1_TSTDISRX 0xff67 |
| 3776 | #define F0900_P1_EN_DISRX 0xff670080 | 3967 | #define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2) |
| 3777 | #define F0900_P1_TST_CURRSRC 0xff670040 | 3968 | #define F0900_P1_PIN_SELECT1 0xff670008 |
| 3778 | #define F0900_P1_IN_DIGSIGNAL 0xff670020 | 3969 | #define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000) |
| 3779 | #define F0900_P1_HIZ_CURRENTSRC 0xff670010 | 3970 | |
| 3780 | #define F0900_TST_P1_PIN_SELECT 0xff670008 | 3971 | #define STV0900_NBREGS 723 |
| 3781 | #define F0900_P1_TST_DISRX 0xff670007 | 3972 | #define STV0900_NBFIELDS 1420 |
| 3782 | |||
| 3783 | #define STV0900_NBREGS 684 | ||
| 3784 | #define STV0900_NBFIELDS 1702 | ||
| 3785 | 3973 | ||
| 3786 | #endif | 3974 | #endif |
| 3787 | 3975 | ||