diff options
author | Mythri P K <mythripk@ti.com> | 2011-09-08 09:36:19 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-09-30 09:16:31 -0400 |
commit | 7b27da548389cede637653033211369a2c9678f7 (patch) | |
tree | 68b7482d61fa2e2048b8e38519a8405878d77ab8 /drivers | |
parent | 95a8aeb6c56ec80fb847e44328e3b53b9934dcbf (diff) |
OMAP4: DSS2: HDMI: Move pll and video configuration
As the pll and the video configuration info are part of the ip_data, pll
and video structures are moved to the ip_data structure. Also the pll and
video configuration functions are modified accordingly to take care of the
structure movement.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/video/omap2/dss/dss.h | 8 | ||||
-rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 42 | ||||
-rw-r--r-- | drivers/video/omap2/dss/hdmi.h | 25 |
3 files changed, 37 insertions, 38 deletions
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index eb716521d775..6aeb1f5505d0 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h | |||
@@ -155,6 +155,13 @@ struct dsi_clock_info { | |||
155 | bool use_sys_clk; | 155 | bool use_sys_clk; |
156 | }; | 156 | }; |
157 | 157 | ||
158 | enum hdmi_clk_refsel { | ||
159 | HDMI_REFSEL_PCLK = 0, | ||
160 | HDMI_REFSEL_REF1 = 1, | ||
161 | HDMI_REFSEL_REF2 = 2, | ||
162 | HDMI_REFSEL_SYSCLK = 3 | ||
163 | }; | ||
164 | |||
158 | /* HDMI PLL structure */ | 165 | /* HDMI PLL structure */ |
159 | struct hdmi_pll_info { | 166 | struct hdmi_pll_info { |
160 | u16 regn; | 167 | u16 regn; |
@@ -163,6 +170,7 @@ struct hdmi_pll_info { | |||
163 | u16 regm2; | 170 | u16 regm2; |
164 | u16 regsd; | 171 | u16 regsd; |
165 | u16 dcofreq; | 172 | u16 dcofreq; |
173 | enum hdmi_clk_refsel refsel; | ||
166 | }; | 174 | }; |
167 | 175 | ||
168 | struct seq_file; | 176 | struct seq_file; |
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index bfd113ce3b47..47e9f4abe322 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
@@ -59,7 +59,6 @@ static struct { | |||
59 | u8 edid[HDMI_EDID_MAX_LENGTH]; | 59 | u8 edid[HDMI_EDID_MAX_LENGTH]; |
60 | u8 edid_set; | 60 | u8 edid_set; |
61 | bool custom_set; | 61 | bool custom_set; |
62 | struct hdmi_config cfg; | ||
63 | 62 | ||
64 | struct clk *sys_clk; | 63 | struct clk *sys_clk; |
65 | } hdmi; | 64 | } hdmi; |
@@ -229,12 +228,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev) | |||
229 | return 0; | 228 | return 0; |
230 | } | 229 | } |
231 | 230 | ||
232 | static int hdmi_pll_init(struct hdmi_ip_data *ip_data, | 231 | static int hdmi_pll_init(struct hdmi_ip_data *ip_data) |
233 | enum hdmi_clk_refsel refsel, int dcofreq, | ||
234 | struct hdmi_pll_info *fmt, u16 sd) | ||
235 | { | 232 | { |
236 | u32 r; | 233 | u32 r; |
237 | void __iomem *pll_base = hdmi_pll_base(ip_data); | 234 | void __iomem *pll_base = hdmi_pll_base(ip_data); |
235 | struct hdmi_pll_info *fmt = &ip_data->pll_data; | ||
238 | 236 | ||
239 | /* PLL start always use manual mode */ | 237 | /* PLL start always use manual mode */ |
240 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); | 238 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); |
@@ -250,10 +248,11 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data, | |||
250 | r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ | 248 | r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ |
251 | r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ | 249 | r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ |
252 | r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ | 250 | r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ |
251 | r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ | ||
253 | 252 | ||
254 | if (dcofreq) { | 253 | if (fmt->dcofreq) { |
255 | /* divider programming for frequency beyond 1000Mhz */ | 254 | /* divider programming for frequency beyond 1000Mhz */ |
256 | REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); | 255 | REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); |
257 | r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ | 256 | r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ |
258 | } else { | 257 | } else { |
259 | r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ | 258 | r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ |
@@ -379,11 +378,9 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data) | |||
379 | return 0; | 378 | return 0; |
380 | } | 379 | } |
381 | 380 | ||
382 | static int hdmi_pll_program(struct hdmi_ip_data *ip_data, | 381 | static int hdmi_pll_program(struct hdmi_ip_data *ip_data) |
383 | struct hdmi_pll_info *fmt) | ||
384 | { | 382 | { |
385 | u16 r = 0; | 383 | u16 r = 0; |
386 | enum hdmi_clk_refsel refsel; | ||
387 | 384 | ||
388 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); | 385 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); |
389 | if (r) | 386 | if (r) |
@@ -397,9 +394,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, | |||
397 | if (r) | 394 | if (r) |
398 | return r; | 395 | return r; |
399 | 396 | ||
400 | refsel = HDMI_REFSEL_SYSCLK; | 397 | r = hdmi_pll_init(ip_data); |
401 | |||
402 | r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); | ||
403 | if (r) | 398 | if (r) |
404 | return r; | 399 | return r; |
405 | 400 | ||
@@ -1015,8 +1010,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, | |||
1015 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); | 1010 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); |
1016 | } | 1011 | } |
1017 | 1012 | ||
1018 | static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, | 1013 | static void hdmi_basic_configure(struct hdmi_ip_data *ip_data) |
1019 | struct hdmi_config *cfg) | ||
1020 | { | 1014 | { |
1021 | /* HDMI */ | 1015 | /* HDMI */ |
1022 | struct omap_video_timings video_timing; | 1016 | struct omap_video_timings video_timing; |
@@ -1026,6 +1020,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, | |||
1026 | struct hdmi_core_infoframe_avi avi_cfg; | 1020 | struct hdmi_core_infoframe_avi avi_cfg; |
1027 | struct hdmi_core_video_config v_core_cfg; | 1021 | struct hdmi_core_video_config v_core_cfg; |
1028 | struct hdmi_core_packet_enable_repeat repeat_cfg; | 1022 | struct hdmi_core_packet_enable_repeat repeat_cfg; |
1023 | struct hdmi_config *cfg = &ip_data->cfg; | ||
1029 | 1024 | ||
1030 | hdmi_wp_init(&video_timing, &video_format, | 1025 | hdmi_wp_init(&video_timing, &video_format, |
1031 | &video_interface); | 1026 | &video_interface); |
@@ -1034,8 +1029,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, | |||
1034 | &avi_cfg, | 1029 | &avi_cfg, |
1035 | &repeat_cfg); | 1030 | &repeat_cfg); |
1036 | 1031 | ||
1037 | hdmi_wp_video_init_format(&video_format, | 1032 | hdmi_wp_video_init_format(&video_format, &video_timing, cfg); |
1038 | &video_timing, cfg); | ||
1039 | 1033 | ||
1040 | hdmi_wp_video_config_timing(ip_data, &video_timing); | 1034 | hdmi_wp_video_config_timing(ip_data, &video_timing); |
1041 | 1035 | ||
@@ -1154,6 +1148,9 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | |||
1154 | pi->dcofreq = phy > 1000 * 100; | 1148 | pi->dcofreq = phy > 1000 * 100; |
1155 | pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; | 1149 | pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; |
1156 | 1150 | ||
1151 | /* Set the reference clock to sysclk reference */ | ||
1152 | pi->refsel = HDMI_REFSEL_SYSCLK; | ||
1153 | |||
1157 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); | 1154 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
1158 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | 1155 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |
1159 | } | 1156 | } |
@@ -1161,7 +1158,6 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | |||
1161 | static int hdmi_power_on(struct omap_dss_device *dssdev) | 1158 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
1162 | { | 1159 | { |
1163 | int r, code = 0; | 1160 | int r, code = 0; |
1164 | struct hdmi_pll_info pll_data; | ||
1165 | struct omap_video_timings *p; | 1161 | struct omap_video_timings *p; |
1166 | unsigned long phy; | 1162 | unsigned long phy; |
1167 | 1163 | ||
@@ -1183,16 +1179,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) | |||
1183 | } | 1179 | } |
1184 | code = get_timings_index(); | 1180 | code = get_timings_index(); |
1185 | dssdev->panel.timings = cea_vesa_timings[code].timings; | 1181 | dssdev->panel.timings = cea_vesa_timings[code].timings; |
1186 | update_hdmi_timings(&hdmi.cfg, p, code); | 1182 | update_hdmi_timings(&hdmi.ip_data.cfg, p, code); |
1187 | 1183 | ||
1188 | phy = p->pixel_clock; | 1184 | phy = p->pixel_clock; |
1189 | 1185 | ||
1190 | hdmi_compute_pll(dssdev, phy, &pll_data); | 1186 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
1191 | 1187 | ||
1192 | hdmi_wp_video_start(&hdmi.ip_data, 0); | 1188 | hdmi_wp_video_start(&hdmi.ip_data, 0); |
1193 | 1189 | ||
1194 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ | 1190 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
1195 | r = hdmi_pll_program(&hdmi.ip_data, &pll_data); | 1191 | r = hdmi_pll_program(&hdmi.ip_data); |
1196 | if (r) { | 1192 | if (r) { |
1197 | DSSDBG("Failed to lock PLL\n"); | 1193 | DSSDBG("Failed to lock PLL\n"); |
1198 | goto err; | 1194 | goto err; |
@@ -1204,9 +1200,9 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) | |||
1204 | goto err; | 1200 | goto err; |
1205 | } | 1201 | } |
1206 | 1202 | ||
1207 | hdmi.cfg.cm.mode = hdmi.mode; | 1203 | hdmi.ip_data.cfg.cm.mode = hdmi.mode; |
1208 | hdmi.cfg.cm.code = hdmi.code; | 1204 | hdmi.ip_data.cfg.cm.code = hdmi.code; |
1209 | hdmi_basic_configure(&hdmi.ip_data, &hdmi.cfg); | 1205 | hdmi_basic_configure(&hdmi.ip_data); |
1210 | 1206 | ||
1211 | /* Make selection of HDMI in DSS */ | 1207 | /* Make selection of HDMI in DSS */ |
1212 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | 1208 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); |
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index ee37bd932116..d2913f8ee003 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h | |||
@@ -218,13 +218,6 @@ enum hdmi_pll_pwr { | |||
218 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | 218 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 |
219 | }; | 219 | }; |
220 | 220 | ||
221 | enum hdmi_clk_refsel { | ||
222 | HDMI_REFSEL_PCLK = 0, | ||
223 | HDMI_REFSEL_REF1 = 1, | ||
224 | HDMI_REFSEL_REF2 = 2, | ||
225 | HDMI_REFSEL_SYSCLK = 3 | ||
226 | }; | ||
227 | |||
228 | enum hdmi_core_inputbus_width { | 221 | enum hdmi_core_inputbus_width { |
229 | HDMI_INPUT_8BIT = 0, | 222 | HDMI_INPUT_8BIT = 0, |
230 | HDMI_INPUT_10BIT = 1, | 223 | HDMI_INPUT_10BIT = 1, |
@@ -558,14 +551,6 @@ struct hdmi_video_interface { | |||
558 | int tm; /* Timing mode */ | 551 | int tm; /* Timing mode */ |
559 | }; | 552 | }; |
560 | 553 | ||
561 | struct hdmi_ip_data { | ||
562 | void __iomem *base_wp; /* HDMI wrapper */ | ||
563 | unsigned long core_sys_offset; | ||
564 | unsigned long core_av_offset; | ||
565 | unsigned long pll_offset; | ||
566 | unsigned long phy_offset; | ||
567 | }; | ||
568 | |||
569 | struct hdmi_cm { | 554 | struct hdmi_cm { |
570 | int code; | 555 | int code; |
571 | int mode; | 556 | int mode; |
@@ -577,6 +562,16 @@ struct hdmi_config { | |||
577 | struct hdmi_cm cm; | 562 | struct hdmi_cm cm; |
578 | }; | 563 | }; |
579 | 564 | ||
565 | struct hdmi_ip_data { | ||
566 | void __iomem *base_wp; /* HDMI wrapper */ | ||
567 | unsigned long core_sys_offset; | ||
568 | unsigned long core_av_offset; | ||
569 | unsigned long pll_offset; | ||
570 | unsigned long phy_offset; | ||
571 | struct hdmi_config cfg; | ||
572 | struct hdmi_pll_info pll_data; | ||
573 | }; | ||
574 | |||
580 | struct hdmi_audio_format { | 575 | struct hdmi_audio_format { |
581 | enum hdmi_stereo_channels stereo_channels; | 576 | enum hdmi_stereo_channels stereo_channels; |
582 | u8 active_chnnls_msk; | 577 | u8 active_chnnls_msk; |