litmus-rt.git - The LITMUS^RT kernel.

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author	Abhilash K V <abhilash.kv@ti.com>	2011-08-22 23:05:48 -0400
committer	David S. Miller <davem@davemloft.net>	2011-08-26 12:48:24 -0400
commit	6f288cc52f478e6f58d96158e7cd857fedb6d111 (patch)
tree	b4d145d3b0de634f502f50f89febe193a1f93dee /drivers
parent	69558eeeaba7d79364bb9ac4743dc1ad209508b7 (diff)

can: ti_hecc: Fix unintialized variable

In ti_hecc_xmit(), local variable "data" is not initialized before being used. This initialization got inadvertently removed in the following patch: can: Unify droping of invalid tx skbs and netdev stats Acked-by: Anant Gole <anantgole@ti.com> Signed-off-by: Abhilash K V <abhilash.kv@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>

Diffstat (limited to 'drivers')

-rw-r--r--

drivers/net/can/ti_hecc.c

1 files changed, 1 insertions, 1 deletions

         spin_unlock_irqrestore(&priv->mbx_lock, flags);
         /* Prepare mailbox for transmission */
+        data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
         if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
                 data |= HECC_CANMCF_RTR;
-        data |= get_tx_head_prio(priv) << 8;
         hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
         if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */

/*------------------------------------------------------------------------ . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device. . . Copyright (C) 2005 Sensoria Corp. . Derived from the unified SMC91x driver by Nicolas Pitre . . This program is free software; you can redistribute it and/or modify . it under the terms of the GNU General Public License as published by . the Free Software Foundation; either version 2 of the License, or . (at your option) any later version. . . This program is distributed in the hope that it will be useful, . but WITHOUT ANY WARRANTY; without even the implied warranty of . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the . GNU General Public License for more details. . . You should have received a copy of the GNU General Public License . along with this program; if not, write to the Free Software . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA . . Information contained in this file was obtained from the LAN9118 . manual from SMC. To get a copy, if you really want one, you can find . information under www.smsc.com. . . Authors . Dustin McIntire <dustin@sensoria.com> . ---------------------------------------------------------------------------*/ #ifndef _SMC911X_H_ #define _SMC911X_H_ #include <linux/smc911x.h> /* * Use the DMA feature on PXA chips */ #ifdef CONFIG_ARCH_PXA #define SMC_USE_PXA_DMA 1 #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING #elif defined(CONFIG_SH_MAGIC_PANEL_R2) #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW #elif defined(CONFIG_ARCH_OMAP34XX) #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW #define SMC_MEM_RESERVED 1 #elif defined(CONFIG_ARCH_OMAP24XX) #define SMC_USE_16BIT 0 #define SMC_USE_32BIT 1 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW #define SMC_MEM_RESERVED 1 #else /* * Default configuration */ #define SMC_DYNAMIC_BUS_CONFIG #endif #ifdef SMC_USE_PXA_DMA #define SMC_USE_DMA #endif /* store this information for the driver.. */ struct smc911x_local { /* * If I have to wait until the DMA is finished and ready to reload a * packet, I will store the skbuff here. Then, the DMA will send it * out and free it. */ struct sk_buff *pending_tx_skb; /* version/revision of the SMC911x chip */ u16 version; u16 revision; /* FIFO sizes */ int tx_fifo_kb; int tx_fifo_size; int rx_fifo_size; int afc_cfg; /* Contains the current active receive/phy mode */ int ctl_rfduplx; int ctl_rspeed; u32 msg_enable; u32 phy_type; struct mii_if_info mii; /* work queue */ struct work_struct phy_configure; int tx_throttle; spinlock_t lock; struct net_device *netdev; #ifdef SMC_USE_DMA /* DMA needs the physical address of the chip */ u_long physaddr; int rxdma; int txdma; int rxdma_active; int txdma_active; struct sk_buff *current_rx_skb; struct sk_buff *current_tx_skb; struct device *dev; #endif void __iomem *base; #ifdef SMC_DYNAMIC_BUS_CONFIG struct smc911x_platdata cfg; #endif }; /* * Define the bus width specific IO macros */ #ifdef SMC_DYNAMIC_BUS_CONFIG static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg) { void __iomem *ioaddr = lp->base + reg; if (lp->cfg.flags & SMC911X_USE_32BIT) return readl(ioaddr); if (lp->cfg.flags & SMC911X_USE_16BIT) return readw(ioaddr) | (readw(ioaddr + 2) << 16); BUG(); } static inline void SMC_outl(unsigned int value, struct smc911x_local *lp, int reg) { void __iomem *ioaddr = lp->base + reg; if (lp->cfg.flags & SMC911X_USE_32BIT) { writel(value, ioaddr); return; } if (lp->cfg.flags & SMC911X_USE_16BIT) { writew(value & 0xffff, ioaddr); writew(value >> 16, ioaddr + 2); return; } BUG(); } static inline void SMC_insl(struct smc911x_local *lp, int reg, void *addr, unsigned int count) { void __iomem *ioaddr = lp->base + reg; if (lp->cfg.flags & SMC911X_USE_32BIT) { readsl(ioaddr, addr, count); return; } if (lp->cfg.flags & SMC911X_USE_16BIT) { readsw(ioaddr, addr, count * 2); return; } BUG(); } static inline void SMC_outsl(struct smc911x_local *lp, int reg, void *addr, unsigned int count) { void __iomem *ioaddr = lp->base + reg; if (lp->cfg.flags & SMC911X_USE_32BIT) { writesl(ioaddr, addr, count); return; } if (lp->cfg.flags & SMC911X_USE_16BIT) { writesw(ioaddr, addr, count * 2); return; } BUG(); } #else #if SMC_USE_16BIT #define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16)) #define SMC_outl(v, lp, r) \ do{ \ writew(v & 0xFFFF, (lp)->base + (r)); \ writew(v >> 16, (lp)->base + (r) + 2); \ } while (0) #define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2) #define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2) #elif SMC_USE_32BIT #define SMC_inl(lp, r) readl((lp)->base + (r)) #define SMC_outl(v, lp, r) writel(v, (lp)->base + (r)) #define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l) #define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l) #endif /* SMC_USE_16BIT */ #endif /* SMC_DYNAMIC_BUS_CONFIG */ #ifdef SMC_USE_PXA_DMA #include <mach/dma.h> /* * Define the request and free functions * These are unfortunately architecture specific as no generic allocation * mechanism exits */ #define SMC_DMA_REQUEST(dev, handler) \ pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev) #define SMC_DMA_FREE(dev, dma) \ pxa_free_dma(dma) #define SMC_DMA_ACK_IRQ(dev, dma) \ { \ if (DCSR(dma) & DCSR_BUSERR) { \ printk("%s: DMA %d bus error!\n", dev->name, dma); \ } \ DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \ } /* * Use a DMA for RX and TX packets. */ #include <linux/dma-mapping.h> static dma_addr_t rx_dmabuf, tx_dmabuf; static int rx_dmalen, tx_dmalen; #ifdef SMC_insl #undef SMC_insl #define SMC_insl(lp, r, p, l) \ smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l) static inline void smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr, int reg, int dma, u_char *buf, int len) { /* 64 bit alignment is required for memory to memory DMA */ if ((long)buf & 4) { *((u32 *)buf) = SMC_inl(lp, reg); buf += 4; len--; } len *= 4; rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE); rx_dmalen = len; DCSR(dma) = DCSR_NODESC; DTADR(dma) = rx_dmabuf; DSADR(dma) = physaddr + reg; DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen)); DCSR(dma) = DCSR_NODESC | DCSR_RUN; } #endif #ifdef SMC_outsl #undef SMC_outsl #define SMC_outsl(lp, r, p, l) \ smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l) static inline void smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr, int reg, int dma, u_char *buf, int len) { /* 64 bit alignment is required for memory to memory DMA */ if ((long)buf & 4) { SMC_outl(*((u32 *)buf), lp, reg); buf += 4; len--; } len *= 4; tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE); tx_dmalen = len; DCSR(dma) = DCSR_NODESC; DSADR(dma) = tx_dmabuf; DTADR(dma) = physaddr + reg; DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen)); DCSR(dma) = DCSR_NODESC | DCSR_RUN; } #endif #endif /* SMC_USE_PXA_DMA */ /* Chip Parameters and Register Definitions */ #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2) #define SMC911X_IO_EXTENT 0x100 #define SMC911X_EEPROM_LEN 7 /* Below are the register offsets and bit definitions * of the Lan911x memory space */ #define RX_DATA_FIFO (0x00) #define TX_DATA_FIFO (0x20) #define TX_CMD_A_INT_ON_COMP_ (0x80000000) #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000) #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000) #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000) #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000) #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000) #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000) #define TX_CMD_A_INT_LAST_SEG_ (0x00001000) #define TX_CMD_A_BUF_SIZE_ (0x000007FF) #define TX_CMD_B_PKT_TAG_ (0xFFFF0000) #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) #define TX_CMD_B_DISABLE_PADDING_ (0x00001000) #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) #define RX_STATUS_FIFO (0x40) #define RX_STS_PKT_LEN_ (0x3FFF0000) #define RX_STS_ES_ (0x00008000) #define RX_STS_BCST_ (0x00002000) #define RX_STS_LEN_ERR_ (0x00001000) #define RX_STS_RUNT_ERR_ (0x00000800) #define RX_STS_MCAST_ (0x00000400) #define RX_STS_TOO_LONG_ (0x00000080) #define RX_STS_COLL_ (0x00000040) #define RX_STS_ETH_TYPE_ (0x00000020) #define RX_STS_WDOG_TMT_ (0x00000010) #define RX_STS_MII_ERR_ (0x00000008) #define RX_STS_DRIBBLING_ (0x00000004) #define RX_STS_CRC_ERR_ (0x00000002) #define RX_STATUS_FIFO_PEEK (0x44) #define TX_STATUS_FIFO (0x48) #define TX_STS_TAG_ (0xFFFF0000) #define TX_STS_ES_ (0x00008000) #define TX_STS_LOC_ (0x00000800) #define TX_STS_NO_CARR_ (0x00000400) #define TX_STS_LATE_COLL_ (0x00000200) #define TX_STS_MANY_COLL_ (0x00000100) #define TX_STS_COLL_CNT_ (0x00000078) #define TX_STS_MANY_DEFER_ (0x00000004) #define TX_STS_UNDERRUN_ (0x00000002) #define TX_STS_DEFERRED_ (0x00000001) #define TX_STATUS_FIFO_PEEK (0x4C) #define ID_REV (0x50) #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */ #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */ #define INT_CFG (0x54) #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */ #define INT_CFG_INT_DEAS_CLR_ (0x00004000) #define INT_CFG_INT_DEAS_STS_ (0x00002000) #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */ #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */ #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */ #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */ #define INT_STS (0x58) #define INT_STS_SW_INT_ (0x80000000) /* R/WC */ #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */ #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */ #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */ #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */ #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */ #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */ #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */ #define INT_STS_PHY_INT_ (0x00040000) /* RO */ #define INT_STS_PME_INT_ (0x00020000) /* R/WC */ #define INT_STS_TXSO_ (0x00010000) /* R/WC */ #define INT_STS_RWT_ (0x00008000) /* R/WC */ #define INT_STS_RXE_ (0x00004000) /* R/WC */ #define INT_STS_TXE_ (0x00002000) /* R/WC */ //#define INT_STS_ERX_ (0x00001000) /* R/WC */ #define INT_STS_TDFU_ (0x00000800) /* R/WC */ #define INT_STS_TDFO_ (0x00000400) /* R/WC */ #define INT_STS_TDFA_ (0x00000200) /* R/WC */ #define INT_STS_TSFF_ (0x00000100) /* R/WC */ #define INT_STS_TSFL_ (0x00000080) /* R/WC */ //#define INT_STS_RXDF_ (0x00000040) /* R/WC */ #define INT_STS_RDFO_ (0x00000040) /* R/WC */ #define INT_STS_RDFL_ (0x00000020) /* R/WC */ #define INT_STS_RSFF_ (0x00000010) /* R/WC */ #define INT_STS_RSFL_ (0x00000008) /* R/WC */ #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */ #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */ #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */ #define INT_EN (0x5C) #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */ #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */ #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */ #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */ //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */ #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */ #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */ #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */ #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */ #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */ #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */ #define INT_EN_RWT_EN_ (0x00008000) /* R/W */ #define INT_EN_RXE_EN_ (0x00004000) /* R/W */ #define INT_EN_TXE_EN_ (0x00002000) /* R/W */ //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */ #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */ #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */ #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */ #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */ #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */ //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */ #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */ #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */ #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */ #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */ #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */ #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */ #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */ #define BYTE_TEST (0x64) #define FIFO_INT (0x68) #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */ #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */ #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */ #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */ #define RX_CFG (0x6C) #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */ #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */ #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */ #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */ #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */ #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */ #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */ //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */ #define TX_CFG (0x70) //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */ //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */ #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */ #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */ #define TX_CFG_TXSAO_ (0x00000004) /* R/W */ #define TX_CFG_TX_ON_ (0x00000002) /* R/W */ #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */ #define HW_CFG (0x74) #define HW_CFG_TTM_ (0x00200000) /* R/W */ #define HW_CFG_SF_ (0x00100000) /* R/W */ #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */ #define HW_CFG_TR_ (0x00003000) /* R/W */ #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */ #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */ #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */ #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */ #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */ #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */ #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */ #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */ #define HW_CFG_SRST_TO_ (0x00000002) /* RO */ #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */ #define RX_DP_CTRL (0x78) #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */ #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */ #define RX_FIFO_INF (0x7C) #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */ #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */ #define TX_FIFO_INF (0x80) #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */ #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */ #define PMT_CTRL (0x84) #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */ #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */ #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */ #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */ #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */


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